Semiconductor package

Abstract

The embodiment of the utility model provides a semiconductor package. A semiconductor device includes a first die over a substrate and including a first via extending through a first semiconductor substrate, a second die laterally displaced relative to the first die and including a second via extending through a second semiconductor substrate, a first die spacer protruding between the first and second dies and over the first substrate, an insulating layer over the first and second vias and the first die spacer and surrounding sidewalls of the first and second vias and the first die spacer, a third die over the first and second dies and electrically connected to the first die, a semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a third die laterally displaced with respect to the first semiconductor substrate, a fourth die laterally displaced with respect to the third die, and a second die spacer between the third and fourth dies, the first via protruding over the first semiconductor substrate, the second via protruding over the second semiconductor substrate, a lowermost surface of the third and fourth dies being flush with a lowermost surface of the second die spacer.

Description

Technical Field

[0001] Embodiments of the utility model relate to a semiconductor package, and more particularly to a semiconductor package including stacked dies. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, and the like). In large part, the improvement in integration density stems from the continuous reduction in minimum feature size, which enables more components to be integrated into a given area. As the demand for ever-shrinking electronic devices grows, the need for smaller and more innovative semiconductor die packaging technologies has emerged.

[0003] As semiconductor technology has advanced, stacked semiconductor devices and bonded semiconductor devices have emerged as effective alternatives to further reduce the physical size of semiconductor devices. In a stacked semiconductor device, active circuits (such as logic circuits, memory circuits, processor circuits, and the like) are at least partially fabricated on separate substrates and then physically and electrically bonded together to form a functional device. This bonding process utilizes complex techniques and improvements are expected. Utility Model Content

[0004] An embodiment of the utility model provides a semiconductor package including a first tube core located on a first substrate, a second tube core located on the substrate and laterally displaced relative to the first tube core, a first tube core spacer located on the substrate and between the first tube core and the second tube core, an insulating layer, a third tube core located on the first tube core and the second tube core, a fourth tube core displaced laterally relative to the third tube core, and a second tube core spacer located between the third tube core and the fourth tube core. The first tube core includes a first conductive via extending through the first semiconductor substrate, and the first conductive via protrudes a first height above the first semiconductor substrate. The second tube core includes a second conductive via extending through the second semiconductor substrate, and the second conductive via protrudes a second height above the second semiconductor substrate. The first tube core spacer protrudes a third height above the first substrate. The insulating layer is located on the first conductive via, the second conductive via, and the first tube core spacer and surrounds the sidewall of the first conductive via, the sidewall of the second conductive via, and the sidewall of the first tube core spacer. The third tube core is electrically connected to the first tube core. A lowermost surface of the third die, a lowermost surface of the fourth die, and a lowermost surface of the second die spacer are flush.

[0005] An embodiment of the utility model provides a semiconductor package including a first tube core and a second tube core located on a substrate, a tube core spacer sandwiched between the side wall of the first tube core and the side wall of the second tube core, and an insulating layer located on the first tube core and the second tube core. The first tube core includes an internal connection structure adjacent to the substrate, a semiconductor substrate located on the internal connection structure, a via extending through the semiconductor substrate, and a dielectric via pad located around the via and sandwiched between the via and the semiconductor substrate. The farthest surface of the semiconductor substrate is at a first distance from the substrate, the farthest point of the via is at a second distance from the substrate, and the farthest point of the dielectric via pad is at a third distance from the substrate. The lower surface of the first tube core is flush with the lower surface of the tube core spacer, and the farthest point of the tube core spacer is at a fourth distance from the substrate, the second distance is greater than the fourth distance, and the fourth distance is greater than the first distance. The farthest surface of the insulating layer is at a fifth distance from the substrate, and the fifth distance is greater than the second distance.

[0006] Based on the above, a plurality of first integrated circuit dies are attached to a carrier substrate and die spacers are formed in the gap regions between adjacent first integrated circuit dies. The first integrated circuit die is processed to prepare for attaching a second integrated circuit die to the first integrated circuit die. An insulating layer is deposited on the first integrated circuit die, the thickness of which is sufficient to cover the protruding vias and the die spacers. By performing a planarization process only on the insulating layer that remains covering the semiconductor substrate, the vias, and the die spacers, the planarization process is performed with improved effectiveness and efficiency. In addition, the bonding of the second integrated circuit die is improved. The packaged semiconductor device can be processed, including similar steps to improve the attachment of the third integrated circuit die. The packaged semiconductor device can be assembled with higher efficiency and increased yield (e.g., thereby reducing costs), and has improved performance.

[0007] In order to make the above features and advantages of the embodiments of the present invention more obvious and easy to understand, embodiments are specifically cited below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A A cross-sectional view of an integrated circuit die is shown in accordance with some embodiments.

[0009] Figure 1B A cross-sectional view of a bridge die is shown in accordance with some embodiments.

[0010] Figure 1C A cross-sectional view of a die stack is shown in accordance with some embodiments.

[0011] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 and Fig.15 Cross-sectional views illustrate intermediate steps during a process for forming a packaged semiconductor device in accordance with some embodiments.

[0012] Figures 16 to 18 Cross-sectional views illustrate intermediate steps during a process for forming a packaged semiconductor device in accordance with some embodiments.

[0013] Fig.19A and Fig.19B Cross-sectional views are shown of intermediate steps during a process for forming a packaged semiconductor device according to various embodiments.

[0014] FIG. 20A to FIG. 20C Cross-sectional views are shown of intermediate steps during a process for forming a packaged semiconductor device according to various embodiments.

[0015] Description of Reference Numerals

[0016] 50: integrated circuit die; 50A: first integrated circuit die; 50B: second integrated circuit die; 50C: third integrated circuit die; 50D: extended integrated circuit die; 52: semiconductor substrate / substrate; 54: device; 56: interlayer dielectric (ILD); 58: conductive plug; 60: interconnect structure; 62: pad; 64: passivation film; 66: die connector; 68, 273, 323, 333, 373, 383: dielectric layer; 70: via; 71: via liner; 72, 122, 172, 272, 322, 332, 372, 382: die spacer; 73, 123, 173: liner layer; 74, 124, 174, 274, 324, 334, 374, 3 84: gap filling material; 76, 78: insulating layer; 80: bridge die; 80A: first bridge die; 80B: second bridge die; 80C: third bridge die; 82, 132: dielectric bonding layer; 84, 134: bonding pads; 90: die stack; 90B: second die stack; 90C: third die stack; 90D: extended die stack; 92, 192: gap area; 100: carrier substrate; 102, 202, 204: bonding layer; 104: alignment mark; 200: support substrate; 273A: first dielectric layer; 273B: second dielectric layer; 273C, 323C, 373C: third dielectric layer; 273D: fourth dielectric layer; H1, H2, H3, H4, H5, H6: height. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to limit the scope of the present disclosure. For example, in the following description, a first feature is formed "above" or "on" a second feature, which may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present disclosure may reuse component numbers and / or letters in each example. Such repetition is for the purpose of simplifying and clearly describing the present disclosure, rather than for limiting the relationship between various embodiments and / or configurations.

[0018] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one component or feature to another (other) component or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used therein may be interpreted in a similar manner.

[0019] Various embodiments provide improved methods for incorporating semiconductor components into packaged semiconductor devices and packaged semiconductor devices formed by the methods. According to some embodiments, a plurality of first integrated circuit dies (e.g., first level integrated circuit dies) are attached to a carrier substrate, and die spacers (e.g., gap fill dielectrics) are formed in gap regions between adjacent first integrated circuit dies. The first integrated circuit dies are processed to prepare for attaching a second integrated circuit die (e.g., second level integrated circuit die) to the first integrated circuit die. For example, the semiconductor substrate of the first integrated circuit die is recessed to expose vias, which then protrude from the semiconductor substrate. The die spacers may also protrude from the semiconductor substrate of the first integrated circuit die. An insulating layer (e.g., an oxide layer) is deposited over the first integrated circuit die, the thickness of which is sufficient to cover the protruding vias and the die spacers. The planarization process is performed with improved effectiveness and efficiency by performing a planarization process only on the insulating layer that remains covering the semiconductor substrate, the vias, and the die spacers. Furthermore, the bonding of the second integrated circuit die (and optionally the bridge die or dummy die) is improved. The packaged semiconductor device may be subjected to further processing, including similar steps to improve the attachment of the third integrated circuit die. According to various embodiments, the packaged semiconductor device may be assembled with higher efficiency and increased yield (e.g., thereby reducing costs), and has improved performance.

[0020] Various embodiments are described below in a specific context. Specifically, a multi-level chip-on-wafer-on-substrate type system integrated chip (SoIC) package is described. However, various embodiments may also be applied to other types of packaging technologies, such as chip-on-wafer-on-substrate (Chip-on-wafer-on-substrate, ) package, a die-die-substrate stack package, an integrated fan-out (InFO) package and / or other types of semiconductor packages.

[0021] Figures 1A to 1CCross-sectional views of exemplary layouts of integrated circuit die 50, bridge die 80, and die stack 90 are respectively shown. As shown and discussed further below, various packaged semiconductor device embodiments may include types and combinations of integrated circuit die 50, bridge die 80, and die stack 90.

[0022] Figure 1A A cross-sectional view of an integrated circuit die 50 is shown in accordance with some embodiments. One or more of the integrated circuit dies 50 will be packaged in subsequent processing to form various embodiments of a packaged semiconductor device. The integrated circuit die 50 may be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), an application processor (AP), a microcontroller, or a similar die); a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, or a similar die); a power management die (e.g., a power management integrated circuit (PMIC) die); a radio frequency (RF) die; a sensor die; a micro-electro-mechanical-system (MEMS) die; a signal processing die (e.g., a digital signal processing (DSP) die); a front-end die (e.g., an analog front-end (AFE) die); or a combination thereof.

[0023] The integrated circuit die 50 may be formed in a wafer, which may include different device areas that are singulated in subsequent steps to form multiple integrated circuit dies. The integrated circuit die 50 may be processed according to an applicable manufacturing process to form an integrated circuit. In some embodiments, the integrated circuit die 50 includes a semiconductor substrate 52 (e.g., doped or undoped silicon) or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52 may include: other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. Other substrates may also be used, such as a multi-layered substrate or a gradient substrate. The semiconductor substrate 52 has an active surface (e.g., Figure 1A The surface facing upward, which may be referred to as the front side), and the inactive surface (e.g. Figure 1A The downward facing surface in the middle can be called the dorsal side).

[0024] A device (represented as a transistor) 54 may be formed at the front side of the semiconductor substrate 52. The device 54 may be an active device (e.g., a transistor, a diode, or a similar active device), a capacitor, a resistor, or a similar device. An interlayer dielectric (ILD) 56 is located on the front side of the semiconductor substrate 52. The ILD 56 surrounds the device 54 and may cover the device 54. The ILD 56 may include one or more dielectric layers formed of materials such as phosphosilicate glass (PSG), boro-silicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like.

[0025] A conductive plug 58 may be formed extending through ILD 56. Conductive plug 58 may be electrically and physically coupled to device 54. In embodiments where device 54 is a transistor, conductive plug 58 may be coupled to a gate and / or source / drain regions of the transistor (source / drain regions may be referred to individually or collectively as source or drain depending on the context). Conductive plug 58 may be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, similar materials, or combinations thereof.

[0026] A via 70 may be formed extending through the ILD 56 and into the semiconductor substrate 52. The via 70 may then be exposed through the back side of the semiconductor substrate 52 and may be used to provide an electrical connection through the semiconductor substrate 52 (e.g., between the front side of the semiconductor substrate 52 and the back side of the semiconductor substrate 52). In some embodiments, the via 70 may be formed by forming a recess in the ILD 56 and / or the semiconductor substrate 52. The recess may be formed by etching, milling, laser technology, a combination thereof, or the like. A via liner 71 (e.g., a dielectric via liner) may be formed in the recess, for example, by thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), or the like. The via liner 71 may include an oxide, such as silicon oxide, silicon oxynitride, or the like. Then, a barrier layer and / or adhesion layer (not shown separately) may be conformally deposited in the recess (e.g., along the via liner 71), for example, by CVD, ALD, physical vapor deposition (PVD), combinations thereof, or the like. The barrier layer and / or adhesion layer may be formed of titanium, titanium nitride, tantalum, tantalum nitride, or the like. A conductive fill material is deposited on the barrier layer and / or adhesion layer and fills the recess. The conductive fill material may be deposited by an electrochemical plating process, CVD, ALD, PVD, combinations thereof, or the like. Examples of conductive fill materials include copper, copper alloys, silver, gold, tungsten, ruthenium, cobalt, aluminum, nickel, combinations thereof, or the like. Excess portions of the conductive filling material, excess portions of the adhesion layer, excess portions of the barrier layer, and / or excess portions of the via liner 71 (e.g., portions extending along the top surface of the ILD 56 and / or the top surface of the semiconductor substrate 52) are removed from the surface of the ILD 56 and / or the surface of the semiconductor substrate 52 by a planarization process (e.g., chemical-mechanical polish (CMP), a grinding process, an etch-back process, or the like). The remaining portions of the barrier layer, the remaining portions of the adhesion layer, and / or the remaining portions of the conductive filling material form the via 70.

[0027] An interconnect structure 60 is formed on the ILD 56, the conductive plug 58, and the via 70. The interconnect structure 60 interconnects the device 54 to form an integrated circuit. In some embodiments, the interconnect structure 60 can be formed by a metallization pattern in a dielectric layer on the ILD 56. The metallization pattern includes metal lines and vias formed in one or more low-k dielectric layers. The metallization pattern of the interconnect structure 60 is electrically coupled to the device 54 through the conductive plug 58 and electrically coupled to the via 70.

[0028] The integrated circuit die 50 further includes a pad 62 (e.g., an aluminum pad) for making external connections. The pad 62 is located on the front side of the semiconductor substrate 52, for example, in and / or on the internal wiring structure 60. A solder area (e.g., a solder ball or a solder bump) may be provided on the pad 62. The solder area may be used to perform chip probe testing on the integrated circuit die 50. The chip probe test may be performed on the integrated circuit die 50 to determine whether the integrated circuit die 50 is a known good die (KGD). Therefore, only the integrated circuit die 50 that is a KGD will undergo subsequent processing and be packaged. The die that does not pass the chip probe test will not be packaged. After testing, the solder area may be removed in a subsequent processing step.

[0029] One or more passivation films 64 are located on the integrated circuit die 50, such as on portions of the interconnect structure 60 and portions of the pads 62. An opening is formed through the passivation film 64 to extend to the pads 62. A die connector 66, such as a conductive post (e.g., formed of a metal such as copper), is formed in the opening extending through the passivation film 64. The die connector 66 can be physically and electrically coupled to a corresponding one of the pads 62. The die connector 66 can be formed by plating or a similar process. In some embodiments, the die connector 66 can be formed by the same or similar materials and processes as the vias 70. The die connector 66 is electrically coupled to the integrated circuit of the integrated circuit die 50.

[0030] The dielectric layer 68 may (or may not) be located on the front side of the semiconductor substrate 52, such as on the passivation film 64 and around the die connector 66. The dielectric layer 68 laterally encapsulates the die connector 66, and the dielectric layer 68 laterally abuts the semiconductor substrate 52. The dielectric layer 68 may be: a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or a similar polymer; a nitride, such as silicon nitride or a similar nitride; an oxide, such as silicon oxide, PSG, BSG, BPSG, or a similar oxide; a similar material; or a combination thereof. The dielectric layer 68 may be formed by spin coating, lamination, CVD, or a similar process. Initially, the dielectric layer 68 may bury the die connector 66 so that the topmost surface of the dielectric layer 68 is above the topmost surface of the die connector 66. In some embodiments, solder regions may be formed on die connector 66 and dielectric layer 68 may bury the solder regions. In some embodiments, die connector 66 is exposed through or protrudes above dielectric layer 68 during formation of integrated circuit die 50. In some embodiments, die connector 66 remains buried and is exposed during subsequent processes for packaging integrated circuit die 50. Exposing die connector 66 may remove any solder regions that may be present on die connector 66.

[0031] Figure 1B A cross-sectional view of a bridge die 80 is shown according to some embodiments. One or more of the bridge die 80 may be packaged in subsequent processing to form various embodiments of a packaged semiconductor device. Within the packaged semiconductor device, the bridge die 80 may be used as a passive component (e.g., lacking active devices, such as transistors, diodes, capacitors, resistors, or the like) that may facilitate electrical connections (e.g., cross-bonding) between other components (e.g., integrated circuit die 50, other bridge die 80, and / or die stack 90). The bridge die 80 shown may be formed similarly to and have most of the same or similar features as described above in connection with the integrated circuit die 50, but lacks, for example, active components, conductive plugs, and surrounding interlayer dielectrics. For example, the bridge die 80 may include: a substrate 52 comprising semiconductor material and / or other suitable materials; an interconnect structure 60 including metal lines and vias formed through one or more dielectric layers and / or through the substrate 52; and a via 70 extending at least partially through the substrate 52. The bridge die 80 may further include some or all of the other features described above in conjunction with the integrated circuit die 50 , such as the pads 62 , the passivation film 64 , the die connector 66 , and the dielectric layer 68 .

[0032] Figure 1CA cross-sectional view of a die stack 90 is shown according to some embodiments. One or more of the die stacks 90 may be packaged in subsequent processing to form various embodiments of a packaged semiconductor device. The die stack 90 may have a single function (e.g., a logic die, a memory die, or the like) or may have multiple functions. In some embodiments, the die stack 90 is a memory device such as an SRAM stack. The die stack 90 shown is a stacked device including a plurality of integrated circuit dies 50. In some embodiments, the die stack 90 may further include one or more bridge dies 80 (e.g., lacking active devices). For example, the die stack 90 may be a memory device including a plurality of memory dies (e.g., an SRAM stack including a plurality of SRAM dies) or a similar device. Each of the components in the die stack 90 (e.g., the integrated circuit die 50 and / or the bridge die 80) may (or may not) have Figure 1A and Figure 1B Any or all of the structures shown in .

[0033] In some embodiments, the integrated circuit dies 50 of the die stack 90 are attached to each other in a face-to-back arrangement, wherein the vias 70 of the overlying integrated circuit die 50 are physically and electrically coupled to the die connections 66 of the underlying integrated circuit die 50. Although shown as including four integrated circuit dies 50, the die stack 90 may include any number of integrated circuit dies 50, such as more or less than four integrated circuit dies 50. The integrated circuit dies 50 of the die stack 90 may be bonded to each other by dielectric-to-dielectric bonding and metal-to-metal bonding. As an example, a first integrated circuit die 50 is disposed face-up, and a second integrated circuit die 50 is placed on the first integrated circuit die 50 and also disposed face-up, such that the back side of the second integrated circuit die 50 faces the front side of the first integrated circuit die. This may be referred to as a face-to-back configuration (F2B).

[0034] Figures 2 to 15 The formation of a multi-level integrated circuit die 50 and a bridge die 80 having a plurality of layers bonded to each other is shown (see, for example, Fig.15 ) is an embodiment of a packaged semiconductor device. For example, a first level including a first integrated circuit die 50A may be attached to a carrier substrate 100 (see Figure 2 ), a second level including a second integrated circuit die 50B and a second bridge die 80B may be attached to the first integrated circuit die 50A (see Fig. 9 ), and a third level including a third integrated circuit die 50C and a third bridge die 80C may be attached to the second integrated circuit die 50B (see Fig.15). According to some embodiments, the integrated circuit die 50 and / or the bridge die 80 may be attached by dielectric-to-dielectric bonding and metal-to-metal bonding. Optionally, additional layers including the integrated circuit die 50 and / or the bridge die 80 may be included in the structure. In some embodiments, the support substrate 200 (see FIG. 1 ) is attached by dielectric-to-dielectric bonding (e.g., by fusion bonding). Fig.15 ) are bonded to the integrated circuit die 50 and the bridge die 80.

[0035] exist Figure 2 , the first integrated circuit die 50A of the first level is attached to the carrier substrate 100. The first integrated circuit die 50A can be bonded to the carrier substrate 100 by bonding the dielectric layer 68 of the first integrated circuit die 50A to the bonding layer 102 on the carrier substrate 100. As shown, a gap region 92 can be sandwiched between adjacent first integrated circuit dies 50A in the first integrated circuit die 50A. The carrier substrate 100 can be a glass carrier substrate, a ceramic carrier substrate, a wafer (such as a silicon wafer), or a similar substrate. The carrier substrate 100 can provide structural support during subsequent processing steps and in the completed device (unless removed). Although two of the first integrated circuit dies 50A are shown, any number of first integrated circuit dies 50A can be attached to the carrier substrate 100, whether in individual packaged semiconductor devices or in multiple packaged semiconductor devices that will eventually be singulated. In some embodiments (not specifically shown), the first level may include a first bridge die 80A attached to the carrier substrate 100 and adjacent to the first integrated circuit die 50A (see Figure 1B ).

[0036] In some embodiments, the first integrated circuit die 50A may be bonded to the carrier substrate 100 using a suitable technique, such as dielectric-to-dielectric bonding (referred to as fusion bonding) or a similar technique. The bonding layer 102 may be an oxide layer, such as silicon oxide (e.g., high density plasma (HDP) oxide or a similar oxide), formed on the surface of the carrier substrate 100 prior to bonding using, for example, CVD, ALD, PVD, thermal oxidation, or a similar process. Other suitable materials may also be used for the bonding layer 102.

[0037] The dielectric-to-dielectric bonding process may further include applying a surface treatment to the dielectric layer 68 and / or the bonding layer 102. The surface treatment may include a plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may further include a cleaning process (e.g., rinsing with deionized water or the like) that may be applied to the dielectric layer 68 and / or the bonding layer 102. The first integrated circuit die 50A is then aligned with the carrier substrate 100 (e.g., aligned with respect to alignment marks 104 disposed in the bonding layer 102). The first integrated circuit die 50A and the carrier substrate 100 are pressed against each other to enable pre-bonding of the dielectric layer 68 and the bonding layer 102. The pre-bonding may be performed at room temperature (e.g., between about 21° C. and about 25° C.). After the pre-bonding, an annealing process may be applied by, for example, heating the first integrated circuit die 50A and / or the carrier substrate 100 to a temperature of about 170° C. to about 500° C.

[0038] In some embodiments, alignment marks 104 may be formed in a bonding layer 102 located on a carrier substrate 100, and the alignment marks 104 may be used to align the first integrated circuit die 50A relative to the carrier substrate 100. The alignment marks 104 may be formed of a metal, a metal alloy, a metal compound, or a similar material. The alignment marks 104 may be formed of a material having a high contrast with a material surrounding the alignment marks 104 (e.g., the material of the bonding layer 102). In some embodiments, the alignment marks 104 may be formed of or may include copper, a copper alloy, tungsten, nickel, or a similar material. Each of the alignment marks 104 may include a metal material, and may or may not include an adhesion layer located under and lining the metal material. The adhesion layer may be formed of or may include titanium, titanium nitride, tantalum, tantalum nitride, or a similar material. The formation process may include depositing the adhesion layer (if included) as a conformal layer using PVD, and depositing a metal material on the adhesion layer. The metal material may be deposited by a plating process such as an electro-chemical plating (ECP) process. A planarization process such as CMP may be performed to remove excess portions of the adhesion layer and excess portions of the metal material, thereby leaving the alignment mark 104 .

[0039] In some embodiments (not specifically shown), the individual first integrated circuit dies 50A may have different thicknesses. As such, after the first integrated circuit dies 50A are attached to the carrier substrate 100, a planarization process may be performed to make the backside surfaces of the first integrated circuit dies 50A flush with each other. The planarization process may be a CMP, a grinding process, an etch-back process, or the like. In some embodiments, this planarization process may be performed later, such as during other planarization processes discussed below (see Figure 3 to Figure 4 ).

[0040] exist Figure 3 In some embodiments, a die spacer 72 including a liner layer 73 and a gap fill material 74 is formed on the first integrated circuit die 50A and the carrier substrate 100 in the gap region 92. The die spacer 72 (e.g., incorporating the liner layer 73 and the gap fill material 74) may also be referred to as a gap fill layer. The liner layer 73 may be formed of a dielectric material having good adhesion to the bonding layer 102 and the first integrated circuit die 50A. In some embodiments, the liner layer 73 is formed of a nitride-containing material (e.g., silicon nitride) or an oxide-containing material (e.g., silicon oxide). The liner layer 73 may be deposited as a conformal layer. For example, the liner layer 73 may be deposited by a conformal deposition process such as ALD, CVD, or a similar process.

[0041] The gap filling material 74 may be formed of a material different from that of the liner layer 73. In some embodiments, the gap filling material 74 may be formed of silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, PSG, BSG, BPSG, or similar materials. For example, the gap filling material 74 may be formed of any of the above-mentioned oxide-containing materials (e.g., silicon oxide). The gap filling material 74 may be formed using CVD, high-density plasma chemical vapor deposition (HDPCVD), flowable chemical vapor deposition (flowable CVD), spin coating, or similar processes. The gap filling material 74 may fill the remaining portion of the gap region 92 between adjacent first integrated circuit dies 50A. After the liner layer 73 and the gap filling material 74 are deposited, a planarization process (e.g., CMP, a grinding process, an etch-back process, a similar process, or a combination thereof) is performed to remove excess portions of the liner layer 73 and excess portions of the gap filling material 74, thereby exposing the first integrated circuit die 50A.

[0042] exist Figure 4 In the embodiment of the present invention, a thinning process is applied to the backside of the first integrated circuit die 50A and the die spacer 72 (e.g., the liner layer 73 and the gap filling material 74). The thinning process may include a planarization process (e.g., mechanical grinding, CMP, or similar processes), an etch-back process, a combination thereof, or the like. According to some embodiments, the thinning process may expose the via 70 and the via liner 71.

[0043] exist Figure 5In the embodiment of the present invention, the semiconductor substrate 52 of the integrated circuit die 50 is recessed so that the corresponding via 70 protrudes above the back side of the semiconductor substrate 52. The semiconductor substrate 52 can be recessed by a suitable etching process, which can include an isotropic etching process (e.g., wet etching), an anisotropic etching process (e.g., dry etching), or the like. The etching process can selectively etch the material of the semiconductor substrate 52 while the via 70 remains substantially unetched. In some embodiments, the etching process can etch the via liner 71, the liner layer 73, and the gap fill material 74 at a greater rate than the via 70 and a smaller rate than the semiconductor substrate 52.

[0044] In some embodiments, after performing the etching process, the via 70 may protrude a height H1 in the range of 0.6 micrometers to 1 micrometer above the semiconductor substrate 52. In addition, the die spacer 72 (e.g., the liner layer 73 and the gap filling material 74) may protrude a height H2 above the semiconductor substrate 52, and the via liner 71 may protrude a height H3 above the semiconductor substrate 52. The height H2 and the height H3 may be the same or different, wherein each height is in the range of 0.2 micrometers to 0.6 micrometers. In some embodiments, the height H2 may be less than the height H3.

[0045] exist Figure 6 , after recessing the semiconductor substrate 52, one or more insulating layers (e.g., insulating layer 76 and insulating layer 78) are formed over the recessed semiconductor substrate 52, the insulating layers having a thickness that also surrounds and covers the vias 70 and the die spacer 72. The insulating layers 76, 78 provide isolation between the vias 70 and can be used for subsequent dielectric-to-dielectric bonding processes to attach various other dies to the first integrated circuit die 50A. Each of the insulating layers 76, 78 is formed by depositing an insulating material on the exposed upper surface (e.g., backside) of the first integrated circuit die 50A. The insulating material can be formed of silicon oxide, silicon carbide, silicon oxynitride, silicon oxycarbon nitride, PSG, BSG, BPSG, similar materials, or combinations thereof. The insulating material can be deposited by CVD, ALD, spin coating, or similar processes.

[0046] For example, the insulating layer 76 may be silicon nitride or silicon oxide and is conformally deposited over the semiconductor substrate 52 and the die spacer 72 (e.g., the liner layer 73 and the gap fill material 74). Although not specifically shown, in some embodiments, the insulating layer 76 may also be deposited along the exposed surfaces (e.g., the sidewalls and / or the upper surface) of the via 70 and the via liner 71. In some embodiments, the insulating layer 76 is formed as a thermal oxide and is optionally nitrided in a post-deposition treatment process. The insulating layer 78 may be silicon oxide or silicon nitride (e.g., the same or different material as the insulating layer 76) and is conformally deposited over the insulating layer 76. According to some embodiments, the insulating layer 78 may have a thickness in the range of 1 micron to 2 microns over the semiconductor substrate and may have a thickness in the range of 1 micron to 2 microns over the via 70.

[0047] exist Figure 7 In the embodiment of the present invention, a planarization process is performed to make the upper surface of the insulating layer 78 flush. The planarization process may be a CMP, a grinding process, an etch-back process, a combination thereof, or a similar process. According to some embodiments, the planarization process stops before reaching the via 70, or the planarization process may continue so that the insulating layer 78 is flush with the via 70. As shown in the figure, after the insulating material is planarized, the planarized upper surface of the insulating layer 78 may be located above the top surface of the via 70, the top surface of the insulating layer 76, the top surface of the liner layer 73, and the top surface of the gap filling material 74. For example, in some embodiments, the insulating layer 78 may have a thickness in the range of 1 micron to 1.5 microns above the semiconductor substrate 52, the insulating layer 78 may have a thickness in the range of 0.2 microns to 0.9 microns above the via 70, and the insulating layer 78 may have a thickness in the range of 0.8 microns to 1.3 microns above the die spacer 72 (or above the insulating layer 76).

[0048] Benefits are achieved by keeping the top surface of the die spacer (e.g., liner layer 73 and gap fill material 74), the top surface of insulating layer 76 (if present), and the top surface of via 70 covered by insulating layer 78 during and after the planarization process. For example, the CMP and / or etch-back process of the planarization process can be more efficient and make the planarized surface more flat because the planarization process is performed on a single material rather than on multiple materials (e.g., with varying etch selectivities). As a result, the planarized surface (e.g., the upper surface of insulating layer 78) is flatter and smoother than if the planarized surface included insulating layer 78 as well as gap fill material 74, liner layer 73, and / or insulating layer 76.

[0049] exist Figure 8In the embodiment of the present invention, a dielectric bonding layer 82 and bonding pads 84 are optionally formed on the insulating layer 78 and the vias 70. In some embodiments, the dielectric bonding layer 82 can be formed of an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), or the like using a suitable process. An opening can be formed through the dielectric bonding layer 82 and partially through the insulating layer 78 to expose the vias 70. A bonding pad 84 is then formed in the opening. In some embodiments, the bonding pad 84 may include a dummy bonding pad that is not coupled to any metal feature (e.g., the via 70) of the integrated circuit die 50.

[0050] To form the bonding pad 84, an opening may be formed in the dielectric bonding layer 82 using acceptable photolithography and etching techniques. The opening may be extended through the insulating layer 78. A liner layer, a barrier layer, an adhesive layer, and / or a conductive filling material (not shown separately) may be formed in the opening, and the liner layer, the barrier layer, the adhesive layer, and / or the conductive filling material (not shown separately) may be used to form the bonding pad 84. The liner layer, the barrier layer, and the adhesive layer may be formed by ALD, PVD, CVD, thermal oxidation, or similar processes. The conductive filling material may be formed by plating (e.g., electroplating or electroless plating) or similar processes. In some embodiments, the liner layer may include oxides such as silicon oxide, silicon oxynitride, or similar materials. The barrier layer and the adhesive layer may include titanium, titanium nitride, tantalum, tantalum nitride, or similar materials. The conductive filling material may include copper, copper alloy, silver, gold, tungsten, ruthenium, cobalt, aluminum, nickel, or similar materials. A planarization process (e.g., CMP) may be performed to remove excess portions of the liner layer, excess portions of the barrier layer, excess portions of the adhesive layer, and / or excess portions of the conductive fill material until the dielectric bonding layer 82 is exposed. The remaining portions of the liner layer, the remaining portions of the barrier layer, the remaining portions of the adhesive layer, and / or the remaining portions of the conductive fill material form bonding pads 84, which are subsequently used for bonding. The dielectric bonding layer 82 (and the insulating layer 78) may provide isolation between the vias 70 and between the bonding pads 84, and the dielectric bonding layer 82 may be used in a subsequent dielectric-to-dielectric bonding process for bonding an additional die to the first integrated circuit die 50A.

[0051] exist Fig. 9, according to some embodiments, the second integrated circuit die 50B and the second bridge die 80B of the second level are bonded to the dielectric bonding layer 82 and the bonding pads 84 on the first integrated circuit die 50A. The second level shown may include gap regions 192 sandwiched between adjacent second integrated circuit dies 50B and second bridge dies 80B in the second integrated circuit die 50B and the second bridge die 80B. In the illustrated embodiment, the second integrated circuit die 50B and the second bridge die 80B are bonded to the first integrated circuit die 50A by dielectric-to-dielectric bonding and / or metal-to-metal bonding. In some embodiments (not specifically shown), dummy dies (e.g., replacing some of the second bridge dies 80B) may be bonded to the first integrated circuit die 50A by fusion bonding (e.g., dielectric-to-dielectric bonding).

[0052] According to some embodiments (not specifically shown), some of the second bridge dies 80B in the second bridge die 80B may be dummy dies (e.g., heat sink dies) to facilitate heat transfer from adjacent integrated circuit dies 50. For example, the dummy die may be formed of homogeneous materials and may not have devices, metal lines, and similar components. The substrate of the dummy die may be formed of one or more materials with high thermal conductivity (e.g., silicon, ceramic, thermally conductive glass, metal (e.g., copper or iron), or similar materials). A dielectric bonding layer of the dummy die may be formed on the substrate, and the dielectric bonding layer may be used to attach the dummy die to the first integrated circuit die 50A. In some embodiments, the dielectric bonding layer may be formed of materials such as silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, combinations thereof, or similar materials.

[0053] The second integrated circuit die 50B is bonded to the first integrated circuit die 50A via the dielectric layer 68 and die connectors 66 of the second integrated circuit die 50B and the dielectric bonding layer 82 and bonding pads 84 along the first integrated circuit die 50A. Similarly, the second bridge die 80B is bonded to the first integrated circuit die 50A via the dielectric layer 68 and die connectors 66 of the second bridge die 80B and the dielectric bonding layer 82 and bonding pads 84 along the first integrated circuit die 50A. A desired type and number of second integrated circuit dies 50B and second bridge dies 80B are bonded to each of the first integrated circuit dies 50A. In the illustrated embodiment, a plurality of second bridge dies 80B are bonded adjacent to each of the second integrated circuit dies 50B, however other suitable arrangements may be used.

[0054] The second integrated circuit die 50B may be a logic device, such as a central processing unit (CPU), a graphics processing unit (GPU), a system-on-chip (SoC), a microcontroller, or a similar device. In some embodiments, the second integrated circuit die 50B may be a memory device, such as a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a hybrid memory cube (HMC) module, a high-bandwidth memory (HBM) module, or a similar device. As described above, the second bridge die 80B may be an interposer including a rewiring structure or a functional device (such as a memory device similar to the devices listed above). The second integrated circuit die 50B and the second bridge die 80B may be formed in a process of the same technology node or may be formed in a process of different technology nodes. For example, the second integrated circuit die 50B may be a more advanced process node than the second bridge die 80B. Similarly, the second integrated circuit die 50B and the first integrated circuit die 50A may be formed in a process of the same technology node or may be formed in a process of different technology nodes. Other combinations of integrated circuit dies (eg, with or without bridge die 80 ) are possible in some embodiments.

[0055] The second integrated circuit die 50B and the second bridge die 80B are shown bonded to the first integrated circuit die 50A in a dielectric-to-dielectric and metal-to-metal bonding configuration. The second integrated circuit die 50B and the second bridge die 80B are disposed face-down so that the respective front sides of the second integrated circuit die 50B and the second bridge die 80B face the dielectric bonding layer 82 and the bonding pads 84 along the back side of the first integrated circuit die 50A.

[0056] The dielectric layer 68 of the second integrated circuit die 50B and the second bridge die 80B can be directly bonded to the dielectric bonding layer 82 along the first integrated circuit die 50A. In some embodiments, the bond between the dielectric bonding layer 82 and each of the dielectric layers 68 is a dielectric-to-dielectric bond, such as an oxide-to-oxide bond, an oxide-to-nitride bond, or the like. In embodiments where some of the second bridge dies 80B are dummy dies, portions of the dielectric bonding layer 82 adjacent to the dielectric layer 68 of the dummy die can have no metal features, such that a dielectric-to-dielectric bond is formed at an interface having a width extending the width of the dummy die.

[0057] The bonding process directly bonds the die connectors 66 of the second integrated circuit die 50B and the second bridge die 80B to the bonding pads 84 by direct metal-to-metal bonding. Thus, the second integrated circuit die 50B and the second bridge die 80B are electrically and mechanically coupled to the first integrated circuit die 50A. In some embodiments, the interface between the second integrated circuit die 50B and the first integrated circuit die 50A also includes a dielectric-to-metal interface (e.g., where the die connectors 66 and the bonding pads 84 are not fully aligned and / or have different widths). A similar dielectric-to-metal interface can enable the second bridge die 80B to be bonded to the first integrated circuit die 50A.

[0058] As an example, the dielectric-to-dielectric and metal-to-metal bonding processes begin with surface treatment of one or more of the dielectric layer 68 and / or the dielectric bonding layer 82. The surface treatment may include a plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may further include a cleaning process (e.g., rinsing with deionized water or the like) that may be applied to one or both of the dielectric layer 68 and / or the dielectric bonding layer 82. The die connectors 66 of the second integrated circuit die 50B and the second bridge die 80B are aligned with the corresponding bonding pads 84 along the first integrated circuit die 50A (e.g., such that the outer side surface of the second bridge die 80B is aligned with and abuts the outer side surface of the first integrated circuit die 50A). When the second integrated circuit die 50B and the second bridge die 80B are aligned with the first integrated circuit die 50A, the die connectors 66 may overlap with the corresponding bonding pads 84 (e.g., and with the corresponding vias 70).

[0059] A pre-bonding step is performed during which the respective dielectric layers 68 and respective die connectors 66 of the second integrated circuit die 50B and the second bridge die 80B are contacted with the dielectric bonding layer 82 and the corresponding bonding pads 84 along the first integrated circuit die 50A. The pre-bonding step may be performed at room temperature (e.g., at about 21° C. to about 25° C.). Annealing may be performed at a temperature in the range of about 150° C. to about 400° C. for a duration in the range of about 0.5 hour to about 3 hours. This causes the metal (e.g., copper) in the die connector 66 and the metal (e.g., copper) in the bonding pad 84 to diffuse into each other, thereby forming a direct metal-to-metal bond. In some embodiments, other direct bonding processes may be used (e.g., using adhesives, polymer-to-polymer bonding, or the like).

[0060] In some embodiments (not specifically shown), the second bridge die 80B is bonded to the first integrated circuit die 50A using a solder connection (e.g., a microbump or the like). For example, the die connection 66 of the second bridge die 80B may be a ball grid array (BGA) connection, a solder ball, a metal pillar, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by an electroless nickel-electroless palladium-immersion gold (ENEPIG) technique, or a similar structure. The die connection 66 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the die connection 66 is formed by initially forming a solder layer by evaporation, plating, printing, solder transfer, ball planting, or a similar process. Once the solder layer has been formed on the structure, a reflow process may be performed to shape the material into the desired bump shape. In another embodiment, the die connector 66 comprises a metal post (e.g., a copper post) formed by sputtering, printing, electroplating, electroless plating, CVD, or a similar process. The metal post may be free of solder and may have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal post. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, a similar material, or a combination thereof, and may be formed by a plating process.

[0061] In some embodiments (not specifically shown), the dielectric layer 68 and the die connector 66 of the second bridge die 80B are directly bonded to the insulating layer 76 and the via 70, respectively, without forming the dielectric bonding layer 82 and / or the bonding pad 84 along the first integrated circuit die 50A. This enables the overall thickness of the packaged semiconductor device to be reduced. The insulating layer 76 can be formed with a reduced thickness compared to a structure including the bonding pad 84 located between the die connector 66 and the via 70. This reduces the thermal resistance of the integrated circuit die 50, which improves heat dissipation in the packaged semiconductor device.

[0062] exist Fig.10In some embodiments, a die spacer 122 including a liner layer 123 and a gap fill material 124 is formed on the second bridge die 80B and the integrated circuit die (50A, 50B) in the gap region 192. The die spacer 122 (e.g., combining the liner layer 123 and the gap fill material 124) may also be referred to as a gap fill layer. The liner layer 123 may be formed of a dielectric material having good adhesion to the dielectric bonding layer 82 (or the insulating layer 76), to the sidewalls of the second bridge die 80B, and to the sidewalls of the second integrated circuit die 50B. In some embodiments, the liner layer 123 is formed of a nitride-containing material (e.g., silicon nitride) or an oxide-containing material (e.g., silicon oxide). The liner layer 123 may be deposited as a conformal layer. For example, the liner layer 123 may be deposited by a conformal deposition process such as ALD, CVD, or a similar process. In some embodiments, the gap filling material 124 may be formed of a conductive material, and the liner layer 123 may be a barrier layer. In such embodiments, the liner layer 123 may be conformally deposited by CVD, ALD, PVD, thermal oxidation, combinations thereof, or the like. The liner layer 123 may be formed of oxides, nitrides, carbides, combinations thereof, or the like.

[0063] The gap filling material 124 may be formed of a material different from that of the liner layer 123. In some embodiments, the gap filling material 124 may be formed of silicon oxide, silicon carbide, silicon oxynitride, silicon oxycarbon nitride, PSG, BSG, BPSG, or similar materials. For example, the gap filling material 124 may be formed of any of the above-mentioned oxide-containing materials (e.g., silicon oxide). The gap filling material 124 may be formed using CVD, HDPCVD, flowable CVD, spin coating, or similar processes. In some embodiments, the gap filling material 124 may be formed of a molding compound, an epoxy resin, or a similar material. The gap filling material 124 may be applied by compression molding, transfer molding, or a similar process. The gap filling material 124 may fill the remaining gap between the adjacent second bridge die 80B and the second integrated circuit die 50B. After depositing the liner layer 123 and the gap filling material 124, a planarization process (e.g., CMP, grinding, etch-back, or the like) is performed to remove excess portions of the liner layer 123 and the gap filling material 124 to form the die spacer 122 and expose the second bridge die 80B and the second integrated circuit die 50B.

[0064] exist Fig.11In the embodiment of the present invention, the semiconductor substrate 52 of the second integrated circuit die 50B and the second bridge die 80B is recessed so that the via 70 protrudes above the back side of the semiconductor substrate 52. The semiconductor substrate 52 can be recessed by a suitable etching process, which can include an isotropic etching process (e.g., wet etching), an anisotropic etching process (e.g., dry etching), or the like. The etching process can selectively etch the material of the semiconductor substrate 52 while the via 70 remains substantially unetched. In some embodiments, the etching process can etch the via liner 71, the liner layer 123, and the gap filling material 124 at a greater etching rate than the via 70 and a smaller etching rate than the semiconductor substrate 52.

[0065] In some embodiments, after performing the etching process, the via 70 may protrude above the semiconductor substrate 52 by a height H4 in a range of 0.6 microns to 1 micron. Additionally, the die spacer 122 (e.g., the liner layer 123 and the gap fill material 124) may protrude above the semiconductor substrate 52 by a height H5, and the via liner 71 may protrude above the semiconductor substrate 52 by a height H6. The height H5 and the height H6 may be the same or different, with each height being in a range of 0.2 microns to 0.6 microns. In some embodiments, the height H5 is less than the height H6. Note that the height H4 may be the same or different from the height H1, the height H5 may be the same or different from the height H2, and the height H6 may be the same or different from the height H3, as described above in conjunction with the discussion of recessing the semiconductor substrate 52 of the first integrated circuit die 50A.

[0066] exist Fig.12 In the embodiment of the present invention, after the semiconductor substrate 52 is recessed, an insulating layer (e.g., insulating layer 126 and insulating layer 128) may be formed over the recessed semiconductor substrate 52 and over and around the vias 70. The insulating layers 126, 128 provide isolation between the vias 70 and may be used in a subsequent dielectric-to-dielectric bonding process to attach various other dies to the second integrated circuit die 50B and the second bridge die 80B. Each of the insulating layers 126, 128 is formed by depositing an insulating material on the exposed upper surface (e.g., backside) of the second integrated circuit die 50B and the second bridge die 80B. The insulating material may be formed of silicon oxide, silicon carbide, silicon oxynitride, silicon oxycarbon nitride, PSG, BSG, BPSG, similar materials, or combinations thereof. The insulating material may be deposited by CVD, ALD, spin coating, or similar processes.

[0067] For example, the insulating layer 126 may be silicon nitride or silicon oxide, and is conformally deposited over the semiconductor substrate 52 and the die spacer 122 (e.g., the liner layer 123 and the gap fill material 124). Although not specifically shown, in some embodiments, the insulating layer 126 may also be deposited along the exposed surfaces of the via 70 and the via liner 71. In some embodiments, the insulating layer 126 is formed as a thermal oxide and is optionally nitrided in a post-deposition treatment process. The insulating layer 128 may be silicon oxide or silicon nitride (e.g., the same or different material as the insulating layer 126), and is conformally deposited over the insulating layer 126. According to some embodiments, the insulating layer 128 may have a thickness in the range of 1 micron to 2 microns over the semiconductor substrate, and may have a thickness in the range of 1 micron to 2 microns over the via 70.

[0068] exist Fig.13 In the embodiment of the present invention, a planarization process is performed to make the upper surface of the insulating layer 128 flush, and optionally, a dielectric bonding layer 132 and a bonding pad 134 are formed on the insulating layer 128 and the via 70. The planarization process may be a CMP, a grinding process, an etch-back process, or the like. In some embodiments, the planarization process stops before reaching the via 70, or the planarization process may continue so that the insulating layer 128 is flush with the via 70. As shown in the figure, after the insulating layer 128 is planarized, the surface of the insulating layer 128 may be located above the top surface of the via 70, the top surface of the insulating layer 126, and the top surface of the die spacer 122 (e.g., the liner layer 123 and the gap filling material 124). For example, in some embodiments, the insulating layer 128 may have a thickness in a range of 1 micron to 1.5 microns over the semiconductor substrate 52 of the second integrated circuit die 50B and the second bridge die 80B, the insulating layer 128 may have a thickness in a range of 0.2 microns to 0.9 microns over the vias 70, and the insulating layer 128 may have a thickness in a range of 0.8 microns to 1.3 microns over the die spacer 122 (or over the insulating layer 126).

[0069] As described above, during and after the planarization process, benefits are achieved by keeping the top surface of the die spacer 122 (e.g., the liner layer 123 and the gap fill material 124), the top surface of the insulating layer 126 (if present), and the top surface of the via 70 covered by the insulating layer 128. For example, the CMP and / or etch-back process of the planarization process may be more efficient and make the planarized surface more flat because the planarization process is performed on a single material rather than on multiple materials (e.g., with varying etch selectivities). As a result, the planarized surface of the structure (e.g., the upper surface of the insulating layer 128) is flatter and smoother than if the planarized surface included the insulating layer 128 as well as the gap fill material 124, the liner layer 123, and / or the insulating layer 126.

[0070] In some embodiments, dielectric bonding layer 132 may be formed of an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), or the like, similar to that described above in connection with dielectric bonding layer 82. An opening may then be formed through dielectric bonding layer 132 and partially through insulating layer 128 to expose via 70. Bond pads 134 may then be formed in the opening similar to that described above in connection with bond pads 84. In some embodiments, bond pads 134 may include dummy bond pads that are not coupled to any metal features (e.g., via 70) of second integrated circuit die 50B or second bridge die 80B.

[0071] exist Fig.14 In the embodiment of the present invention, the third integrated circuit die 50C and the third bridge die 80C of the third level are bonded to the dielectric bonding layer 132 and the bonding pads 134 disposed along the second integrated circuit die 50B and the second bridge die 80B, similar to the above description of bonding the second integrated circuit die 50B and the second bridge die 80B to the first integrated circuit die 50A. In addition, a die spacer 172 (e.g., also referred to as a gap filler layer) including a liner layer 173 and a gap filler material 174 is formed on the third integrated circuit die 50C and the third bridge die 80C and between the third integrated circuit die 50C and the third bridge die 80C. The die spacer 172 can be formed similarly to the above description of bonding the die spacers 72, 122 (e.g., including the respective liner layers 73, 123 and the respective gap filler materials 74, 124).

[0072] exist Fig.15 In some embodiments, a support substrate 200 is attached to a third integrated circuit die 50C and a third bridge die 80C. For example, a bonding layer 204 is formed on the third integrated circuit die 50C, the third bridge die 80C, and the die spacer 172 (e.g., the liner layer 173 and the gap fill material 174). The bonding layer 204 can be an oxide layer, such as silicon oxide (e.g., HDP oxide or similar material). The bonding layer 204 can be deposited on the planarized upper surface of the structure using, for example, CVD, ALD, PVD, thermal oxidation, or similar processes. Other suitable materials can be used for the bonding layer 204.

[0073] As described above, the support substrate 200 may be bonded to the third integrated circuit die 50C and the third bridge die 80C by bonding the bonding layer 202 disposed along the support substrate 200 to the bonding layer 204 disposed along the third integrated circuit die 50C, the third bridge die 80C, and the die spacer 172. The support substrate 200 may be a glass support substrate, a ceramic support substrate, a wafer (e.g., a silicon wafer), or the like. The support substrate 200 may provide structural support during subsequent processing steps and in a completed device.

[0074] In some embodiments, the support substrate 200 may be bonded to the third integrated circuit die 50C and the third bridge die 80C using a suitable technique, such as dielectric-to-dielectric bonding or the like. The bonding layer 102 may be an oxide layer, such as silicon oxide (e.g., HDP oxide or the like), formed on the surface of the support substrate 200 prior to bonding using, for example, CVD, ALD, PVD, thermal oxidation, or the like. Other suitable materials may be used for the bonding layer 202. The dielectric-to-dielectric bonding process may be combined with the above process to bond the carrier substrate 100 to the first integrated circuit die 50A (see Figure 2 ) are the same or similar to the dielectric-to-dielectric bonding process described herein.

[0075] In some embodiments (not specifically shown), the third integrated circuit die 50C and the third bridge die 80C do not include the vias 70 because external electrical connections are made through the first integrated circuit die 50A. In some embodiments (also not specifically shown), external electrical connections are made to the vias 70 of the third integrated circuit die 50C and / or the bridge die 80C instead of attaching the supporting substrate 200.

[0076] In the above-described embodiments, the integrated circuit die 50 and the bridge die 80 are bonded to each other using various combinations of dielectric-to-dielectric bonding and metal-to-metal bonding, the carrier substrate 100 is bonded to the first integrated circuit die 50A by dielectric-to-dielectric bonding (e.g., fusion bonding), and the support substrate 200 is bonded to the third integrated circuit die 50C and the third bridge die 80C by dielectric-to-dielectric bonding (e.g., fusion bonding). In addition, as described above, dielectric bonding layers 82, 132 and corresponding bonding pads 84, 134 may be formed to facilitate the attachment of the integrated circuit die 50 and the bridge die 80 to each other.

[0077] In some embodiments (not specifically shown), the integrated circuit die 50 and / or the bridge die 80 may be attached in a packaged semiconductor device without forming the dielectric bonding layers 82, 132 and the bonding pads 84, 134. For example, the die connectors 66 (or other conductive features) of the integrated circuit die 50 and / or the bridge die 80 may be directly bonded to the vias 70 (or other conductive features) of the other integrated circuit die 50 and the bridge die 80. In addition, the dielectric layer 68 may be directly bonded to the corresponding insulating layer 78, 128. By coupling the die connectors 66 and the dielectric layer 68 directly to the vias 70 and the insulating layers 76, 126 without forming additional bonding pads and / or dielectric layers therebetween, the packaged semiconductor device may have a reduced overall thickness. Additionally, eliminating these steps and additional layers may also reduce costs and increase yields of packaged semiconductor devices.

[0078] Although not specifically shown, according to some embodiments, the packaged semiconductor device may be subjected to further processing. Specifically, after attaching the support substrate 200, the carrier substrate 100 may be removed, and external connectors may be formed over the die connectors 66 of the first integrated circuit die 50A. For example, the carrier substrate 100 and the bonding layer 102 may be removed to expose the die connectors 66 of the first integrated circuit die 50A. A dielectric layer (e.g., a passivation layer) may then be formed along the first integrated circuit die 50A and the exposed die spacer 72 (e.g., a liner layer 73). The dielectric layer may be patterned to form an opening to the die connector 66, and an under-bump metallurgy (UBM) may be formed in the opening using a suitable process. External connectors may then be formed on the UBM. The external connectors may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip attach (C4) bumps, microbumps, bumps formed by electroless nickel palladium immersion gold (ENEPIG) technology, or similar components. If formed at the wafer level, the packaged semiconductor devices can be singulated from each other and attached to other components (e.g., incorporated into an electronic device).

[0079] Reference Figures 16 to 18 According to some embodiments, a packaged semiconductor device may be formed with variations in the formation of a die spacer. The resulting die spacer may be formed to have improved strength and reliability, thereby providing the packaged semiconductor device with improved durability and performance. Unless otherwise specifically stated, the packaged semiconductor device may be formed similarly to the various processing steps described above.

[0080] exist Fig.16 In the process of attaching the first integrated circuit die 50A to the carrier substrate 100 (see Figure 2), the die spacer 272 is formed by conformally depositing a plurality of dielectric layers 273 over and between the first integrated circuit dies 50A, followed by depositing a gap fill material 274 to fill the remaining space between the first integrated circuit dies 50A. The plurality of dielectric layers 273 and the gap fill material 274 may be deposited by ALD, CVD, or similar processes. In some embodiments, the plurality of dielectric layers 273 are deposited with alternating compositions, such as chemical compositions. Each of the plurality of dielectric layers 273 shown may be deposited as an embedded U-shape. After depositing the plurality of dielectric layers 273, the gap fill material 274 may be deposited as a T-shape within the U-shape of the last of the dielectric layers 273.

[0081] For example, each of the plurality of dielectric layers 273 may be silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxynitride, or the like. According to some embodiments, the first dielectric layer 273A may be deposited as a first composition, and then the second dielectric layer 273B may be deposited as a second composition. Then, the third dielectric layer 273C may be deposited from the same composition as the first dielectric layer 273A, and the fourth dielectric layer 273D may be deposited from the same composition as the second dielectric layer 273B. For example, in an embodiment (not specifically shown) in which an additional dielectric layer 273 is deposited, the additional dielectric layer 273 may continue the pattern formed by the alternating composition. Then, the gap filling material 274 may be selected to continue the alternating composition pattern. For example, in some embodiments, the first composition may be silicon nitride, and the second composition may be silicon carbide, silicon oxide, or silicon oxynitride. In addition, in some embodiments, the first composition may be silicon oxide, and the second composition may be silicon carbide, silicon nitride, or silicon carbonitride.

[0082] It should be understood that other combinations of compositions of the plurality of dielectric layers 273 and gap fill material 274 may be used to form the die spacer 272. For example, the plurality of dielectric layers may alternate between any other of the above-listed oxygen-containing layers and any other of the above-listed carbon-containing layers, between any other of the above-listed oxygen-containing layers and any other of the above-listed nitrogen-containing layers, or between any other of the above-listed carbon-containing layers and any other of the above-listed nitrogen-containing layers. In addition, three or more types of compositions may be used for the plurality of dielectric layers.

[0083] exist Fig.17 In the embodiment, a planarization process is performed on the die spacer 272 (e.g., the plurality of dielectric layers 273 and the gap filling material 274) to be flush with the first integrated circuit die 50A. For example, the planarization process may include CMP, a grinding process, an etch-back process, a similar process, or a combination thereof, and the planarization process is performed to remove excess portions of the gap filling material 274 and excess portions of the plurality of dielectric layers 273, thereby similarly to the above (see Figure 3) exposes the semiconductor substrate 52 of the first integrated circuit die 50A. Although not specifically shown, subsequent processing steps may be performed in conjunction with the above Figures 4 to 8 Similar to what is described.

[0084] exist Fig.18 In the embodiment, the integrated circuit die (50B, 50C) and the bridge die (80B, 80C) can be attached, and combined with the above Figures 9 to 14 As shown in the figure, a die spacer 322, 332 can be formed between the second integrated circuit die 50B and the second bridge die 80B, and the die spacer 322, 332 can be formed between the second integrated circuit die 50B and the second bridge die 80B. Figure 16 to Figure 17 In addition, die spacers 372, 382 may be formed between the third integrated circuit die 50C and the third bridge die 80C to form a plurality of die spacers 372, 382. Figure 16 to Figure 17 As further shown, wide die spacers 322, 372 are formed in the wide gap region, and narrow die spacers 332, 382 are formed in the narrow gap region.

[0085] As shown, the wide die spacer 322 (e.g., within the second level including the second integrated circuit die 50B and the second bridge die 80B) can be formed similarly as described in connection with the die spacer 272. For example, the wide die spacer 322 can have the same number of the plurality of dielectric layers 323 before depositing the gap filling material 324 as compared to the plurality of dielectric layers 273 and the gap filling material 274 of the die spacer 272. Additionally, the narrow die spacer 332 can be formed with a smaller number of the plurality of dielectric layers 333 (e.g., compared to the die spacer 272 and the wide die spacer 322) before depositing the gap filling material 334. For example, in some embodiments, the third dielectric layer 323C of the wide die spacer 322 can be formed simultaneously with the gap filling material 334 of the narrow die spacer 332.

[0086] Similarly, a wide die spacer 372 (e.g., within a third level including the third integrated circuit die 50C and the third bridge die 80C) can be formed similarly as described in connection with the die spacer 272. For example, the wide die spacer 372 can have the same number of the plurality of dielectric layers 373 prior to depositing the gap filling material 374 as compared to the plurality of dielectric layers 273 and gap filling material 274 of the die spacer 272. Additionally, a narrow die spacer 382 can be formed with a smaller number of the plurality of dielectric layers 383 (e.g., as compared to the die spacer 272 and the wide die spacers 322, 372). For example, in some embodiments, the third dielectric layer 373C of the wide die spacer 372 can be formed simultaneously with the gap filling material 384 of the narrow die spacer 382.

[0087] In addition, you can combine Fig.15 The subsequent processing steps are performed, such as attaching the support substrate 200. In addition, as described above, the packaged semiconductor device may be subjected to subsequent processing steps not shown herein, including the formation of UBMs and external connectors, singulation and / or attachment to other components (e.g., incorporation into an electronic device).

[0088] Reference FIG. 19A to FIG. 20C According to some embodiments, a packaged semiconductor device may be formed with variations in the integrated circuit die 50 and the bridge die 80. Variations may be advantageous to achieve specific functional benefits. Unless otherwise specified, the following packaged semiconductor device may be formed similarly to the various processing steps described above (including variations in forming the die spacers 72, 122, 172, 272).

[0089] exist Fig.19A and Fig.19B In some embodiments, the packaged semiconductor device may include an extended integrated circuit die 50D (e.g., having a direct electrical connection with one or more of the integrated circuit die 50 and / or the bridge die 80). As shown, the extended integrated circuit die 50D may have a greater width than the other integrated circuit die 50 and the bridge die 80. In some embodiments (not specifically shown), the extended integrated circuit die 50D may have the same width as the other integrated circuit die 50, while being offset to bridge and have a direct electrical connection with one or more of the integrated circuit die 50 and / or the bridge die 80 above or below. Other dies (e.g., a third bridge die 80C) may be attached laterally adjacent to the extended integrated circuit die 50D, or the extended integrated circuit die 50D may span all or most of the width of the packaged semiconductor device. Although three levels of integrated circuit die 50 and bridge die 80 are shown, the packaged semiconductor device may have two levels or more than three levels. Additionally, extended integrated circuit die 50D may be attached to more than one level of a packaged semiconductor device.

[0090] Reference Fig.19A , the extended integrated circuit die 50D can be located on the second level of the packaged semiconductor device. As such, the extended integrated circuit die 50D can have intermediate connections (e.g., direct connections via bonding pads 84) with two or more of the underlying first integrated circuit dies 50A. Additionally, the extended integrated circuit die 50D can have intermediate connections (e.g., direct connections via bonding pads 134) with two or more of the overlying third integrated circuit die 50C and the third bridge die 80C.

[0091] Reference Fig.19B, the extended integrated circuit die 50D can be located on the third level of the packaged semiconductor device. As such, the extended integrated circuit die 50D can have an intermediate connection (e.g., a direct connection via bonding pads 134) with two or more of the underlying second integrated circuit die 50B and the second bridge die 80B. Additionally, the support substrate 200 can be attached to the extended integrated circuit die 50D (and the third bridge die 80C, if present).

[0092] exist FIG. 20A to FIG. 20C In the embodiment, the packaged semiconductor device may include a die stack 90, for example, replacing one or more of the integrated circuit dies 50 from any of the above-described embodiments. Figure 1C ), each die stack 90 may include a plurality of integrated circuit dies 50 or a combination of an integrated circuit die 50 and a bridge die 80 in a stacked form.

[0093] For example, Fig. 20A Show and combine Fig.15 A packaged semiconductor device similar to the device described above, wherein the second die stack 90B replaces the second integrated circuit die 50B, and the third die stack 90C replaces the third integrated circuit die 50C. In addition, Fig. 20B Show and combine Fig.19A A packaged semiconductor device similar to the device described above, wherein the extended die stack 90D replaces the extended integrated circuit die 50D, and the third die stack 90C replaces the third integrated circuit die 50C. In addition, Fig. 20C Show and combine Fig.19B A packaged semiconductor device similar to the device described above is provided, wherein the extended die stack 90D replaces the extended integrated circuit die 50D, and the second die stack 90B replaces the second integrated circuit die 50B.

[0094] Various embodiments can achieve various advantages. As described above, after attaching the first integrated circuit die 50A to the carrier substrate 100, the first integrated circuit die 50A is processed to prepare for attaching the second integrated circuit die 50B to the first integrated circuit die 50A. For example, the semiconductor substrate 52 of the first integrated circuit die 50A is recessed to expose the via 70, and then the via 70 protrudes from the semiconductor substrate 52. The die spacer 72 can also protrude from the semiconductor substrate 52 of the first integrated circuit die 50A. An insulating layer 78 (e.g., an oxide layer) is deposited on the first integrated circuit die 50A, and its thickness is sufficient to cover the protruding via 70 and the die spacer 72. A planarization process is performed so that the insulating layer 78 has a flat upper surface, which remains to cover the semiconductor substrate 52, the via 70, and the die spacer 72. The insulating layer 78 remaining above the other features ensures that the etchant included in the planarization process etches only the material of the insulating layer 78, thereby achieving a flat upper surface more effectively and efficiently. The resulting flatter surface improves the efficiency and yield of subsequent steps (such as forming an overlying dielectric bonding layer 82 and bonding pads 84). In addition, the bonding of the second integrated circuit die 50B (and optionally, the second bridge die 80B or the dummy die) is improved. The packaged semiconductor device can undergo further processing, including similar steps to improve the attachment of the third integrated circuit die 50C. According to various embodiments, the packaged semiconductor device can be assembled with higher efficiency and increased yield (such as thereby reducing costs), and has improved performance.

[0095] In an embodiment, a method includes: attaching a first die and a second die to a substrate, the first die including a via; forming a die spacer between the first die and the second die; thinning the first die and the second die, wherein after thinning the first die and the second die, the die spacer protrudes a first height above an upper surface of the first die; depositing an insulating layer over the first die and the second die; planarizing the insulating layer, wherein after planarization, the insulating layer has a first thickness above the first die and a second thickness above the die spacer; attaching a third die and a fourth die to the first die and the second die; and attaching a supporting substrate to the third die and the fourth die. In another embodiment, after thinning the first die and the second die, the via of the first die protrudes a second height above the upper surface of the first die. In another embodiment, the second height is greater than the first height. In another embodiment, the method further includes: depositing a dielectric bonding layer over the insulating layer; and forming bonding pads in the dielectric bonding layer, the bonding pads electrically coupled to the vias. In another embodiment, attaching the third die and the fourth die includes bonding die connectors and dielectric layers dielectric-to-dielectric and metal-to-metal to the bonding pads and the dielectric bonding layer, respectively. In another embodiment, the first thickness is greater than the second thickness. In another embodiment, the first die includes a via liner located around the via, and wherein after thinning the first die and the second die, the via liner has a third height above the upper surface of the first die, the second height being greater than the third height. In another embodiment, the first height is the same as the third height. In another embodiment, forming the die spacer includes: conformally depositing a first dielectric layer over and between the first die and the second die, the first dielectric layer being a first composition; conformally depositing a second dielectric layer over the first dielectric layer, the second dielectric layer being a second composition; conformally depositing a third dielectric layer over the second dielectric layer, the third dielectric layer being the first composition; and conformally depositing a fourth dielectric layer over the third dielectric layer, the fourth dielectric layer being the second composition. In another embodiment, the first composition is silicon oxide, and wherein the second composition is silicon nitride.

[0096] In an embodiment, a semiconductor package includes: a first tube core, located on a first substrate, the first tube core includes a first conductive via extending through the first semiconductor substrate, the first conductive via protruding a first height above the first semiconductor substrate; a second tube core, located on the substrate and laterally displaced relative to the first tube core, the second tube core includes a second conductive via extending through the second semiconductor substrate, the second conductive via protruding a second height above the second semiconductor substrate; a first tube core spacer, located on the substrate and between the first tube core and the second tube core, the first tube core spacer being located on the first substrate a third die protruding above the bottom of the first tube core; an insulating layer located above the first via, the second via and the first tube core spacer and surrounding the sidewalls of the first via, the second via and the first tube core spacer; a third tube core located above the first tube core and the second tube core, the third tube core being electrically connected to the first tube core; a fourth tube core being laterally displaced relative to the third tube core; and a second tube core spacer located between the third tube core and the fourth tube core, the lowermost surface of the third tube core, the lowermost surface of the fourth tube core and the lowermost surface of the second tube core spacer being flush. In another embodiment, the second tube core spacer protrudes a third height above the third semiconductor substrate of the third tube core, wherein the third height is less than the first height and the second height. In another embodiment, the semiconductor package further includes a dielectric bonding layer and a bonding pad sandwiched between the first tube core and the third tube core, and the uppermost surface of the dielectric bonding layer and the uppermost surface of the bonding pad are in physical contact with the lowermost surface of the third tube core, the lowermost surface of the fourth tube core, and the lowermost surface of the second tube core spacer. In another embodiment, the third tube core includes a stack of multiple tube cores, and the sidewalls of the multiple tube cores are flush. In another embodiment, the fourth tube core is a bridge tube core without active devices, and the bridge tube core is electrically connected to the fourth tube core. In another embodiment, the semiconductor package further includes a fifth tube core located above the third tube core and the fourth tube core, and the fifth tube core is electrically connected to the third tube core and the fourth tube core.

[0097] In an embodiment, a semiconductor package includes: a first die and a second die, which are located on a substrate, the active side of the first die facing the substrate, the first die including: an internal connection structure, adjacent to the substrate; a semiconductor substrate, which is located on the internal connection structure, the farthest surface of the semiconductor substrate being at a first distance from the substrate; a via, which extends through the semiconductor substrate, the farthest point of the via being at a second distance from the substrate; and a dielectric via liner, which is located around the via and sandwiched between the via and the semiconductor substrate, the farthest point of the dielectric via liner being at a third distance from the substrate; a die spacer, which is sandwiched between the sidewalls of the first die and the sidewalls of the second die, the lower surface of the first die is flush with the lower surface of the die spacer, the farthest point of the die spacer being at a fourth distance from the substrate, the second distance being greater than the fourth distance, and the fourth distance being greater than the first distance; and an insulating layer, which is located on the first die and the second die, the farthest surface of the insulating layer being at a fifth distance from the substrate, the fifth distance being greater than the second distance. In another embodiment, the third distance is the same as the fourth distance. In another embodiment, the die spacer comprises a plurality of U-shaped dielectric layers and an innermost dielectric layer. In another embodiment, the plurality of U-shaped dielectric layers and the innermost dielectric layer have alternating chemical compositions.

[0098] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the utility model, rather than to limit them. Although the embodiments of the utility model are described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the utility model.

Claims

1. A semiconductor package, characterized in that: include: A first tube core is located on the substrate, the first tube core includes a first conductive via extending through the first semiconductor substrate, and the first conductive via protrudes a first height above the first semiconductor substrate; a second die disposed over the substrate and laterally displaced relative to the first die, the second die comprising a second via extending through the second semiconductor substrate, the second via protruding a second height above the second semiconductor substrate; a first die spacer located on the substrate and between the first die and the second die, the first die spacer protruding above the substrate by a third height; an insulating layer located on the first via, the second via, and the first die spacer and surrounding a sidewall of the first via, the second via, and the first die spacer; A third tube die is located above the first tube die and the second tube die, and the third tube die is electrically connected to the first tube die; a fourth tube core, laterally displaced relative to the third tube core; as well as The second tube die spacer is located between the third tube die and the fourth tube die, and the lowermost surface of the third tube die, the lowermost surface of the fourth tube die and the lowermost surface of the second tube die spacer are flush.

2. The semiconductor package according to claim 1, wherein: The second die spacer protrudes a third height above the third semiconductor substrate of the third die, wherein the third height is smaller than the first height and the second height.

3. The semiconductor package according to claim 1, wherein: Also includes: a dielectric bonding layer; and The bonding pad is sandwiched between the first tube core and the third tube core, and the uppermost surface of the dielectric bonding layer and the uppermost surface of the bonding pad are in physical contact with the lowermost surface of the third tube core, the lowermost surface of the fourth tube core and the lowermost surface of the second tube core spacer.

4. The semiconductor package according to claim 1, wherein: The third tube core includes a stack of multiple tube cores, and the sidewalls of the multiple tube cores are flush.

5. The semiconductor package according to claim 1, wherein: The fourth die is a bridge die without active devices, and the bridge die is electrically connected to the fourth die.

6. The semiconductor package according to claim 5, wherein: Also includes: The fifth tube core is located on the third tube core and the fourth tube core, and the fifth tube core is electrically connected to the third tube core and the fourth tube core.

7. A semiconductor package, characterized in that: include: A first tube die and a second tube die are located on a substrate, an active side of the first tube die faces the substrate, and the first tube die includes: an interconnect structure adjacent to the substrate; A semiconductor substrate is located on the interconnect structure, and the farthest point surface of the semiconductor substrate is at a first distance from the substrate; a via extending through the semiconductor substrate, wherein a farthest point of the via is a second distance from the substrate; and a dielectric via liner located around the via and sandwiched between the via and the semiconductor substrate, wherein the farthest point of the dielectric via liner is a third distance away from the substrate; a die spacer sandwiched between the sidewall of the first die and the sidewall of the second die, the lower surface of the first die is flush with the lower surface of the die spacer, the farthest point of the die spacer is at a fourth distance from the substrate, the second distance is greater than the fourth distance, and the fourth distance is greater than the first distance; and An insulating layer is located on the first tube core and the second tube core, and the farthest point surface of the insulating layer is at a fifth distance from the substrate, and the fifth distance is greater than the second distance.

8. The semiconductor package according to claim 7, wherein: The third distance is the same as the fourth distance.

9. The semiconductor package according to claim 7, wherein: The die spacer includes a plurality of U-shaped dielectric layers and an innermost dielectric layer.

10. The semiconductor package according to claim 7, wherein: Also includes: A third tube die is located above the first tube die and the second tube die, and the third tube die is electrically connected to the first tube die; a fourth tube core, laterally displaced relative to the third tube core; as well as The spacer is located between the third tube core and the fourth tube core, and the lowermost surface of the third tube core, the lowermost surface of the fourth tube core and the lowermost surface of the spacer are flush.

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