Fan-out wafer level packaging unit
By using a combined structure of carrier board, dielectric layer and outer cover in fanout wafer-level packaging to form the conductor circuit, the high cost of manufacturing the conductor circuit and environmental protection problems are solved, and the packaging effect is achieved is achieved. Adapt to the packaging needs of multi-chip types and improve the competitiveness of the product.
Patent Information
- Application Number
- CN202420870265.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-25
- Publication Date
- 2025-01-17
- Estimated Expiration
- 2034-04-25
AI Technical Summary
In the existing fan-out wafer-level packaging technology, the production cost of the re-wiring layer (RDL) conductor circuit is high and is not conducive to environmental protection. At the same time, the design space requirement increases when packaging in multi-chip type, making it difficult to maintain the effect of thinness and shortness. .
By adopting a combined structure of a carrier plate, a bare crystal, a first dielectric layer, a second dielectric layer and an outer sheath, a plurality of grooves are formed in the first dielectric layer and the second dielectric layer and a metal paste is filled with Construct the conductor circuit and form a welding pad through the opening of the outer cover layer to realize the electrical connection of the conductor circuit, simplify the process and reduce costs.
It effectively reduces the manufacturing cost of the conductor circuit, simplifies the manufacturing process, improves the lightness, shortness and reliability of the packaging unit, and at the same time adapts to the packaging needs of multi-chip types, and improves the market competitiveness of the products.
Smart Images
Figure CN222365597U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a chip packaging unit, in particular to a fan-out wafer-level packaging unit. Background Art
[0002] Lightweight, thin, short, high-efficiency and high-reliability packaging technology is the development trend of the semiconductor industry, among which Fan-Out Wafer Level Packaging (FOWLP) is already an existing packaging technology.
[0003] In the advanced packaging FOWLP, the redistribution layer (RDL) is the most critical, because each conductive line in the RDL can make multiple pads on the die produce XY plane electrical extension and interconnection, so that multiple more dispersed pads can be formed around each die, which can effectively improve the design space and reliability of each conductive line. However, how to make each conductive line in the RDL maintain or achieve a certain degree of lightness, thinness and shortness while producing XY plane electrical extension and interconnection is the most critical. However, the forming method of each conductive line in the RDL technology used in the existing FOWLP packaging technology is to use chemical plating forming technology or electroplating forming technology to make it. In addition to the relatively high material cost and production cost, the process in the existing technology does not meet or is not conducive to environmental protection requirements.
[0004] In addition, when FOWLP is used to provide products with higher performance or more functions, at least two bare chips are generally set up in FOWLP and integrated through RDL to form a multi-chip fan-out wafer-level packaging unit. At this time, the design space demand for each conductive line of the RDL in FOWLP will increase relatively, and the manufacturing technology of each conductive line in the RDL will also be relatively more critical. Utility Model Content
[0005] The main purpose of the utility model is to provide a fan-out wafer level packaging (FOWLP) unit, which includes a carrier, a bare die, a first dielectric layer, a second dielectric layer, a plurality of conductive lines and an outer protective layer, each conductive line is formed by filling a plurality of first grooves in the first dielectric layer and a plurality of second grooves in the second dielectric layer with metal paste, one end of each conductive line is electrically connected to a plurality of crystal pads of each bare die, and the other end is exposed to the outside through a plurality of openings in the outer protective layer and a welding pad is formed in each opening, and at least one welding pad is located around a chip area on the second surface of each bare die to form a fan-out wafer level packaging (FOWLP) unit; wherein each bare die is electrically connected to the outside through each crystal pad, each conductive line and each welding pad, effectively solving the problem that the existing fan-out packaging technology is prone to generate higher manufacturing costs and is not environmentally friendly when manufacturing each conductive line.
[0006] To achieve the above-mentioned object, the utility model provides a fan-out wafer-level packaging unit, which includes a carrier, at least two dies, a first dielectric layer, a second dielectric layer, a plurality of conductive lines and an outer protective layer; the at least two dies are each divided from the same wafer or different wafers, each of the dies is parallel and spaced side by side on the carrier, each of the dies has a first surface and an opposite second surface, the first surface of each of the dies is fixed on the carrier, the second surface of each of the dies has a plurality of crystal pads, and the vertical chip area of the second surface is defined as a chip area; the first dielectric layer is disposed on the carrier and the second surface of each of the dies, the first dielectric layer has a plurality of first grooves formed extending in a horizontal direction, wherein each of the crystal pads of each of the dies is exposed to the outside by each of the first grooves; The second dielectric layer is disposed on the first dielectric layer, and the second dielectric layer has a plurality of second grooves extending in a horizontal direction, and each of the second grooves is connected to each of the first grooves; each of the conductive circuits is formed by filling a metal paste in each of the first grooves and each of the second grooves, and each of the conductive circuits is electrically connected to each of the crystal pads of each of the bare crystals; the outer protective layer is disposed on the second dielectric layer, and the outer protective layer has a plurality of openings, and at least two of the openings are located around the chip area on the second side of each of the bare crystals, wherein each of the conductive circuits is exposed to the outside by each of the openings and a solder pad is formed in each of the openings; each of the bare crystals can be electrically connected to the outside in sequence through each of the crystal pads, each of the conductive circuits, and each of the solder pads located around the chip area on the second side of each of the bare crystals, thereby forming the fan-out wafer-level packaging unit.
[0007] In a preferred embodiment of the present invention, each of the bare dies is formed by being divided from the same wafer.
[0008] In a preferred embodiment of the present invention, each of the bare dies is formed by being divided from different wafers.
[0009] In a preferred embodiment of the present invention, the horizontal heights of the second surfaces of each of the bare die on the carrier are the same.
[0010] In a preferred embodiment of the present invention, the carrier includes a silicon (Si) carrier, a glass carrier or a ceramic carrier.
[0011] In a preferred embodiment of the present invention, the metal paste includes silver paste, nano silver paste, copper paste or nano copper paste.
[0012] In a preferred embodiment of the present invention, the first surface of each of the bare chips is further disposed on the carrier by using a die attach film (DAF).
[0013] In a preferred embodiment of the present invention, a solder ball is further disposed on each of the openings, and each of the solder balls can be electrically connected to each of the pads in each of the openings.
[0014] In a preferred embodiment of the present invention, the fan-out wafer-level packaging unit can be disposed on a printed circuit board (PCB) by electrically connecting each of the solder balls. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 It is a side cross-sectional schematic diagram of the fan-out wafer-level packaging unit of the utility model being arranged on a printed circuit board.
[0016] Figure 2 It is a side cross-sectional schematic diagram of a bare die of the utility model being arranged on a carrier board.
[0017] Figure 3 It is a side cross-sectional schematic diagram of the utility model in which the first dielectric layer is arranged on the second surface of the carrier and the bare die.
[0018] Figure 4 It is a side cross-sectional schematic diagram of the second dielectric layer of the utility model arranged on the first dielectric layer.
[0019] Figure 5 It is a side cross-sectional schematic diagram of the first groove and the second groove of the utility model filled with metal paste.
[0020] Figure 6 yes Figure 5 A side cross-sectional schematic diagram of grinding the metal paste above the surface of the second dielectric layer.
[0021] Figure 7 It is a side cross-sectional schematic diagram of the utility model in which a plurality of openings are formed on the outer protective layer.
[0022] Figure 8 It is a side cross-sectional schematic diagram of the fan-out wafer-level packaging unit of the utility model.
[0023] Explanation of reference numerals: 1-fan-out wafer-level packaging unit; 1a-chip area; 10-carrier; 20-bare die; 20a-first bare die; 20b-second bare die; 21-first surface; 22-second surface; 23-crystal pad; 30-first dielectric layer; 31-first groove; 40-second dielectric layer; 41-second groove; 50-conducting line; 50a-metal paste; 60-outer protective layer; 61-opening; 70-die bonding film; 80-solder ball; 2-printed circuit board. . DETAILED DESCRIPTION
[0024] With the help of illustrations, the structure and technical features of the present invention are described in detail as follows, wherein each illustration is only used to illustrate the structural relationship and related functions of the present invention, so the size of each element in each illustration is not drawn according to the actual scale and is not used to limit the present invention.
[0025] refer to Figure 1 The utility model provides a fan-out wafer level packaging (FOWLP) unit 1, which includes a carrier 10, at least two bare chips (dies) 20, a first dielectric layer 30, a second dielectric layer 40, a plurality of conductive lines 50 and an outer protective layer 60.
[0026] The carrier 10 includes a silicon (Si) carrier, a glass carrier or a ceramic carrier but is not limited to Figure 2 As shown, it is conducive to diversified product development and application.
[0027] Each die 20 is separated from the same wafer or different wafers. Each die 20 is arranged parallel and spaced apart on the carrier 10. Each die 20 has a first surface 21 and an opposite second surface 22. The first surface 21 of each die 20 is fixed on the carrier 10. The second surface 22 of each die 20 has a plurality of die pads 23. The vertical chip area of the second surface 22 is defined as a chip area 1a. Figure 2 As shown. Figure 2 The wafer pads 23 of each bare die 20 are described by taking two wafer pads 23 as an example, but the present invention is not limited thereto.
[0028] In addition, in order to illustrate the structural relationship and related functions of the utility model, Figures 1 to 8In the illustrated embodiment, each bare die 20 on the carrier 10 further includes a first bare die 20 a and a second bare die 20 b , but this is not limiting. That is, two bare die 20 are used as an example for illustration but are not intended to limit the present invention.
[0029] The first dielectric layer 30 is disposed on the second surface 22 of the carrier 10 and each of the bare die 20 (the first bare die 20a and the second bare die 20b). The first dielectric layer 30 has a plurality of first grooves 31 extending in a horizontal direction. Figure 3 wherein each of the die pads 23 of each die 20 (the first die 20a and the second die 20b) is exposed to the outside by each first groove 31, such as Figure 3 shown.
[0030] The second dielectric layer 40 is disposed on the first dielectric layer 30. The second dielectric layer 40 has a plurality of second grooves 41 extending in a horizontal direction. Each second groove 41 is connected to each first groove 31. Figure 4 shown.
[0031] Each conductive circuit 50 is formed by a metal paste 50a filled in each first groove 31 and each second groove 41. Each conductive circuit 50 is electrically connected to each die pad 23 of each bare die 20 (the first bare die 20a and the second bare die 20b). Figure 6 As shown; wherein the metal paste 50a includes silver paste, nano silver paste, copper paste or nano copper paste, but is not limited. The nano silver paste material has the characteristics of low cost, high conductivity and low temperature sintering, but since the nano silver paste material is a common material, it is not described here.
[0032] The outer protective layer 60 is disposed on the second dielectric layer 40, and the outer protective layer 60 has a plurality of openings 61, and at least two of the openings 61 are located around the chip region 1a on the second surface 22 of each die 20 (the first die 20a and the second die 20b). Figure 7 wherein each conductive circuit 50 is exposed to the outside by each opening 61 and a pad 51 is formed in each opening 61, such as Figure 7 As shown. Figure 7 In the figure, the openings 61 of the outer protective layer 60 are described by taking two openings 61 as an example, but this is not intended to limit the present invention.
[0033] Each die 20 (the first die 20a and the second die 20b) can be electrically connected to the outside via each die pad 23, each conductive circuit 50, and each pad 51 located around the chip region 1a on the second surface 22 of each die 20 (the first die 20a and the second die 20b), so as to form the fan-out wafer-level packaging unit 1, as shown in FIG. Figure 7 shown.
[0034] The fan-out wafer-level packaging unit 1 can be manufactured by the following steps, but is not limited thereto:
[0035] Step S1: Provide a carrier board 10, such as Figure 2 shown.
[0036] Step S2: multiple dies 20 separated from the same wafer or different wafers are arranged parallely and spaced apart on the carrier 10, such as Figure 2 As shown; wherein each bare crystal 20 has a first surface 21 and an opposite second surface 22, the first surface 21 of each bare crystal 20 is disposed on the carrier 10, and the second surface 22 of each bare crystal 20 has a plurality of pads 23, and the vertical chip area of the second surface 22 is defined as a chip area 1a, such as Figure 2 shown.
[0037] Step S3: Lay a first dielectric layer 30 on the carrier 10 and the second surface 22 of each bare die 20. Figure 3 shown.
[0038] Step S4: forming a plurality of first grooves 31 extending horizontally on the first dielectric layer 30, and allowing each die pad 23 of each bare die 20 to be exposed to the outside through each first groove 31. Figure 3 shown.
[0039] Step S5: Lay a second dielectric layer 40 on the first dielectric layer 30. Figure 4 shown.
[0040] Step S6: forming a plurality of second grooves 41 extending horizontally on the second dielectric layer 40, and making each second groove 41 communicate with each first groove 31, such as Figure 4 shown.
[0041] Step S7: Filling a metal paste 50a into each of the first grooves 31 and each of the second grooves 41, and making the thickness of the metal paste 50a higher than the surface of the second dielectric layer 40, such as Figure 5 shown.
[0042] Step S8: Grind the metal paste 50a above the surface of the second dielectric layer 40 so that the surface of the metal paste 50a is flush with the surface of the second dielectric layer 40 to form a plurality of conductive circuits 50, such as Figure 6 shown.
[0043] Step S9: Lay an outer protective layer 60 on the second dielectric layer 40, such as Figure 7 shown.
[0044] Step S10: forming a plurality of openings 61 on the outer protective layer 60 and forming at least one of the openings 61 around the chip region 1a on the second surface 22 of each bare die 20, so that each conductive circuit 50 can be exposed to the outside through each opening 61 and a bonding pad 51 is formed in each opening 61, such as Figure 7 shown.
[0045] Step S11: Perform a segmentation operation and segment a package with at least two bare die 20 (the first bare die 20a and the second bare die 20b) as a unit to form a plurality of fan-out wafer-level package units 1, such as Figure 7 As shown, in Figure 7 The fan-out wafer-level packaging units 1 shown in the figure are described by taking one fan-out wafer-level packaging unit 1 as an example, but are not intended to limit the present invention.
[0046] In the above-mentioned process of manufacturing the fan-out wafer-level packaging unit 1, the process of step S3 to step S10 can be regarded as the key steps of manufacturing the redistribution layer (RDL) of the fan-out wafer-level packaging unit 1, wherein step S4 is to form a plurality of first grooves 31 extending horizontally on the first dielectric layer 30, step S6 is to form a plurality of second grooves 41 extending horizontally on the second dielectric layer 40, step S7 is to fill a metal paste 50a into each of the first grooves 31 and each of the second grooves 41, and step S8 is to grind the metal paste 50a that is higher than the surface of the second dielectric layer 40 so that the surface of the metal paste 50a is flush with the surface of the second dielectric layer 40 to form Since steps S4 to S8 are processes that are easy to implement precisely, the process is relatively simple, which is sufficient to enable each conductive circuit 50 in the redistribution layer to produce XY plane electrical extension and interconnection. At the same time, the fan-out wafer-level packaging unit 1 can still maintain or achieve a certain degree of lightness, thinness and shortness. When there are at least two bare chips 20 in the fan-out wafer-level packaging unit 1, it can still maintain or achieve a certain degree of lightness, thinness and shortness.
[0047] refer to Figure 2 When each bare die 20 is formed by being divided from the same wafer, each bare die 20 has the same specification, performance or intended function, but this is not limited.
[0048] refer to Figure 2 When each bare die 20 is formed by being cut from different wafers, it is beneficial to increase the diversified application of the product. Each bare die 20 can be a bare die with different specifications, performance or intended functions, but it is not limited to Figure 2 The first bare die 20a is smaller in size than the second bare die 20b.
[0049] refer to Figure 2 The horizontal heights of the second surfaces 22 of the bare crystals 20 on the carrier 10 are the same but not limited, so that the first grooves 31 of the first dielectric layer 30 and the second grooves 41 of the second dielectric layer 40 formed by the RDL technology can be extended and formed smoothly, which helps the subsequent structures stacked on the bare crystals 20 to maintain better structural flatness to increase the reliability of the product.
[0050] refer to Figure 2 The first surface 21 of each bare die 20 is further disposed on the carrier 10 using a die attach film (DAF, Die Attach Film) 70 but is not limited thereto.
[0051] refer to Figure 8 , each opening 61 is further provided with a solder ball 80 but is not limited thereto, and each solder ball 80 can be electrically connected to each solder pad 51 in each opening 61 .
[0052] refer to Figure 1 The fan-out wafer-level packaging unit 1 can be electrically connected to a printed circuit board (PCB) 2 using each solder ball 80, but is not limited thereto.
[0053] Compared with the existing fan-out wafer-level packaging unit technology, the fan-out wafer-level packaging unit 1 of the utility model has the following advantages:
[0054] (1) In steps S3 to S10 of the manufacturing process of the fan-out wafer-level packaging unit 1 of the present invention, compared with the related manufacturing technology of the existing fan-out wafer-level packaging unit, the present invention can make each conductive line in the RDL produce each conductive line in the RDL while generating XY plane electrical extension and interconnection, while also maintaining or achieving a certain degree of lightness, thinness and shortness. These are simplified and easy to implement precisely, and are particularly helpful in reducing the thickness of the packaging unit. Therefore, the manufacturing process of the present invention is not only relatively simplified and cost-saving, but also can effectively improve the use efficiency and reliability of the fan-out wafer-level packaging unit 1.
[0055] (2) In the process of forming each conductive circuit 50 of the present invention, the metal paste 50a may be first filled into each first groove 31 and each second groove 41, and the thickness of the metal paste 50a is higher than the surface of the second dielectric layer 40. Figure 5 As shown, the metal paste 50a which is higher than the surface of the second dielectric layer 40 is then ground so that the surface of the metal paste 50a is flush with the surface of the second dielectric layer 40 to form each conductive circuit 50, as shown in FIG. Figure 6As shown, the manufacturing of the utility model can effectively solve the problems of the existing fan-out packaging technology that the manufacturing of each conductive circuit is prone to generate high manufacturing costs and is not conducive to environmental protection.
[0056] (3) Each bare die 20 of the present invention can be electrically connected to the outside via each die pad 23, each conductive line 50 (formed by RDL technology) and each pad 51 located around the chip area 1a on the second surface 22 of each bare die 20 in sequence. That is, each conductive line in the RDL can generate XY plane electrical extension and interconnection while also enabling the multi-chip fan-out wafer-level packaging unit to maintain or achieve a certain degree of light, thin and short integration effect, so as to provide a product with higher performance (e.g., each bare die 20 is a bare die with the same specification, performance or intended function) or more functions (e.g., each bare die 20 is a bare die with different specifications, performance or intended function), thereby increasing the market competitiveness of the product.
[0057] The above are only preferred embodiments of the present invention, which are only illustrative rather than restrictive of the present invention. A person skilled in the art will understand that many changes, modifications, and even equivalent changes may be made to the present invention within the spirit and scope defined by the claims of the present invention, but all of these will fall within the scope of protection of the present invention.
Claims
1. A fan-out wafer-level packaging unit, characterized in that: Include: a carrier board; At least two bare die, each of which is separated from the same wafer or different wafers, each of which is parallel and spaced apart and arranged side by side on the carrier, each of which has a first surface and an opposite second surface, the first surface of each of which is fixed on the carrier, the second surface of each of which has a plurality of die pads, and a vertical chip area of the second surface is defined as a chip area; A first dielectric layer is disposed on the carrier and the second surface of each of the bare crystals, the first dielectric layer having a plurality of first grooves extending in a horizontal direction; wherein each of the crystal pads of each of the bare crystals is exposed to the outside through each of the first grooves; A second dielectric layer is disposed on the first dielectric layer, the second dielectric layer having a plurality of second grooves extending in a horizontal direction, each of the second grooves being connected to each of the first grooves; A plurality of conducting circuits, each of which is formed by a metal paste filled in each of the first grooves and each of the second grooves, and each of the conducting circuits is electrically connected to each of the die pads of each of the bare die; and An outer protective layer is disposed on the second dielectric layer, the outer protective layer has a plurality of openings and at least two of the openings are located around the chip region on the second surface of each die; Each of the conductive lines is exposed to the outside through each of the openings and a welding pad is formed in each of the openings; Each of the bare die can be electrically connected to the outside via each of the die pads, each of the conducting circuits and each of the bonding pads around the chip region on the second surface of each of the bare die in sequence, so as to form the fan-out wafer-level packaging unit.
2. The fan-out wafer-level packaging unit according to claim 1, characterized in that: Each of the dies is formed by being separated from the same wafer.
3. The fan-out wafer-level packaging unit according to claim 1, characterized in that: Each of the bare dies is separated from a different wafer.
4. The fan-out wafer-level packaging unit according to claim 1, characterized in that: The level heights of the second surfaces of each of the bare die on the carrier are the same.
5. The fan-out wafer level packaging unit according to claim 1, characterized in that: The carrier includes a silicon carrier, a glass carrier or a ceramic carrier.
6. The fan-out wafer level packaging unit according to claim 1, characterized in that: The metal paste includes silver paste, nano silver paste, copper paste or nano copper paste.
7. The fan-out wafer level packaging unit according to claim 1, characterized in that: The first surface of each bare die is further disposed on the carrier using a die attach film.
8. The fan-out wafer-level packaging unit according to claim 1, characterized in that: A solder ball is further disposed on each of the openings, and each of the solder balls can be electrically connected to each of the pads in each of the openings.
9. The fan-out wafer-level packaging unit according to claim 8, characterized in that: The fan-out wafer-level packaging unit can be electrically connected to a printed circuit board by using each solder ball.