Fan-out wafer level packaging unit
By filling metal paste with dielectric layer grooves in fanout wafer-level packaging and forming a guide line, the high cost and environmental protection problems of the guide line are solved, and the electrical extension and interconnection of the guide line are realized. At the same time, the packaging is thin and short.
Patent Information
- Application Number
- CN202420870483.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-25
- Publication Date
- 2025-01-17
- Estimated Expiration
- 2034-04-25
AI Technical Summary
In the existing fan-out wafer-level packaging technology, the production cost of the re-wiring layer (RDL) conductor circuit is high and is not conducive to environmental protection, and it is difficult to achieve light and short effects while maintaining electrical extension and interconnection.
Using a guide line composed of metal paste in the first dielectric layer and the second dielectric layer, a guide line is formed by filling the dielectric layer groove and grinding it, and forming it at the opening of the outer cover layer. Solder pads to achieve electrical connection and exposure of the conductor lines.
It reduces the cost of conductor wiring, simplifies the process, improves the lightness, shortness and efficiency of packaging units, and meets environmental protection requirements.
Smart Images
Figure CN222365598U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a chip packaging unit, in particular to a fan-out wafer-level packaging unit. Background Art
[0002] Lightweight, thin, short, high-efficiency and high-reliability packaging technology is the development trend of the semiconductor industry, among which Fan-Out Wafer Level Packaging (FOWLP) is already an existing packaging technology.
[0003] In the advanced packaging FOWLP, the redistribution layer (RDL) is the most critical, because each conductive line in the RDL can make multiple pads on the bare die produce XY plane electrical extension and interconnection, so as to form a plurality of more dispersed pads around the bare die, thereby effectively improving the design space and reliability of each conductive line. However, how to make each conductive line in the RDL maintain or achieve a certain degree of lightness, thinness and shortness while producing XY plane electrical extension and interconnection is the most critical.
[0004] However, the RDL technology used in the existing FOWLP packaging technology is formed by using chemical plating or electroplating techniques to form each conductive line. In addition to the relatively high material cost and production cost, the process in the existing technology does not meet or is not conducive to environmental protection requirements. Utility Model Content
[0005] The main purpose of the utility model is to provide a fan-out wafer level packaging (FOWLP) unit, which includes a carrier, a bare die, a first dielectric layer, a second dielectric layer, a plurality of conductive lines and an outer protective layer, each conductive line is formed by filling a plurality of first grooves in the first dielectric layer and a plurality of second grooves in the second dielectric layer with a metal paste, one end of each conductive line is electrically connected to a plurality of crystal pads of the bare die, and the other end is exposed to the outside through a plurality of openings in the outer protective layer and a welding pad is formed in each opening, and at least one welding pad is located around a chip area on the second surface of the bare die to form a fan-out wafer level packaging (FOWLP) unit; wherein the bare die is electrically connected to the outside through each crystal pad, each conductive line and each welding pad, effectively solving the problem that the existing fan-out packaging technology is prone to generate a higher manufacturing cost and is not conducive to environmental protection when manufacturing each conductive line.
[0006] To achieve the above-mentioned purpose, the utility model provides a fan-out wafer-level packaging unit, which includes a carrier, a bare die, a first dielectric layer, a second dielectric layer, a plurality of conductive lines and an outer protective layer; wherein the bare die is split from a wafer, the bare die has a first surface and an opposite second surface, the first surface of the bare die is fixed on the carrier, the second surface of the bare die has a plurality of crystal pads, and the vertical chip area of the second surface is defined as a chip area; wherein the first dielectric layer is arranged on the carrier and the second surface of the bare die, the first dielectric layer has a plurality of first grooves formed extending in a horizontal direction, wherein each of the crystal pads of the bare die is exposed to the outside by each of the first grooves; wherein the second dielectric layer is arranged on the first dielectric layer, the first dielectric layer has a plurality of first grooves ... The two dielectric layers have a plurality of second grooves extending in a horizontal direction, each of the second grooves being connected to each of the first grooves; each of the conductive circuits is formed by a metal paste filled in each of the first grooves and each of the second grooves, and each of the conductive circuits is electrically connected to each of the crystal pads of the bare crystal; the outer protective layer is disposed on the second dielectric layer, and the outer protective layer has a plurality of openings, and at least one of the openings is located around the chip area on the second side of the bare crystal; each of the conductive circuits is exposed to the outside by each of the openings, and a solder pad is formed in each of the openings; the bare crystal can be electrically connected to the outside in sequence through each of the crystal pads, each of the conductive circuits, and each of the solder pads located around the chip area on the second side of the bare crystal, thereby forming the fan-out wafer-level packaging unit.
[0007] In a preferred embodiment of the present invention, the carrier includes a silicon (Si) carrier, a glass carrier or a ceramic carrier.
[0008] In a preferred embodiment of the present invention, the metal paste includes silver paste, nano silver paste, copper paste or nano copper paste.
[0009] In a preferred embodiment of the present invention, the first surface of the bare die is further fixedly disposed on the carrier by using a die attach film (DAF).
[0010] In a preferred embodiment of the present invention, a solder ball is further provided on each of the second grooves, and each of the solder balls can be electrically connected to each of the pads in each of the openings, so that the fan-out wafer-level packaging unit can be electrically connected to a printed circuit board (PCB) using each of the solder balls. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Figure 1The utility model is a side cross-sectional schematic diagram of a fan-out wafer-level packaging unit arranged on a printed circuit board.
[0012] Figure 2 It is a side cross-sectional schematic diagram of a bare die of the utility model being arranged on a carrier board.
[0013] Figure 3 It is a side cross-sectional schematic diagram of the utility model in which the first dielectric layer is arranged on the second surface of the carrier and the bare die.
[0014] Figure 4 It is a side cross-sectional schematic diagram of the second dielectric layer of the utility model being arranged on the first dielectric layer.
[0015] Figure 5 It is a side cross-sectional schematic diagram of the first groove and the second groove of the utility model filled with metal paste.
[0016] Figure 6 yes Figure 5 A side cross-sectional schematic diagram of grinding the metal paste above the surface of the second dielectric layer.
[0017] Figure 7 It is a side cross-sectional schematic diagram of the utility model in which a plurality of openings are formed on the outer protective layer.
[0018] Figure 8 It is a side cross-sectional schematic diagram of the fan-out wafer-level packaging unit of the utility model.
[0019] Explanation of the reference numerals: 1-fan-out wafer-level packaging unit; 1a-chip area; 10-carrier; 20-bare crystal; 20a-first side; 20b-second side; 21-crystal pad; 30-first dielectric layer; 31-first groove; 40-second dielectric layer; 41-second groove; 50-conducting line; 50a-metal paste; 60-outer protective layer; 61-opening; 70-chip bonding film; 80-solder ball; 2-printed circuit board. DETAILED DESCRIPTION
[0020] With the help of illustrations, the structure and technical features of the present invention are described in detail as follows, wherein each illustration is only used to illustrate the structural relationship and related functions of the present invention, so the size of each element in each illustration is not drawn according to the actual scale and is not used to limit the present invention.
[0021] refer to Figure 1 The utility model provides a fan-out wafer level packaging (FOWLP) unit 1, which includes a carrier 10, a die 20, a first dielectric layer 30, a second dielectric layer 40, a plurality of conductive lines 50 and an outer protective layer 60.
[0022] The carrier 10 includes a silicon (Si) carrier, a glass carrier, or a ceramic carrier but is not limited thereto. Figure 2 shown.
[0023] The bare die 20 is cut from a wafer and has a first surface 20a and an opposite second surface 20b. The first surface 20a of the bare die 20 is fixed on the carrier 10. The second surface 20b of the bare die 20 has a plurality of pads 21, and a vertical chip area of the second surface 20b is defined as a chip area 1a. Figure 2 As shown. Figure 2 In the figure, the die pads 21 of the bare die 20 are described by taking two die pads 21 as an example, but this is not intended to limit the present invention.
[0024] The first dielectric layer 30 is disposed on the carrier 10 and the second surface 20b of the die 20. The first dielectric layer 30 has a plurality of first grooves 31 extending in a horizontal direction. Figure 3 wherein each crystal pad 21 of the bare crystal 20 is exposed to the outside by each first groove 31, such as Figure 3 shown.
[0025] The second dielectric layer 40 is disposed on the first dielectric layer 30. The second dielectric layer 40 has a plurality of second grooves 41 extending in a horizontal direction. Each second groove 41 is connected to each first groove 31. Figure 4 shown.
[0026] Each conductive circuit 50 is formed by a metal paste 50a filled in each first groove 31 and each second groove 41. Each conductive circuit 50 is electrically connected to each die pad 21 of the bare die 20. Figure 6 As shown; wherein the metal paste 50a includes silver paste, nano silver paste, copper paste or nano copper paste, but is not limited. The nano silver paste material has the characteristics of low cost, high conductivity and low temperature sintering, but since the nano silver paste material is a common material, it is not described here.
[0027] The outer protective layer 60 is disposed on the second dielectric layer 40. The outer protective layer 60 has a plurality of openings 61, and at least one of the openings 61 is located around the chip region 1a on the second surface 20b of the die 20. Figure 7 wherein each conductive circuit 50 is exposed to the outside by each opening 61 and a pad 51 is formed in each opening 61, such as Figure 7 As shown. Figure 7 The openings 61 of the outer protective layer 60 are described by taking four openings 61 as an example, but this is not intended to limit the present invention.
[0028] The bare die 20 can be electrically connected to the outside through each die pad 21, each conductive circuit 50 and each pad 51 around the chip region 1a on the second surface 20b of the bare die 20 in sequence, so as to form the fan-out wafer-level packaging unit 1. Figure 7 shown.
[0029] The fan-out wafer-level packaging unit 1 of the utility model can be manufactured by the following method, but is not limited thereto, including:
[0030] Step S1: Provide a carrier board 10, such as Figure 2 shown.
[0031] Step S2: a plurality of dies 20 separated from at least one wafer are fixedly disposed on the carrier 10 at intervals, such as Figure 2 As shown, in Figure 2 The bare die 20 disposed on the carrier 10 is illustrated by taking one of the bare die 20 as an example but is not intended to limit the present invention; wherein each bare die 20 has a first surface 20a and an opposite second surface 20b, the first surface 20a of each bare die 20 is disposed on the carrier 10, the second surface 20b of each bare die 20 has a plurality of die pads 21, and the vertical chip area of the second surface 20b is defined as a chip area 1a, such as Figure 2 shown.
[0032] Step S3: Lay a first dielectric layer 30 on the carrier 10 and the second surface 20b of each bare die 20. Figure 3 shown.
[0033] Step S4: forming a plurality of first grooves 31 extending horizontally on the first dielectric layer 30, and allowing each die pad 21 of each bare die 20 to be exposed to the outside through each first groove 31. Figure 3 shown.
[0034] Step S5: Lay a second dielectric layer 40 on the first dielectric layer 30. Figure 4 shown.
[0035] Step S6: forming a plurality of second grooves 41 extending horizontally on the second dielectric layer 40, and making each second groove 41 communicate with each first groove 31, such as Figure 4 shown.
[0036] Step S7: Fill each first groove 31 and each second groove 41 with a metal paste 50a, and the thickness of the metal paste 50a is higher than the surface of the second dielectric layer 40, indicating that the metal paste 50a has completely filled each first groove 31 and each second groove 41. Figure 5 shown.
[0037] Step S8: Grind the metal paste 50a above the surface of the second dielectric layer 40 so that the surface of the metal paste 50a is flush with the surface of the second dielectric layer 40 to form a plurality of conductive circuits 50, such as Figure 6 shown.
[0038] Step S9: Lay an outer protective layer 60 on the second dielectric layer 40, such as Figure 7 shown.
[0039] Step S10: forming a plurality of openings 61 on the outer protective layer 60 and forming at least one of the openings 61 around the chip region 1a on the second surface 20b of the bare die 20, so that each conductive circuit 50 can be exposed to the outside through each opening 61 and a bonding pad 51 is formed in each opening 61, such as Figure 7 shown.
[0040] Step S11: Perform a segmentation operation to segment and form a plurality of fan-out wafer-level packaging units 1, such as Figure 7 As shown, in Figure 7 The fan-out wafer-level packaging units 1 shown in the figure are illustrated by taking one fan-out wafer-level packaging unit 1 as an example but are not intended to limit the present invention.
[0041] The processes of step S3 to step S10 in the manufacturing method of the fan-out wafer-level packaging unit 1 can be regarded as the key steps of manufacturing the redistribution layer (RDL) of the fan-out wafer-level packaging unit 1, wherein step S4 is to form a plurality of first grooves 31 extending horizontally on the first dielectric layer 30, step S6 is to form a plurality of second grooves 41 extending horizontally on the second dielectric layer 40, step S7 is to fill a metal paste 50a into each of the first grooves 31 and each of the second grooves 41, step S8 is to grind the metal paste 50a above the surface of the second dielectric layer 40 so that the surface of the metal paste 50a is flush with the surface of the second dielectric layer 40 to form a plurality of conductive lines 50, and since steps S4 to S8 are processes that are easy to implement precisely, the process is relatively simplified, which is sufficient to make the redistribution layer (RDL) Each conductive circuit 50 in the layer generates XY plane electrical extension and interconnection, while also enabling the completed fan-out wafer-level packaging unit 1 to maintain or achieve a certain degree of lightness, thinness and compactness.
[0042] refer to Figure 2 The first surface 20 a of the bare die 20 is further fixedly disposed on the carrier 10 by using a die attach film (DAF, Die Attach Film) 70, but it is not limited thereto.
[0043] refer to Figure 8A solder ball 80 is further disposed on each second groove 41 but is not limited thereto. Each solder ball 80 can be electrically connected to each solder pad 51 in each opening 61 .
[0044] refer to Figure 1 The fan-out wafer-level packaging unit 1 can be electrically connected to a printed circuit board (PCB) 2 using each solder ball 80, but is not limited thereto.
[0045] Compared with the existing fan-out wafer-level packaging unit technology, the fan-out wafer-level packaging unit 1 of the utility model has the following advantages:
[0046] (1) Compared with the related manufacturing technology of the existing fan-out wafer-level packaging unit, the steps S3 to S10 adopted by the present invention during the manufacturing of the fan-out wafer-level packaging unit 1 can make the conductive lines in the RDL produce XY plane electrical extension and interconnection while maintaining or achieving a certain degree of lightness, thinness and shortness. These steps are simplified and easy to implement precisely, which is particularly beneficial to reducing the thickness of the packaging unit. Therefore, the manufacturing process of the present invention is not only relatively simple and cost-saving, but also can effectively improve the use efficiency and reliability of the fan-out wafer-level packaging unit 1.
[0047] (2) The method for forming each conductive line 50 of the fan-out wafer-level packaging unit 1 of the present invention can first fill the metal paste 50a into each first groove 31 and each second groove 41, and the thickness of the metal paste 50a is higher than the surface of the second dielectric layer 40, such as Figure 5 As shown, the metal paste 50a which is higher than the surface of the second dielectric layer 40 is then ground so that the surface of the metal paste 50a is flush with the surface of the second dielectric layer 40 to form each conductive circuit 50, as shown in FIG. Figure 6 As shown, the utility model can effectively solve the problems of the existing fan-out packaging technology that the manufacturing of each conductive circuit is prone to generate high manufacturing costs and is not conducive to environmental protection.
[0048] The above are only preferred embodiments of the present invention, which are only illustrative and not restrictive of the present invention. A person skilled in the art will understand that many changes, modifications, and even equivalent changes may be made to the present invention within the spirit and scope defined by the claims of the present invention, but all of them will fall within the scope of protection of the present invention.
Claims
1. A fan-out wafer-level packaging unit, characterized in that: Include: a carrier board; A bare die is cut from a wafer, the bare die has a first surface and an opposite second surface, the first surface of the bare die is fixed on the carrier, the second surface of the bare die has a plurality of die pads, and a vertical chip area of the second surface is defined as a chip area; A first dielectric layer is disposed on the carrier and the second surface of the bare die, the first dielectric layer having a plurality of first grooves extending in a horizontal direction; wherein each of the die pads of the bare die is exposed to the outside through each of the first grooves; A second dielectric layer is disposed on the first dielectric layer, the second dielectric layer having a plurality of second grooves extending in a horizontal direction, each of the second grooves being connected to each of the first grooves; A plurality of conducting circuits, each of which is formed by a metal paste filled in each of the first grooves and each of the second grooves, and each of the conducting circuits is electrically connected to each of the die pads of the bare die; and An outer protective layer is disposed on the second dielectric layer, the outer protective layer has a plurality of openings and at least one of the openings is located around the chip region on the second surface of the die; Each of the conductive lines is exposed to the outside through each of the openings and a welding pad is formed in each of the openings; The bare die is electrically connected to the outside via each of the die pads, each of the conducting circuits and each of the bonding pads around the chip region on the second surface of the bare die in sequence, thereby forming the fan-out wafer-level packaging unit.
2. The fan-out wafer-level packaging unit according to claim 1, characterized in that: The carrier includes a silicon carrier, a glass carrier or a ceramic carrier.
3. The fan-out wafer-level packaging unit according to claim 1, characterized in that: The metal paste includes silver paste, nano silver paste, copper paste or nano copper paste.
4. The fan-out wafer-level packaging unit according to claim 1, characterized in that: The first surface of the bare die is disposed on the carrier by using a chip bonding film.
5. The fan-out wafer level packaging unit according to claim 1, characterized in that: A solder ball is disposed on each of the second grooves, and each of the solder balls is electrically connected to each of the solder pads in each of the openings.
6. The fan-out wafer-level packaging unit according to claim 5, characterized in that: The fan-out wafer-level packaging unit is electrically connected to a printed circuit board by using each solder ball.