Electronic tag for semen cryopreservation recording

Abstract

The utility model discloses an electronic tag for semen cryopreservation recording, which belongs to the technical field of livestock breeding and comprises a power supply module, a main controller, a low-power-consumption power supply control module, a temperature sensor, an RFID (radio frequency identification) module, a memory A, a memory B, a memory C and a memory D, according to the utility model, the technical problem that the electronic tag for semen cryopreservation records realizes low power consumption design and further realizes tamper-proof design through a low-cost logic circuit is solved, temperature data during the preservation period can be accurately measured, and the storage space is expanded; the temperature data generated during the storage period can be reliably stored for a long time, the electric energy of a battery is saved to the maximum extent, the energy consumption is reduced, through the design of a low-cost logic circuit, the safety protection of the stored data is realized, the data tampering difficulty is effectively increased, and the reliability and integrity of the data are ensured.

Description

Technical Field

[0001] The utility model belongs to the technical field of animal husbandry, and particularly relates to an electronic tag used for semen freezing and storage recording. Background Art

[0002] With the development of animal husbandry and the advancement of modern veterinary technology, livestock semen cryopreservation has become an important reproductive technology. This technology is widely used in the breeding of excellent livestock, the protection of germplasm resources and genetic improvement, and is of great significance to improving the production efficiency and breed quality of animal husbandry.

[0003] The application and effectiveness of semen cryopreservation technology often rely on accurate monitoring and recording of temperature during the storage process. Traditional electronic tags used for recording have small storage capacity and poor durability, and cannot meet the needs of long-term temperature detection and data storage. What's worse, the data is easily tampered with, and the confidentiality and accuracy are poor. Utility Model Content

[0004] The utility model aims to provide an electronic tag for recording cryopreservation of semen, which solves the technical problem of realizing low power consumption design and further realizing tamper-proof design of the electronic tag for recording cryopreservation of semen through low-cost logic circuit.

[0005] In order to achieve the above purpose, the utility model adopts the following technical solutions:

[0006] An electronic tag for recording sperm cryopreservation comprises a power module, a main controller, a low-power power supply control module, a temperature sensor, an RFID module, a memory A, a memory B, a memory C and a memory D. The low-power power supply control module, the temperature sensor, the RFID module, the memory A, the memory B, the memory C and the memory D are all connected to the main controller. An output end VOUT1 of the power module directly supplies power to the main controller and the temperature sensor respectively. A power supply input end VIN of the low-power power supply control module is connected to an output end VOUT2 of the power module. An input end of the power module is connected to an external power supply POW. An output end of the low-power power supply control module comprises an output end V1, an output end V2, an output end V3, an output end V4 and an output end V5. The output ends V1, V2, V3, V4 and V5 supply power to the RFID module, the memory A, the memory B, the memory C and the memory D respectively. The low-power power supply control module is used to control the on-off of a power supply circuit from the power module to the RFID module, the memory A, the memory B, the memory C and the memory D respectively.

[0007] Preferably, the low-power power supply control module includes a 3-channel NOT gate circuit, an AND gate B, an AND gate C, an AND gate D, a switch circuit A, a switch circuit B, a switch circuit C, a switch circuit D and a switch circuit E. The 3-channel NOT gate circuit includes three NOT gates, the input end of the first NOT gate is the input end A1, and the output end is the output end Y1, the input end of the second NOT gate is the input end A2, and the output end is the output end Y2, the input end of the third NOT gate is the input end A3, and the output end is the output end Y3, and the input end A1, the input end A2 and the input end A3 of the 3-channel NOT gate circuit are respectively connected to three IO ports of the main controller, which are respectively recorded as IO port IO2, IO port IO3 and IO port IO4;

[0008] AND gate B, AND gate C and AND gate D are all 4-input AND gates, the output end Y1 of the 3-channel NOT gate circuit is respectively connected to one input end of AND gate C and one input end of AND gate D, the output end Y2 of the 3-channel NOT gate circuit is respectively connected to one input end of AND gate B and one input end of AND gate D, the output end Y3 of the 3-channel NOT gate circuit is respectively connected to one input end of AND gate B and one input end of AND gate C, IO port IO2 is connected to one input end of AND gate B, IO port IO3 is connected to one input end of AND gate C, and IO port IO4 is connected to one input end of AND gate D;

[0009] Switch circuit A, switch circuit B, switch circuit C, switch circuit D and switch circuit E are all MOS tube circuits. The gate control end of switch circuit A is connected to an IO port of the main controller, which is recorded as IO port IO1. IO port IO1 is also connected to an input end of AND gate B, an input end of AND gate C and an input end of AND gate D respectively. The input end of AND gate B is connected to the gate control end of switch circuit B, the input end of AND gate C is connected to the gate control end of switch circuit C, the input end of AND gate D is connected to the gate control end of switch circuit D, and the gate control end of switch circuit E is connected to an IO port of the main controller, which is recorded as IO port IO5. The S pole of switch circuit A, the S pole of switch circuit B, the S pole of switch circuit C, the S pole of switch circuit D and the S pole of switch circuit E are all connected to the output end VOUT2 of the power module. The D pole of switch circuit A, the D pole of switch circuit B, the D pole of switch circuit C, the D pole of switch circuit D and the D pole of switch circuit E respectively power the memory A, the memory B, the memory C, the memory D and the RFID module.

[0010] Preferably, the 3-channel NOT gate circuit includes a NOT gate IC3, AND gates B and C are both arranged in an AND gate IC4, and AND gate D is arranged in an AND gate IC5, switch circuit A includes a resistor R5 and a MOS transistor U1, switch circuit B includes a resistor R4 and a MOS transistor U2, switch circuit C includes a resistor R6 and a MOS transistor U3, switch circuit D includes a resistor R6 and a MOS transistor U3, and switch circuit E includes a resistor R7 and a MOS transistor U4;

[0011] The input terminal A1 pin of the NOT gate IC3 is connected to the IO port IO2, the output terminal Y1 pin is respectively connected to the 2C pin of the AND gate IC4 and the 1C pin of the AND gate IC5, the input terminal A2 pin is connected to the IO port IO3, the output terminal Y2 pin is respectively connected to the 1B pin of the AND gate IC4 and the 1C pin of the AND gate IC5, the input terminal A3 pin is connected to the IO port IO4, the output terminal Y3 is respectively connected to the 1C pin and the 2B pin of the AND gate IC4, the GND pin is connected to the ground wire, and the VCC pin is connected to the output terminal VOUT2 of the power module;

[0012] The 1A pin of the AND gate IC4 is connected to the IO port IO1, the 1D pin is connected to the IO port IO2, the 1Y pin is connected to the G pole of the MOS tube U2 through the resistor R4, the GND pin is connected to the ground wire, the 2Y pin is connected to the G pole of the MOS tube U3 through the resistor R6, the 2A pin is connected to the IO port IO1, the 2D pin is connected to the IO port IO3, and the VCC pin is connected to the output terminal VOUT2 of the power module;

[0013] The 1A pin of the AND gate IC5 is connected to the IO port IO1, the 1D pin is connected to the IO port IO4, the 1Y pin is connected to the G pole of the MOS tube U4 through the resistor R7, and the IO port IO1 is connected to the G pole of the MOS tube U1 through the resistor R5;

[0014] IO port IO5 is connected to the G pole of MOS tube U5 through resistor R8;

[0015] Memory A, memory B, memory C and memory D are FLASH chip IC6, FLASH chip IC7, FLASH chip IC8 and FLASH chip IC9 respectively;

[0016] The S pole of the MOS tube U1 is connected to the output terminal VOUT2 of the power module, and the D pole is connected to the VCC terminal of the FLASH chip IC6;

[0017] The S pole of MOS tube U2 is connected to the output terminal VOUT2 of the power module, and the D pole is connected to the VCC terminal of the FLASH chip IC7;

[0018] The S pole of the MOS tube U3 is connected to the output terminal VOUT2 of the power module, and the D pole is connected to the VCC terminal of the FLASH chip IC8;

[0019] The S pole of the MOS tube U4 is connected to the output terminal VOUT2 of the power module, and the D pole is connected to the VCC terminal of the FLASH chip IC9;

[0020] The S pole of the MOS tube U5 is connected to the output terminal VOUT2 of the power module, and the D pole supplies power to the RFID module.

[0021] Preferably, the power module includes a battery manager, a battery pack BAT, an interface J1 and an LDO regulator IC2, the battery pack BAT and the interface J1 are both connected to the battery manager, the interface J1 is connected to an external power supply, the input end of the LDO regulator IC2 is connected to the output end of the battery manager, the output end includes an output end VOUT1 and an output end VOUT2, and the output end VOUT1 and the output end VOUT2 both output a voltage VCC.

[0022] Preferably, the model of the main controller is STM32F103C8T6, the model of the MOS tube U1, MOS tube U2, MOS tube U3, MOS tube U4 and MOS tube U5 are all IRF9540, the model of the FLASH chip IC6, the FLASH chip IC7, the FLASH chip IC8 and the FLASH chip IC9 are all W25Q128JVSIQ, the model of the temperature sensor is DS18B20, the model of the RFID module is SL3S1203, the model of the NOT gate IC3 is SN74LVC04A, and the model of the AND gate IC4 and the AND gate IC5 are both SN74LVC21. Preferably, the battery manager includes a battery management chip BQ24032 and its peripheral circuits, and the model of the LDO regulator IC2 is LM1117-3.3.

[0023] The electronic tag for semen cryopreservation record described in the utility model solves the technical problem of realizing low-power design and further realizing tamper-proof design of the electronic tag for semen cryopreservation record through low-cost logic circuit. The utility model can accurately measure the temperature data during the storage period, and the expanded storage space can reliably store the temperature data generated during the storage period for a long time. The low-power logic circuit design is adopted, and power is not supplied to all memories at the same time, which saves battery power to the maximum extent, effectively prolongs the service life of the electronic tag, reduces energy consumption, and is conducive to the continuous monitoring of the long-term semen storage process. Through the design of low-cost logic circuit, the security protection of the stored data is realized, the difficulty of data tampering is effectively increased, and the reliability and integrity of the data are guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic block diagram of the utility model;

[0025] Figure 2 It is a schematic block diagram of the low-power supply control module of the utility model;

[0026] Figure 3 This is a circuit diagram of a low-power power supply control module of the utility model;

[0027] Figure 4It is a circuit diagram of the memory A, the memory B, the memory C and the memory D of the utility model. DETAILED DESCRIPTION

[0028] like Figure 1-4 An electronic tag for semen cryopreservation record shown in the figure includes a power module, a main controller, a low-power power supply control module, a temperature sensor, an RFID module, a memory A, a memory B, a memory C and a memory D. The low-power power supply control module, the temperature sensor, the RFID module, the memory A, the memory B, the memory C and the memory D are all connected to the main controller. The output end VOUT1 of the power module directly powers the main controller and the temperature sensor respectively. The power supply input end VIN of the low-power power supply control module is connected to the output end VOUT2 of the power module. The input end of the power module is connected to an external power supply POW. The output end of the low-power power supply control module includes an output end V1, an output end V2, an output end V3, an output end V4 and an output end V5. The output ends V1, V2, V3, V4 and V5 supply power to the RFID module, the memory A, the memory B, the memory C and the memory D respectively. The low-power power supply control module is used to control the on-off of the power supply circuit from the power module to the RFID module, the memory A, the memory B, the memory C and the memory D respectively.

[0029] The low-power power supply control module includes a 3-channel NOT gate circuit, an AND gate B, an AND gate C, an AND gate D, a switch circuit A, a switch circuit B, a switch circuit C, a switch circuit D and a switch circuit E. The 3-channel NOT gate circuit includes three NOT gates. The input end of the first NOT gate is the input end A1, and the output end is the output end Y1. The input end of the second NOT gate is the input end A2, and the output end is the output end Y2. The input end of the third NOT gate is the input end A3, and the output end is the output end Y3. The input end A1, the input end A2 and the input end A3 of the 3-channel NOT gate circuit are respectively connected to three IO ports of the main controller, which are respectively recorded as IO port IO2, IO port IO3 and IO port IO4;

[0030] AND gate B, AND gate C and AND gate D are all 4-input AND gates, the output end Y1 of the 3-channel NOT gate circuit is respectively connected to one input end of AND gate C and one input end of AND gate D, the output end Y2 of the 3-channel NOT gate circuit is respectively connected to one input end of AND gate B and one input end of AND gate D, the output end Y3 of the 3-channel NOT gate circuit is respectively connected to one input end of AND gate B and one input end of AND gate C, IO port IO2 is connected to one input end of AND gate B, IO port IO3 is connected to one input end of AND gate C, and IO port IO4 is connected to one input end of AND gate D;

[0031] The 3-channel NOT gate circuit includes a NOT gate IC3, AND gates B and C are both arranged in an AND gate IC4, and an AND gate D is arranged in an AND gate IC5, a switch circuit A includes a resistor R5 and a MOS tube U1, a switch circuit B includes a resistor R4 and a MOS tube U2, a switch circuit C includes a resistor R6 and a MOS tube U3, a switch circuit D includes a resistor R6 and a MOS tube U3, and a switch circuit E includes a resistor R7 and a MOS tube U4;

[0032] The input terminal A1 pin of the NOT gate IC3 is connected to the IO port IO2, the output terminal Y1 pin is respectively connected to the 2C pin of the AND gate IC4 and the 1C pin of the AND gate IC5, the input terminal A2 pin is connected to the IO port IO3, the output terminal Y2 pin is respectively connected to the 1B pin of the AND gate IC4 and the 1C pin of the AND gate IC5, the input terminal A3 pin is connected to the IO port IO4, the output terminal Y3 is respectively connected to the 1C pin and the 2B pin of the AND gate IC4, the GND pin is connected to the ground wire, and the VCC pin is connected to the output terminal VOUT2 of the power module;

[0033] Switch circuit A, switch circuit B, switch circuit C, switch circuit D and switch circuit E are all MOS tube circuits. The gate control end of switch circuit A is connected to an IO port of the main controller, which is recorded as IO port IO1. IO port IO1 is also connected to an input end of AND gate B, an input end of AND gate C and an input end of AND gate D respectively. The input end of AND gate B is connected to the gate control end of switch circuit B, the input end of AND gate C is connected to the gate control end of switch circuit C, the input end of AND gate D is connected to the gate control end of switch circuit D, and the gate control end of switch circuit E is connected to an IO port of the main controller, which is recorded as IO port IO5. The S pole of switch circuit A, the S pole of switch circuit B, the S pole of switch circuit C, the S pole of switch circuit D and the S pole of switch circuit E are all connected to the output end VOUT2 of the power module. The D pole of switch circuit A, the D pole of switch circuit B, the D pole of switch circuit C, the D pole of switch circuit D and the D pole of switch circuit E respectively power the memory A, the memory B, the memory C, the memory D and the RFID module.

[0034] The 1A pin of the AND gate IC4 is connected to the IO port IO1, the 1D pin is connected to the IO port IO2, the 1Y pin is connected to the G pole of the MOS tube U2 through the resistor R4, the GND pin is connected to the ground wire, the 2Y pin is connected to the G pole of the MOS tube U3 through the resistor R6, the 2A pin is connected to the IO port IO1, the 2D pin is connected to the IO port IO3, and the VCC pin is connected to the output terminal VOUT2 of the power module;

[0035] The 1A pin of the AND gate IC5 is connected to the IO port IO1, the 1D pin is connected to the IO port IO4, the 1Y pin is connected to the G pole of the MOS tube U4 through the resistor R7, and the IO port IO1 is connected to the G pole of the MOS tube U1 through the resistor R5;

[0036] IO port IO5 is connected to the G pole of MOS tube U5 through resistor R8;

[0037] Memory A, memory B, memory C and memory D are FLASH chip IC6, FLASH chip IC7, FLASH chip IC8 and FLASH chip IC9 respectively;

[0038] The S pole of the MOS tube U1 is connected to the output terminal VOUT2 of the power module, and the D pole is connected to the VCC terminal of the FLASH chip IC6;

[0039] The S pole of MOS tube U2 is connected to the output terminal VOUT2 of the power module, and the D pole is connected to the VCC terminal of the FLASH chip IC7;

[0040] The S pole of the MOS tube U3 is connected to the output terminal VOUT2 of the power module, and the D pole is connected to the VCC terminal of the FLASH chip IC8;

[0041] The S pole of the MOS tube U4 is connected to the output terminal VOUT2 of the power module, and the D pole is connected to the VCC terminal of the FLASH chip IC9;

[0042] The S pole of the MOS tube U5 is connected to the output terminal VOUT2 of the power module, and the D pole supplies power to the RFID module.

[0043] The low-power power supply control module of the utility model can realize independent power supply to the memory through a low-cost circuit. When in specific use, the user can use the memory A as the main memory to store the storage address of each data and view and modify the password and other data. The memory B, the memory C and the memory D are the memories for actually storing the data. Through the logic control of the low-power power supply control module of the utility model, only the memory A and the other memory can be powered at the same time, that is, the memory B, the memory C and the memory D will not be powered at the same time, and the memory B, the memory C and the memory D can only be powered when the memory A is powered. This can save the consumption of battery power and increase the difficulty of tampering.

[0044] The power module includes a battery manager, a battery pack BAT, an interface J1 and an LDO regulator IC2. The battery pack BAT and the interface J1 are both connected to the battery manager. The interface J1 is connected to an external power supply. The input end of the LDO regulator IC2 is connected to the output end of the battery manager. The output end includes an output end VOUT1 and an output end VOUT2. Both the output end VOUT1 and the output end VOUT2 output a voltage VCC.

[0045] The battery manager includes a battery management chip BQ24032 and its peripheral circuits, and the model of the LDO regulator IC2 is LM1117-3.3.

[0046] The model of the main controller is STM32F103C8T6, the model of the MOS tube U1, MOS tube U2, MOS tube U3, MOS tube U4 and MOS tube U5 are all IRF9540, the model of the FLASH chip IC6, the FLASH chip IC7, the FLASH chip IC8 and the FLASH chip IC9 are all W25Q128JVSIQ, the model of the temperature sensor is DS18B20, the model of the RFID module is SL3S1203, the model of the NOT gate IC3 is SN74LVC04A, and the model of the AND gate IC4 and the AND gate IC5 are both SN74LVC21.

[0047] The electronic tag for semen cryopreservation record described in the utility model solves the technical problem of realizing low-power design and further realizing tamper-proof design of the electronic tag for semen cryopreservation record through low-cost logic circuit. The utility model can accurately measure the temperature data during the storage period, and the expanded storage space can reliably store the temperature data generated during the storage period for a long time. The low-power logic circuit design is adopted, and power is not supplied to all memories at the same time, which saves battery power to the maximum extent, effectively prolongs the service life of the electronic tag, reduces energy consumption, and is conducive to the continuous monitoring of the long-term semen storage process. Through the design of low-cost logic circuit, the security protection of the stored data is realized, the difficulty of data tampering is effectively increased, and the reliability and integrity of the data are guaranteed.

Claims

1. An electronic tag for recording semen cryopreservation, characterized in that: It includes a power supply module, a main controller, a low-power supply control module, a temperature sensor, an RFID module, a memory A, a memory B, a memory C and a memory D. The low-power supply control module, the temperature sensor, the RFID module, the memory A, the memory B, the memory C and the memory D are all connected to the main controller. The output end VOUT1 of the power supply module directly supplies power to the main controller and the temperature sensor respectively. The power supply input end VIN of the low-power supply control module is connected to the output end VOUT2 of the power supply module. The input end of the power supply module is connected to an external power supply POW. The output end of the low-power supply control module includes an output end V1, an output end V2, an output end V3, an output end V4 and an output end V5. The output ends V1, V2, V3, V4 and V5 supply power to the RFID module, the memory A, the memory B, the memory C and the memory D respectively. The low-power supply control module is used to control the on / off of the power supply circuits from the power supply module to the RFID module, the memory A, the memory B, the memory C and the memory D respectively.

2. An electronic tag for recording semen cryopreservation as claimed in claim 1, characterized in that: The low-power power supply control module includes a 3-channel NOT gate circuit, an AND gate B, an AND gate C, an AND gate D, a switch circuit A, a switch circuit B, a switch circuit C, a switch circuit D and a switch circuit E. The 3-channel NOT gate circuit includes three NOT gates. The input end of the first NOT gate is the input end A1, and the output end is the output end Y1. The input end of the second NOT gate is the input end A2, and the output end is the output end Y2. The input end of the third NOT gate is the input end A3, and the output end is the output end Y3. The input end A1, the input end A2 and the input end A3 of the 3-channel NOT gate circuit are respectively connected to three IO ports of the main controller, which are respectively recorded as IO port IO2, IO port IO3 and IO port IO4; AND gate B, AND gate C and AND gate D are all 4-input AND gates, the output end Y1 of the 3-channel NOT gate circuit is respectively connected to one input end of AND gate C and one input end of AND gate D, the output end Y2 of the 3-channel NOT gate circuit is respectively connected to one input end of AND gate B and one input end of AND gate D, the output end Y3 of the 3-channel NOT gate circuit is respectively connected to one input end of AND gate B and one input end of AND gate C, IO port IO2 is connected to one input end of AND gate B, IO port IO3 is connected to one input end of AND gate C, and IO port IO4 is connected to one input end of AND gate D; Switch circuit A, switch circuit B, switch circuit C, switch circuit D and switch circuit E are all MOS tube circuits. The gate control end of switch circuit A is connected to an IO port of the main controller, which is recorded as IO port IO1. IO port IO1 is also connected to an input end of AND gate B, an input end of AND gate C and an input end of AND gate D respectively. The input end of AND gate B is connected to the gate control end of switch circuit B, the input end of AND gate C is connected to the gate control end of switch circuit C, the input end of AND gate D is connected to the gate control end of switch circuit D, and the gate control end of switch circuit E is connected to an IO port of the main controller, which is recorded as IO port IO5. The S pole of switch circuit A, the S pole of switch circuit B, the S pole of switch circuit C, the S pole of switch circuit D and the S pole of switch circuit E are all connected to the output end VOUT2 of the power module. The D pole of switch circuit A, the D pole of switch circuit B, the D pole of switch circuit C, the D pole of switch circuit D and the D pole of switch circuit E respectively power the memory A, the memory B, the memory C, the memory D and the RFID module.

3. An electronic tag for recording semen cryopreservation as claimed in claim 2, characterized in that: The 3-channel NOT gate circuit includes a NOT gate IC3, AND gates B and C are both arranged in an AND gate IC4, and an AND gate D is arranged in an AND gate IC5, a switch circuit A includes a resistor R5 and a MOS tube U1, a switch circuit B includes a resistor R4 and a MOS tube U2, a switch circuit C includes a resistor R6 and a MOS tube U3, a switch circuit D includes a resistor R6 and a MOS tube U3, and a switch circuit E includes a resistor R7 and a MOS tube U4; The input terminal A1 pin of the NOT gate IC3 is connected to the IO port IO2, the output terminal Y1 pin is respectively connected to the 2C pin of the AND gate IC4 and the 1C pin of the AND gate IC5, the input terminal A2 pin is connected to the IO port IO3, the output terminal Y2 pin is respectively connected to the 1B pin of the AND gate IC4 and the 1C pin of the AND gate IC5, the input terminal A3 pin is connected to the IO port IO4, the output terminal Y3 is respectively connected to the 1C pin and the 2B pin of the AND gate IC4, the GND pin is connected to the ground wire, and the VCC pin is connected to the output terminal VOUT2 of the power module; The 1A pin of the AND gate IC4 is connected to the IO port IO1, the 1D pin is connected to the IO port IO2, the 1Y pin is connected to the G pole of the MOS tube U2 through the resistor R4, the GND pin is connected to the ground wire, the 2Y pin is connected to the G pole of the MOS tube U3 through the resistor R6, the 2A pin is connected to the IO port IO1, the 2D pin is connected to the IO port IO3, and the VCC pin is connected to the output terminal VOUT2 of the power module; The 1A pin of the AND gate IC5 is connected to the IO port IO1, the 1D pin is connected to the IO port IO4, the 1Y pin is connected to the G pole of the MOS tube U4 through the resistor R7, and the IO port IO1 is connected to the G pole of the MOS tube U1 through the resistor R5; IO port IO5 is connected to the G pole of MOS tube U5 through resistor R8; Memory A, memory B, memory C and memory D are FLASH chip IC6, FLASH chip IC7, FLASH chip IC8 and FLASH chip IC9 respectively; The S pole of the MOS tube U1 is connected to the output terminal VOUT2 of the power module, and the D pole is connected to the VCC terminal of the FLASH chip IC6; The S pole of MOS tube U2 is connected to the output terminal VOUT2 of the power module, and the D pole is connected to the VCC terminal of the FLASH chip IC7; The S pole of the MOS tube U3 is connected to the output terminal VOUT2 of the power module, and the D pole is connected to the VCC terminal of the FLASH chip IC8; The S pole of the MOS tube U4 is connected to the output terminal VOUT2 of the power module, and the D pole is connected to the VCC terminal of the FLASH chip IC9; The S pole of the MOS tube U5 is connected to the output terminal VOUT2 of the power module, and the D pole supplies power to the RFID module.

4. An electronic tag for recording semen cryopreservation as claimed in claim 2, characterized in that: The power module includes a battery manager, a battery pack BAT, an interface J1 and an LDO regulator IC2. The battery pack BAT and the interface J1 are both connected to the battery manager. The interface J1 is connected to an external power supply. The input end of the LDO regulator IC2 is connected to the output end of the battery manager. The output end includes an output end VOUT1 and an output end VOUT2. Both the output end VOUT1 and the output end VOUT2 output a voltage VCC.

5. The electronic tag for recording semen cryopreservation according to claim 3, characterized in that: The model of the main controller is STM32F103C8T6, the model of the MOS tube U1, MOS tube U2, MOS tube U3, MOS tube U4 and MOS tube U5 are all IRF9540, the model of the FLASH chip IC6, the FLASH chip IC7, the FLASH chip IC8 and the FLASH chip IC9 are all W25Q128JVSIQ, the model of the temperature sensor is DS18B20, the model of the RFID module is SL3S1203, the model of the NOT gate IC3 is SN74LVC04A, and the model of the AND gate IC4 and the AND gate IC5 are both SN74LVC21.

6. An electronic tag for recording sperm cryopreservation as claimed in claim 4, characterized in that: The battery manager includes a battery management chip BQ24032 and its peripheral circuits, and the model of the LDO regulator IC2 is LM1117-3.3.

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