Electrical test structure

Abstract

The utility model provides an electrical property test structure, comprising a plurality of circuits to be tested, the plurality of circuits to be tested are arranged in sequence according to a test purpose, and at least two circuits to be tested have different at least one parameter; and the plurality of bonding pads, except the bonding pads at the starting end and the terminal end, are only connected with one to-be-tested circuit, and the two ends of any of the rest bonding pads are connected with the to-be-tested circuit. The to-be-tested circuits are sequentially arranged according to the test purpose, the test sequence and accuracy can be guaranteed, at least one parameter between at least two to-be-tested circuits is different, other parameters are kept unchanged, only the to-be-tested variables are changed, the influence of other factors on the test result can be eliminated, and the test accuracy is improved. Therefore, the change condition of the to-be-tested parameters can be measured more accurately. The circuit testing device is simple and efficient in design, can effectively carry out circuit testing, facilitates comparison of circuit performance with different parameters, and has important application value.

Description

Technical Field

[0001] The utility model belongs to the field of semiconductor manufacturing, and in particular relates to an electrical testing structure. Background Art

[0002] In general chip manufacturing processes, the layers that need to monitor the disconnection of the connection include the active area, gate and metal layer. The active area or gate is generally divided into N-type and P-type. The total number of metal layers is about 5 to 10 layers, and the total number of layers that need to be tested is 9 to 14 layers. Assuming that each layer needs to design 4 metal wire structures of different widths, the total number of pins required is about 72 to 112. Traditionally, these pins are usually implemented through pads, and 72 to 112 pads need to be designed to meet the connection and testing requirements. For complex chip designs, the number of pins that need to be connected may be more, and the traditional pin layout has certain limitations, which will lead to a waste of the use area of ​​the test chip, limiting the overall performance and function of the test chip.

[0003] According to the traditional testing method, when analyzing and judging whether multiple circuits to be tested have a short circuit, each circuit to be tested needs to be connected to two pads and tested separately. If n circuits to be tested are tested, 2n pads need to be connected. Assuming that the test time of the tester is the same (t) for each test, the test time for n circuits to be tested is nt. Figure 1 , Figure 2 As shown, to test 4 circuits to be tested, 8 pads need to be connected, and each circuit to be tested needs to be tested separately, and the total test time is 4t. Since each circuit to be tested needs to be tested separately, the test time increases linearly. For a large number of circuits to be tested, the test time will increase greatly, affecting efficiency. Utility Model Content

[0004] In order to solve all or part of the problems of the prior art, the utility model provides an electrical test structure, which can reduce test time and cost and improve the area utilization of the test chip by improving the arrangement and connection method of the test circuit and the pad.

[0005] In order to achieve the above purpose, the utility model provides the following technical solutions:

[0006] An electrical test structure, comprising: a plurality of circuits to be tested, the plurality of circuits to be tested are arranged in sequence according to the test purpose, at least one parameter of at least two of the circuits to be tested is different; a plurality of pads, except for the pads at the starting end and the terminal end which are only connected to one of the circuits to be tested, both ends of any of the remaining pads are connected to the circuit to be tested; that is, the two ends of the plurality of circuits to be tested are respectively connected to different pads, and two adjacent circuits to be tested share one pad. The beneficial effect of this technical solution is that by connecting the plurality of circuits to be tested in series through a plurality of pads, the number of connection lines and the area occupied by the pads can be reduced, thereby saving the layout space of the chip and improving the area utilization of the chip.

[0007] The circuits to be tested are arranged in a manner of arranging from small to large or from large to small according to the line width of the circuits to be tested. Narrower line widths may be more prone to faults such as open circuits, while wider line widths are relatively more reliable and less likely to fail. Sorting by line width can optimize the test process, and testing test circuits with smaller line widths can quickly screen out reliable circuits, reducing unnecessary test time and resource investment.

[0008] Only one circuit to be tested is arranged between any two adjacent pads, forming a simple and effective series test structure, which can reduce the number of connection lines and the area occupied by pads, thereby saving the layout space of the chip and improving the area utilization of the chip.

[0009] In some specific implementations, all the circuits to be tested are circuits of the same layer, and their line widths are different. The test structure can be used to test circuits to be tested in the same layer.

[0010] All the circuits to be tested have the same circuit structure. Since the circuit structure is the same, it is easier to compare and analyze circuits with different line widths, which helps to find the impact of line width on circuit performance and characteristics, thereby guiding the optimization design and manufacturing process.

[0011] In some other specific embodiments, the circuit to be tested is an interconnected two-layer or multi-layer structure. The test structure can also be used to test the circuit to be tested across two or more layers.

[0012] The layers of the circuits to be tested are connected by through holes, and the number and size of through holes of each circuit to be tested are the same, which helps to maintain consistency and reduce the number of variables, so as to better observe the impact of the variables to be studied (such as line width) on circuit performance.

[0013] In any of the circuits to be tested, only one layer has different line widths, and the line widths of the other layers remain the same. Under the premise of controlling variables, only one layer has different line widths, and the line widths of the other layers remain the same. Sorting by line width can detect possible circuit breaks more quickly without being interfered by other factors.

[0014] The layers of the circuit to be tested include at least one of a metal layer, an active layer, and a polysilicon layer. For the active region layer or the gate layer, the N-type and P-type have no difference in the design of the test structure.

[0015] When the layer of the circuit to be tested is a metal layer, an active layer or a polysilicon layer, it is arranged according to the width of the metal line, the width of the active area pattern or the width of the gate pattern.

[0016] Compared with the prior art, the beneficial effects of the utility model mainly include: 1) connecting multiple circuits to be tested in series through multiple pads can reduce the number of connection lines and the area occupied by the pads, thereby saving the layout space of the chip and improving the area utilization of the chip. 2) The circuits to be tested are arranged in order from small to large or from large to small according to the line width. The circuits to be tested with low line width are more likely to have a circuit break. Electrical detection of the pads connected to them in the test structure in order of line width from small to large can quickly diagnose the circuit break, effectively saving test time. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A schematic diagram of the electrical test structure in the background technology

[0019] Figure 2 A schematic diagram of the test flow of the electrical test structure in the background technology

[0020] Figure 3 It is a structural schematic diagram of the electrical testing structure provided in Example 1 of the utility model.

[0021] Figure 4 It is a structural schematic diagram of the electrical testing structure provided in Example 2 of the utility model.

[0022] Figure 5 This is a schematic diagram of the structure of the circuit to be tested provided in Example 2 of the utility model.

[0023] Figure 6The figure is a schematic diagram of the test flow of the electrical test structure provided by the utility model. DETAILED DESCRIPTION

[0024] The technical solutions in the specific embodiments of the utility model are described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of them. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0025] Example 1

[0026] See also Figure 3 , Figure 6 , an electrical test structure provided in Embodiment 1 of the present utility model comprises:

[0027] Multiple circuits to be tested, multiple circuits to be tested are arranged in sequence according to the test purpose, and at least one parameter of at least two circuits to be tested is different. In this embodiment, all circuits to be tested are circuits of the same layer, and the circuit structures of all circuits to be tested are the same, and their line widths are different. The arrangement of the circuits to be tested is arranged from small to large or from large to small according to the line width of the circuits to be tested. In the same layer of circuits, the circuit structures of all circuits to be tested are the same, so that the influence of other variables can be controlled; in this embodiment, the same circuit structure refers to only the metal wire structure, without other circuit devices. In other embodiments, the same circuit structure can also be provided with the same circuit devices, which is not specifically limited in this patent. By keeping other parameters unchanged and only changing the variables to be tested (line width), the influence of other factors on the test results can be eliminated, thereby more accurately measuring the changes in the parameters to be tested. Putting the circuit with a narrower line width in front for testing can quickly screen out reliable circuits. Circuits with narrower line widths may have the risk of faults such as open circuits. Therefore, by testing the circuit with a narrower line width first, problems can be discovered and repaired as early as possible, thereby reducing the time and resource investment for subsequent testing.

[0028] Multiple pads, except for the pads at the starting end and the terminal end which are only connected to one circuit to be tested, both ends of any other pads are connected to the circuit to be tested, and only one circuit to be tested is arranged between any two adjacent pads; that is, the two ends of the multiple circuits to be tested are respectively connected to different pads, and two adjacent circuits to be tested share one pad. By connecting multiple circuits to be tested in series through multiple pads, the number of connection lines and the area occupied by pads can be reduced, thereby saving the layout space of the chip, improving the area utilization of the chip, and thus improving the production capacity of the manufacturing plant. When a fault occurs, by checking the connection between the pad and the circuit to be tested, the specific location of the fault can be quickly located, and corresponding measures can be taken to repair it.

[0029] The test structure of the utility model is used to test whether the connection is open circuit, and then to evaluate the window range of the manufacturing process. It is generally not suitable for multi-pin (pin) structure. The circuit to be tested can be a metal layer, an active layer or a polysilicon layer. When the circuit to be tested is a metal layer, an active layer or a polysilicon layer, it is arranged according to the width of the metal line, the width of the active area pattern or the width of the gate pattern. For the active area layer or the gate layer, the N-type and P-type (doping type) are divided into no difference for the design of the test structure of the utility model. In the same test structure, there is no limit on the line length of the circuit to be tested with different line widths. Generally speaking, the more samples, the better, that is, the line length is not required to be the same.

[0030] By adopting an electrical test structure of the utility model, only n+1 pads are needed to test n circuits to be tested. Compared with the test structure in the background technology, nearly half of the test pads can be saved and the area utilization rate of the test chip is nearly doubled.

[0031] The test method of the electrical test structure of the utility model is: n circuits to be tested are arranged in ascending order according to line width, and the specific method of using the test structure provided by the utility model to test the circuit is: the n+1th pad is connected to a high level Vf, and the other pads are all connected to a low level 0, and the current value of the pad connected to the low level 0 is tested in sequence according to the following steps to perform an electrical test. (In this embodiment, the criterion for determining whether the test structure has failed is: if the total resistance of the circuit to be tested is ≤10 times the estimated resistance value, it is determined that the test structure has not failed; if the total resistance of the circuit to be tested is >10 times the estimated resistance value, it is determined that the test structure has failed. The estimated resistance value of each circuit to be tested can be calculated based on "total number of blocks in the structure * block resistance". This test method is based on a known number of blocks. The number of blocks can generally be obtained through the line length / line width of the structure, and the block resistance generally has a reference value. Preferably, in other implementations, other determination criteria can be used according to specific circumstances.)

[0032] Step (1): Test the current value I1 of the first pad and calculate the total resistance R1=Vf / I1 of n circuits to be tested;

[0033] If the total resistance R1≤10R n预估 (R n预估 is the estimated resistance value of the n circuits to be tested), it is determined that no short circuit occurs, the total test time is t, and the test is ended; through one test, the short circuit test of the n circuits to be tested in this embodiment is completed.

[0034] If the total resistance R1>10R n预估 (R n预估is the estimated resistance value of n circuits to be tested), it is determined that a circuit is broken, and it is necessary to further determine the circuit to be tested where the circuit is broken, and the test time t has been used; continue to execute step (2);

[0035] Step (2): Test the current value I2 of the second pad and calculate the total resistance R2 = Vf / I2 of the n-1 circuits to be tested; if the total resistance R2 ≤ 10R n-1预估 (R n-1预估 is the estimated resistance value of n-1 circuits to be tested), it is determined that no short circuit occurs. At this time, it can be determined that the first circuit to be tested has a short circuit, and the following n-1 circuits to be tested have no short circuits. The total test time is 2t, and the test is ended; through the secondary test, the short circuit test of the n circuits to be tested in this embodiment is completed.

[0036] If the total resistance R2>10R n-1预估 (R n-1预估 is the estimated resistance value of n-1 circuits to be tested), it is determined that a circuit is broken, and further determination is required on the circuit to be tested where the circuit is broken. The test time used is 2t; continue to execute step (3);

[0037] Step (3): Test the current value I3 of the third pad and calculate the total resistance R3 = Vf / I3 of the n-2 circuits to be tested; if the total resistance R3 ≤ 10R n-2预估 (R n-2预估 is the estimated resistance value of n-2 circuits to be tested), it is determined that no short circuit occurs. At this time, it can be determined that short circuits occur in the first two circuits to be tested, and no short circuits occur in the following n-2 circuits to be tested. The total test time is 3t, and the test is ended. After three tests, the short circuit test of the n circuits to be tested in this embodiment is completed.

[0038] If the total resistance R3>10R n-2预估 (R n-2预估 is the estimated resistance value of n-2 circuits to be tested), it is determined that a circuit is broken, and it is necessary to further determine the circuit to be tested where the circuit is broken. The test time 3t has been used; the current values ​​in the subsequent circuits to be tested are tested one by one in the same manner as steps (1), (2), and (3), and then the total resistance of the remaining circuits to be tested is calculated, and the determination is made based on the comparison result of the total resistance with the estimated resistance value of the circuit to be tested, until the circuit to be tested where the circuit is broken is determined or it is confirmed that no circuit is broken. The maximum test time required is nt, that is, it is possible to execute to step (n).

[0039] Step (n): Test the current value I of the nth pad n , calculate the total resistance R of the nth circuit to be tested n =Vf / I n ;

[0040] If the total resistance R n ≤10R (R is the estimated resistance value of a circuit to be tested), it is determined that no short circuit occurs. At this time, it can be determined that the first n-1 circuits to be tested have short circuits, and the nth circuit to be tested has no short circuit. The total test time is nt; the test ends.

[0041] If the total resistance R n >10R (R is the estimated resistance of a circuit to be tested), it is determined that the nth circuit to be tested has a short circuit, the total test time is nt, and the test is ended.

[0042] The lines are sorted in order from small to large according to the line width. The principle of sorting is that the line width can generally represent the probability of structural failure. The wider the structure, the less likely it is to fail. It can also be said that they are arranged according to the probability of short-circuit failure. Therefore, by testing the test circuit with a smaller line width, it is possible to determine whether the process level is healthy. Considering that the probability of a short circuit occurring in a normal chip process is a small probability time, for most cases, using this test method to test once (i.e., current detection of all test circuits in series) can determine whether the process level is healthy. Compared with the test method in the background technology, this test method can save almost n times the test time (related to the number of circuits to be tested).

[0043] Furthermore, if the line width of the circuit to be tested is arranged from large to small, the test method is adjusted accordingly. The first pad is connected to the high level Vf, and the other pads are connected to the low level 0. Starting from the n+1th pad, the current value of the pad connected to the low level 0 is tested in reverse order according to the above steps to perform electrical testing.

[0044] The following combination Figure 3 The specific test structure in the utility model is explained in detail. Figure 3 The test structure in the example includes 4 circuits to be tested (split1-4) and 5 pads. The line widths of the 4 circuits to be tested are arranged from small to large: W1=0.1, W2=0.15, W3=0.3, W4=0.4. The probability of a circuit break is: split1>split2>split3>split4. The specific test method is: the 5th pad is connected to a high level Vf, and the other pads are connected to a low level 0, such as Figure 6 As shown, the current value of the pad connected to the low level 0 is tested in sequence according to the above steps. The shortest way is to complete the open circuit test of the four circuits to be tested in this embodiment by only one test.

[0045] When more than two circuits to be tested are found to be short-circuited, the position of the connected pads can be changed to perform current testing on the short-circuited circuits to be tested, which can effectively save testing time. If it is necessary to accurately determine the circuit to be tested that is short-circuited, the pads at both ends of the circuit to be tested can also be connected separately for testing, and this patent does not make specific restrictions.

[0046] Compared with the testing method in the background art, the testing method can save up to 4 times of testing time.

[0047] Example 2

[0048] See also Figure 4 , Figure 5 , Figure 6 The electrical test structure provided in Example 2 of the utility model is different from that in Example 1 in that, in this embodiment, the circuit to be tested is an interconnected two-layer or multi-layer structure.

[0049] The layers of the circuits to be tested are connected by vias, and the number and size of vias in each circuit to be tested are the same, which helps to maintain consistency and reduce the number of variables. If only one layer of the line width of any circuit to be tested is different, and the line widths of the remaining layers are kept the same, it will help to test under the premise of controlling the variables. Such a design can ensure that only one variable changes, that is, the difference in line width, while other factors remain the same (errors caused by manufacturing processes, etc. are also the same). Sorting by line width can detect possible circuit breaks more quickly without being interfered by other factors.

[0050] In this embodiment, 4 circuits to be tested are specifically tested, which requires 5 pads. The line widths of the circuits to be tested are arranged from small to large. The testing method is consistent with the method provided in Embodiment 1.

[0051] It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made to the utility model without departing from the principle of the utility model, and these improvements and modifications also fall within the scope of protection of the claims of the utility model.

Claims

1. An electrical test structure, characterized in that: include: A plurality of circuits to be tested, wherein the plurality of circuits to be tested are arranged in sequence according to a test purpose, and at least one parameter of at least two of the circuits to be tested is different; Multiple pads, except for the pads at the starting end and the terminal end which are only connected to one of the circuits to be tested, both ends of any of the other pads are connected to the circuit to be tested; that is, the two ends of the multiple circuits to be tested are respectively connected to different pads, and two adjacent circuits to be tested share one pad.

2. An electrical test structure according to claim 1, characterized in that: The circuits to be tested are arranged in a manner of arranging from small to large or from large to small according to the line width of the circuits to be tested.

3. An electrical test structure according to claim 1 or 2, characterized in that: Only one circuit to be tested is arranged between any two adjacent pads.

4. An electrical test structure according to claim 3, characterized in that: All the circuits to be tested are circuits of the same layer, and their line widths are different.

5. An electrical test structure according to claim 4, characterized in that: All the circuits to be tested have the same circuit structure.

6. The electrical test structure according to claim 3, characterized in that: The circuit to be tested is an interconnected two-layer or multi-layer structure.

7. An electrical test structure according to claim 6, characterized in that: The layers of the circuits to be tested are connected via through holes, and the number and size of the through holes of each circuit to be tested are the same.

8. An electrical test structure according to claim 7, characterized in that: In any of the circuits to be tested, only one layer has a different line width, and the line widths of the remaining layers remain the same.

9. The electrical test structure according to claim 1, characterized in that: The layer of the circuit to be tested includes at least one of a metal layer, an active layer, and a polysilicon layer.

10. An electrical test structure according to claim 9, characterized in that: When the layer of the circuit to be tested is a metal layer, an active layer or a polysilicon layer, it is arranged according to the width of the metal line, the width of the active area pattern or the width of the gate pattern respectively.

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