Semiconductor device and silicon carbide device integrated with super barrier rectifier

Abstract

The utility model provides a semiconductor device and a silicon carbide device integrated with a super barrier rectifier. The semiconductor device includes a substrate; the first gate dielectric layers and the first gate conducting layers are located on the substrate and used for forming a plurality of transistor devices, the first gate conducting layers extend in the first direction, the first gate conducting layers are sequentially arranged in the second direction, and the ends of the first gate conducting layers are electrically connected with one another; wherein the end parts of the partially adjacent first gate conductive layers are connected with each other to define a rectification region; the second gate dielectric layer and the second gate conducting layer are located on the substrate and used for forming the super barrier rectifier, the second gate dielectric layer and the second gate conducting layer are sequentially stacked in the rectification area, the thickness of the second gate dielectric layer is smaller than that of the first gate dielectric layer, and the length of the second gate conducting layer is smaller than that of the first gate conducting layer. According to the utility model, the circuit scale is reduced and the chip manufacturing cost is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a semiconductor device and a silicon carbide device integrated with a super barrier rectifier. Background Art

[0002] In the prior art, commonly used rectifiers generally include Schottky barrier rectifiers and super barrier rectifiers (SBR). Among them, the super barrier rectifier SBR can provide a low barrier environment for the majority carriers in the MOS channel, which can achieve lower reverse voltage and lower reverse leakage current, and because the super barrier rectifier SBR has advantages such as high stability and reliability, it is widely used in semiconductor devices.

[0003] For example, in high-voltage and high-current working environments, the field effect transistors used are usually required to have high withstand voltage characteristics. At this time, silicon carbide-based field effect transistors can be used instead of silicon-based field effect transistors. Specifically, silicon carbide (SiC) is a wide-bandgap semiconductor material with a higher bandgap than silicon (Si). The breakdown electric field of silicon carbide is higher than the breakdown electric field of silicon. Compared with silicon, silicon carbide can maintain stability even under high temperature conditions. Therefore, compared with silicon-based field effect transistors, silicon carbide-based field effect transistors have high breakdown voltage and excellent heat dissipation. For silicon carbide devices, in order to achieve their rapid shutdown and increase the reverse recovery speed, the traditional method usually requires a separate Schottky barrier diode chip (SiC SBD chip) for freewheeling to be made, and the silicon carbide device is connected in parallel with the Schottky barrier diode chip (SiC SBD chip) for freewheeling through a circuit.

[0004] However, in the prior art, the use of an external freewheeling chip not only increases the scale of the circuit and the manufacturing cost of the chip, but also introduces additional parasitic capacitance and parasitic inductance into the circuit. Utility Model Content

[0005] One of the purposes of the utility model is to provide a semiconductor device to solve the problem that the circuit scale is enlarged and the manufacturing cost of the chip is increased when an external chip is connected.

[0006] To this end, the utility model provides a semiconductor device, a substrate; a plurality of first gate dielectric layers and a plurality of first gate conductive layers located on the substrate, used to form a plurality of transistor devices, the first gate conductive layer extends along a first direction, the plurality of first gate conductive layers are arranged in sequence along a second direction, and the ends of the plurality of first gate conductive layers are electrically connected to each other, wherein the ends of some adjacent first gate conductive layers are connected to each other to define a rectifying region; a second gate dielectric layer and a second gate conductive layer located on the substrate, used to form a super barrier rectifier, the second gate dielectric layer and the second gate conductive layer are stacked in sequence in the rectifying region, and the thickness of the second gate dielectric layer is less than the thickness of the first gate dielectric layer, and the length of the second gate conductive layer is less than the length of the first gate conductive layer.

[0007] Optionally, the semiconductor device further includes: a source region formed in the substrate on the side of the first gate conductive layer and in the substrate on the side of the second gate conductive layer.

[0008] Optionally, the semiconductor device also includes: an insulating dielectric layer, covering the first gate conductive layer, and a first contact hole and a second contact hole are opened in the insulating dielectric layer, the first contact hole exposes the second gate conductive layer, and the second contact hole exposes the source region; and a source metal layer, covering the insulating dielectric layer and filling the first contact hole and the second contact hole to electrically connect the source region and the second gate conductive layer.

[0009] Optionally, portions of adjacent first gate conductive layers are defined as source connection regions, and contact holes are formed in the source connection regions for electrically connecting the source regions.

[0010] Optionally, a connecting line is also formed on the substrate, the connecting line is located at the end of the first gate conductive layer and extends along the second direction, and the end of each first gate conductive layer is connected to the connecting line, and the end of the second gate conductive layer is spaced apart from the connecting line.

[0011] Optionally, the semiconductor device further includes: a gate metal layer, wherein the gate metal layer is formed on the connecting line and is used for electrically connecting the first gate conductive layer.

[0012] Optionally, a plurality of the first gate conductive layers are formed by the same conductive layer, the conductive layer is formed on the substrate, and a plurality of first opening regions extending along the first direction and at least one second opening region extending along the first direction are formed in the conductive layer, and the first opening regions and the second opening regions are arranged along the second direction. The portion of the conductive layer located on the side of the first opening region along the second direction constitutes the first gate conductive layer, the first opening region is used to form a source connection region; the second opening region is used to form the rectifying region, the second gate conductive layer is formed in the second opening region, and the length of the second gate conductive layer is less than the length of the second opening region.

[0013] Optionally, the semiconductor device further includes: an insulating dielectric layer, covering the conductive layer and the second gate conductive layer, and forming a first contact hole, a second contact hole and a third contact hole in the insulating dielectric layer. The first contact hole is located above the second gate conductive layer, and is used to expose the second gate conductive layer; the second contact hole is located in the first opening area, and is used to expose the source area; the third contact hole is located above the conductive layer, and is arranged outside the end of the first gate conductive layer, and is used to expose part of the conductive layer.

[0014] Optionally, the width of the second opening area is greater than the width of the first opening area.

[0015] Another object of the present invention is to provide a silicon carbide device integrated with a super-barrier rectifier, which comprises: the semiconductor device as described above, wherein the transistor device in the semiconductor device is a silicon carbide-based transistor device.

[0016] In the semiconductor device provided by the utility model, the gate structure in the superbarrier rectifier is arranged between the gate structures of adjacent transistor devices, so that the superbarrier rectifier can be integrated with the transistor device on the same chip without the need for an external chip, which is beneficial to improving the chip's surge resistance and preventing the problem of chip failure caused by surge current being concentrated on a certain chip due to poor chip consistency; at the same time, it is also beneficial to reducing the circuit scale and reducing the manufacturing cost of the chip. Moreover, integrating the superbarrier rectifier in the semiconductor device can further increase the switching speed and reduce the switching loss. The semiconductor device provided by the utility model is, for example, a silicon carbide device integrated with a superbarrier rectifier, which is beneficial to achieving circuit optimization and performance improvement of the silicon carbide device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the distribution of the first gate conductive layer and the second gate conductive layer of the semiconductor device in one embodiment of the utility model.

[0018] Figure 2 FIG. 4 is a schematic diagram showing the distribution of some contact holes of a semiconductor device in an embodiment of the present invention.

[0019] Figure 3 It is a schematic structural diagram of a semiconductor device, a transistor device and a super-barrier rectifier in one embodiment of the utility model.

[0020] Figure 4 This is a schematic structural diagram of a semiconductor device in an embodiment of the present invention, showing a source metal layer.

[0021] The reference numerals are as follows:

[0022] 100-substrate;

[0023] 110-source area;

[0024] 120-well region;

[0025] 210-a first gate dielectric layer;

[0026] 220- a second gate dielectric layer;

[0027] 310 - a first gate conductive layer;

[0028] 320- a second gate conductive layer;

[0029] 330-connecting wire;

[0030] 300a-first opening area;

[0031] 300b - second opening area;

[0032] 400-insulating dielectric layer;

[0033] 410-first contact hole;

[0034] 420-second contact hole;

[0035] 430-third contact hole;

[0036] 500 - Source metal layer. DETAILED DESCRIPTION

[0037] As described in the background technology, in the prior art, the use of an external freewheeling chip will result in a larger circuit scale and increase the manufacturing cost of the chip. To this end, the core concept of the utility model is to provide a method of embedding a rectifier into a semiconductor device to optimize circuit design and performance. In addition, a rectifier is formed using a Schottky barrier diode, which is more conducive to further reducing the forward voltage, improving the reverse recovery characteristics, and reducing the switching loss of the device compared to a super barrier rectifier (SBR).

[0038] In view of this, in the semiconductor device provided by the utility model, a super barrier rectifier (SBR) can be embedded in an adjacent transistor device to utilize the low turn-on voltage of the super barrier rectifier (SBR) to provide a current discharge channel for the transistor device when it is turned off. Specifically, the semiconductor device includes: a substrate, a plurality of transistor devices formed on the substrate, and at least one super barrier rectifier.

[0039] Among them, a plurality of first gate dielectric layers and a plurality of first gate conductive layers in a plurality of transistor devices are formed on a substrate, the first gate conductive layer extends along a first direction, a plurality of first gate conductive layers are sequentially arranged along a second direction, and the ends of the plurality of first gate conductive layers are connected to each other, wherein the ends of some adjacent first gate conductive layers are connected to each other to define a rectifying region. And, the super-barrier rectifier comprises a second gate dielectric layer and a second gate conductive layer located on the substrate, the second gate dielectric layer and the second gate conductive layer are sequentially stacked in the rectifying region, and the thickness of the second gate dielectric layer is less than the thickness of the first gate dielectric layer, and the length of the second gate conductive layer is less than the length of the first gate conductive layer.

[0040] The semiconductor device and the silicon carbide device integrated with the super-barrier rectifier proposed in the utility model are further described in detail below in conjunction with the accompanying drawings. According to the following description, the advantages and features of the utility model will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the utility model. It should be recognized that relative terms such as "above", "below", "top", "bottom", "above" and "below" shown in the drawings can be used to describe the relationship between various elements. These relative terms are intended to cover different orientations of elements other than the orientations depicted in the drawings. For example, if the device is inverted relative to the view in the drawing, an element described as "above" another element will now be below the element.

[0041] Figure 1 Schematic diagram of the distribution of the first gate conductive layer and the second gate conductive layer of the semiconductor device in one embodiment of the utility model, Figure 2 FIG. 1 is a schematic diagram showing the distribution of some contact holes of a semiconductor device in an embodiment of the present invention. Figure 3 It is a schematic structural diagram of a semiconductor device, a transistor device and a super-barrier rectifier in one embodiment of the utility model.

[0042] like Figure 1-Figure 3 As shown, the semiconductor device includes a substrate 100 and a transistor device and a super-barrier rectifier formed on the substrate 100 .

[0043] Specifically, the multiple transistor devices in the semiconductor device correspondingly include multiple first gate dielectric layers 210 and multiple first gate conductive layers 310, the first gate conductive layers 310 extend along a first direction (Y direction), and the multiple first gate conductive layers 310 are arranged in sequence along a second direction (X direction), and the ends of the multiple first gate conductive layers 310 are electrically connected to each other.

[0044] For example, please refer to Figure 1 As shown, a connection line 330 is provided at the end of the first gate conductive layer 310. The connection line 330 extends along the second direction (X direction) and can connect the end of each first gate conductive layer 310 to the connection line 330, thereby electrically connecting the ends of the plurality of first gate conductive layers 310 to each other. Further, a connection line 330 can be provided at both ends of the first gate conductive layer 310, so that both ends of each first gate conductive layer 310 are connected to the corresponding connection line 330.

[0045] In the specific examples, focus on Figure 1 As shown, a plurality of first gate conductive layers 310 are formed from the same conductive layer, the conductive layer is formed on the substrate 100, and a plurality of first opening regions 300a extending along the first direction and at least one second opening region 300b extending along the first direction are formed in the conductive layer, and the first opening regions 300a and the second opening regions 300b are arranged along the second direction (X direction). A plurality of first gate conductive layers 310 can be defined by the first opening regions 300a and the second opening regions 300b, that is, the portion of the conductive layer located on the side of the first opening region 300a along the second direction constitutes the first gate conductive layer 310, and the first opening region 300a can be used to form a source connection region.

[0046] Combination Figure 3 As shown, an active region 110 is also formed in the substrate 100. The source region 110 is formed in the substrate 100 on the side of the first gate conductive layer 310, that is, the source region 110 is arranged between some adjacent first gate conductive layers 310. Therefore, the area between some adjacent first gate conductive layers 310 can be defined as a source connection region, and a contact hole is formed in the source connection region for electrically connecting the source region 110. Figure 1 and Figure 3 In the example, the first opening region 300 a between adjacent first gate conductive layers 310 forms a source connection region.

[0047] Furthermore, ends of some adjacent first gate conductive layers 310 are connected to each other to define a rectifying region, and a super-barrier rectifier is formed in the rectifying region, for example Figure 1As shown, the second opening region 300 b in the conductive layer is used to form a rectifying region, wherein the width dimension of the second opening region 300 b is greater than the width dimension of the second opening region 300 b.

[0048] Specific reference Figure 1-Figure 3 As shown, the super-barrier rectifier includes a second gate dielectric layer 220 and a second gate conductive layer 320 located on the substrate 100, and the second gate dielectric layer 220 and the second gate conductive layer 320 are stacked in sequence in the rectifying region (i.e., the second opening region 300b). The thickness of the second gate dielectric layer 220 is less than the thickness of the first gate dielectric layer 210, so that when the transistor device is turned off, the super-barrier rectifier can still be turned on at a lower voltage and serve as a current discharge channel, thereby realizing rapid shutdown of the device and improving the reliability and switching frequency of the device. In addition, the length of the second gate conductive layer 320 is less than the length of the first gate conductive layer 310, so that the second gate conductive layer 320 is formed in the second opening region 300b, and the end of the second gate conductive layer 320 can maintain a distance from the connected wire 330 to avoid the second gate conductive layer 320 being electrically connected to the first gate conductive layer 310.

[0049] Continue to refer Figure 3 As shown, an active region 110 is also formed in the substrate on the side of the second gate conductive layer 320, and a contact hole may be provided above the source region 110. In this embodiment, the second gate conductive layer 320 is located in the middle of the second opening region 300b, and the active region 110 is provided on both sides of the second gate conductive layer 320.

[0050] In addition, a well region 120 is formed in the substrate 100, and a source region 110 is formed in the well region 120. Specifically, a plurality of well regions 120 extending along a first direction (Y direction) can be formed in the substrate 100, and the plurality of well regions 120 are sequentially arranged along a second direction (X direction); the first gate conductive layer 310 and the second gate conductive layer 320 cover the corresponding well regions 120, and a source region 110 is formed in each well region 120. When the transistor device or the super-barrier rectifier is turned on, the portion of the well region 120 located below the gate structure can be inverted to form a conductive channel.

[0051] Furthermore, an insulating dielectric layer 400 is formed on the substrate 100, and the insulating dielectric layer 400 covers the first gate conductive layer 310 and the second gate conductive layer 320, and a first contact hole 410 and a second contact hole 420 are formed in the insulating dielectric layer 400, the first contact hole 410 is located above the second gate conductive layer 30 and exposes the second gate conductive layer 320, and the second contact hole 420 exposes the source region 110. Specifically, the second contact hole 420 is formed in the first opening region 300a, and the second contact holes 420 are also formed in the second opening region 300b and on both sides of the second gate conductive layer 320.

[0052] For specific examples, continue to refer to Figure 2 As shown, the insulating dielectric layer 400 also covers the connecting wire 330, and the insulating dielectric layer 400 also forms a third contact hole 430 above the connecting wire 330 to expose the connecting wire 330 for electrically connecting the first gate conductive layer 310. Further, the first contact hole 410 and the second contact hole 420 both extend along the first direction (Y direction) for electrically leading out the second gate conductive layer 320 and the source region 110; the third contact hole 430 extends outside the ends of the first contact hole 410 and the second contact hole 420 and along the second direction (X direction) for electrically leading out the first gate conductive layer 310.

[0053] Next reference Figure 4 As shown, the semiconductor device further includes a source metal layer 500, which covers the insulating dielectric layer 400 and fills the first contact hole 410 and the second contact hole 420 to electrically connect the source region 110 and the second gate conductive layer 320. That is, the source metal layer 500 is used to electrically lead out the source region 110, and the second gate conductive layer 320 of the super barrier rectifier is also electrically connected to the source port.

[0054] In a further embodiment, the semiconductor device further includes a gate metal layer (not shown in the figure), which is formed on the connection line 330 and is used to electrically connect the first gate conductive layer 210. Specifically, the gate metal layer fills the third contact hole 430 to electrically connect the first gate conductive layer 210.

[0055] In summary, in the semiconductor device provided by the present disclosure, the super-barrier rectifier is arranged between adjacent transistor devices, so that the super-barrier rectifier can be integrated with the transistor device on the same chip without an external chip. On the one hand, it is beneficial to improve the chip's surge resistance and prevent the problem of chip failure caused by surge current concentrated on a certain chip due to poor chip consistency; on the other hand, it is also beneficial to reduce the circuit scale and reduce the manufacturing cost of the chip. In addition, the super-barrier rectifier is integrated in the semiconductor device, which can further improve the switching speed and reduce the switching loss.

[0056] The semiconductor device provided by the present disclosure is, for example, a silicon carbide device integrated with a super-barrier rectifier, that is, the transistor device in the semiconductor device can be a silicon carbide-based transistor device, so as to facilitate circuit optimization and performance improvement of the silicon carbide device.

[0057] It should be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the above disclosed technical content can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

[0058] It should also be recognized that the terms described herein are only used to describe specific embodiments and are not used to limit the scope of the utility model. It must be noted that the singular forms "one" and "a kind" used herein and in the appended claims include plural references unless the context clearly indicates the opposite meaning. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have a logical "or" definition, rather than a logical "exclusive or" definition, unless the context clearly indicates the opposite meaning. In addition, the implementation of the method and / or device in the embodiment of the utility model may include performing the selected task manually, automatically, or in combination.

Claims

1. A semiconductor device, characterized in that: include: substrate; A plurality of first gate dielectric layers and a plurality of first gate conductive layers located on the substrate are used to form a plurality of transistor devices, wherein the first gate conductive layers extend along a first direction, and the plurality of first gate conductive layers are sequentially arranged along a second direction, and ends of the plurality of first gate conductive layers are electrically connected to each other, wherein ends of some adjacent first gate conductive layers are connected to each other to define a rectifying region; The second gate dielectric layer and the second gate conductive layer located on the substrate are used to form a super barrier rectifier. The second gate dielectric layer and the second gate conductive layer are stacked in sequence in the rectifying region, and the thickness of the second gate dielectric layer is less than the thickness of the first gate dielectric layer, and the length of the second gate conductive layer is less than the length of the first gate conductive layer.

2. The semiconductor device according to claim 1, wherein Also includes: A source region is formed in the substrate on the side of the first gate conductive layer and in the substrate on the side of the second gate conductive layer.

3. The semiconductor device according to claim 2, wherein: Also includes: an insulating dielectric layer covering the first gate conductive layer, wherein a first contact hole and a second contact hole are formed in the insulating dielectric layer, wherein the first contact hole exposes the second gate conductive layer, and the second contact hole exposes the source region; and, A source metal layer covers the insulating dielectric layer and fills the first contact hole and the second contact hole to electrically connect the source region and the second gate conductive layer.

4. The semiconductor device according to claim 2, wherein: A source connection region is defined between portions of adjacent first gate conductive layers, and a contact hole is formed in the source connection region for electrically connecting the source region.

5. The semiconductor device according to claim 1, wherein: A connecting line is also formed on the substrate. The connecting line is located at the end of the first gate conductive layer and extends along the second direction. The ends of each first gate conductive layer are connected to the connecting line, and the ends of the second gate conductive layer are spaced apart from the connecting line.

6. The semiconductor device according to claim 5, characterized in that Also includes: A gate metal layer is formed on the connecting line and is used for electrically connecting the first gate conductive layer.

7. The semiconductor device according to claim 1, wherein: A plurality of the first gate conductive layers are formed from the same conductive layer, the conductive layer is formed on the substrate, and a plurality of first opening regions extending along a first direction and at least one second opening region extending along the first direction are formed in the conductive layer, and the first opening regions and the second opening regions are arranged along a second direction; Among them, the portion of the conductive layer located on the side of the first opening area along the second direction constitutes the first gate conductive layer, and the first opening area is used to form the source connection area; the second opening area is used to form the rectifying area, the second gate conductive layer is formed in the second opening area, and the length of the second gate conductive layer is less than the length of the second opening area.

8. The semiconductor device according to claim 7, wherein: Also includes: an insulating dielectric layer, covering the conductive layer and the second gate conductive layer, and forming a first contact hole, a second contact hole and a third contact hole in the insulating dielectric layer; wherein, The first contact hole is located above the second gate conductive layer and is used to expose the second gate conductive layer; The second contact hole is located in the first opening area and is used to expose the source region; The third contact hole is located above the conductive layer and is arranged outside the end of the first gate conductive layer to expose a portion of the conductive layer.

9. The semiconductor device according to claim 7, wherein: The width of the second opening area is greater than the width of the first opening area.

10. A silicon carbide device integrated with a superbarrier rectifier, characterized in that: include: The semiconductor device according to any one of claims 1 to 9, wherein the transistor device is a silicon carbide-based transistor device.

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