Processor mainboard and processor system

Abstract

The utility model provides a processor mainboard and a processor system, the processor mainboard comprises a mainboard substrate, a first processor and a second processor, the first processor and the second processor are fixedly arranged on the mainboard substrate, and the first processor is electrically connected with the second processor; the plurality of connecting ports are fixedly arranged on the mainboard substrate and are electrically connected with the first processor and the second processor respectively; the 16 memory slots are fixedly arranged on the mainboard substrate, 8 of the 16 memory slots are electrically connected with the first processor, and the other 8 of the 16 memory slots are electrically connected with the second processor; and the expansion connector is fixedly arranged on the mainboard substrate, is electrically connected with the first processor, and is used for being connected with an external input and output board. According to the utility model, interfaces on the processor mainboard can be enriched, and the integration level of the processor mainboard is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of computers, in particular to a processor mainboard and a processor system. Background Art

[0002] With the rapid development of the electronic equipment industry, the functions of processors in electronic equipment are becoming more and more diversified. However, existing processor motherboards have problems such as low integration and relatively simple interfaces on the motherboard. Utility Model Content

[0003] To solve the above problems, the processor motherboard and processor system provided by the present invention can enrich the interfaces on the processor motherboard and improve the integration of the processor motherboard by setting multiple connection ports, expansion connectors and 16 memory slots on the motherboard substrate.

[0004] In a first aspect, the utility model provides a processor mainboard, the processor mainboard comprising:

[0005] Main board substrate,

[0006] A first processor and a second processor are fixedly arranged on the mainboard substrate, and the first processor is electrically connected to the second processor;

[0007] A plurality of connection ports fixedly arranged on the mainboard substrate, the plurality of connection ports being electrically connected to the first processor and the second processor respectively;

[0008] 16 memory slots fixedly arranged on the mainboard substrate, 8 of the 16 memory slots are electrically connected to the first processor, and the other 8 of the 16 memory slots are electrically connected to the second processor; and

[0009] An expansion connector is fixedly arranged on the mainboard substrate, the expansion connector is electrically connected to the first processor, and the expansion connector is used to connect an input and output board of a peripheral device.

[0010] Optionally, the processor mainboard further includes:

[0011] A BMC chip fixedly disposed on the mainboard substrate, the BMC chip being electrically connected to the first processor; and

[0012] The video graphics array switch module is fixedly arranged on the mainboard substrate, and the video graphics array switch module and the BMC chip.

[0013] Optionally, the expansion connector is also electrically connected to an off-board PHY chip and an input / output board, and the PHY chip is electrically connected to the BMC chip.

[0014] Optionally, the processor mainboard further includes:

[0015] The MUX chip and the flash chip are fixedly arranged on the mainboard substrate, the flash chip stores BIOS firmware, the flash chip is electrically connected to the MUX chip, and the MUX chip is selectively electrically connected to the first processor and the BMC chip.

[0016] Optionally, the plurality of connection ports include a plurality of MCIO physical slots.

[0017] Optionally, the number of the plurality of MCIO physical slots is 13;

[0018] Seven of the 13 MCIO physical slots are electrically connected to the first processor, and the other six of the 13 MCIO physical slots are electrically connected to the second processor.

[0019] Optionally, six of the seven MCIO physical slots electrically connected to the first processor are X8 MCIO physical slots, and one is an X4 MCIO physical slot;

[0020] The six MCIO physical slots electrically connected to the second processor are all MCIO physical slots of X8 specification.

[0021] Optionally, the plurality of connection ports further include an OCP connector, a Smart NIC connector, a SlimLine connector, a SATA physical slot, and a USB interface;

[0022] The OCP connector, the Smart NIC connector, the SlimLine connector, the SATA physical slot and the USB interface are all electrically connected to the first processor.

[0023] Optionally, the number of the OCP connector, the Smart NIC connector, the SlimLine connector, and the USB interface is one;

[0024] The number of physical SATA slots is four.

[0025] In a second aspect, the present invention provides a processor system, the processor system comprising: a processor mainboard as described in any one of the above items.

[0026] The processor mainboard and processor system provided by the embodiment of the utility model, by arranging multiple connection ports, expansion connectors and 16 memory slots on the mainboard substrate, enable the processor mainboard to be connected to a display device and various types of input and output devices, enrich the interfaces on the processor mainboard, and improve the integration of the processor mainboard. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 A partial circuit diagram of a processor motherboard according to an embodiment of the present application;

[0029] Figure 2 A partial circuit diagram of a processor motherboard according to an embodiment of the present application;

[0030] Figure 3 This is a schematic structural diagram of a processor motherboard according to an embodiment of the present application. DETAILED DESCRIPTION

[0031] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0033] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0034] It should be noted that when an element is referred to as being "fixedly connected" to another element, it may be directly on the other element or there may also be a central element. When an element is considered to be "connected" to another element, it may be directly connected to the other element or there may be a central element at the same time. In contrast, when an element is referred to as being "directly on" another element, there is no intermediate element. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0035] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0036] With the development of chip design technology, more and more IP (intellectual property core, which refers to a reusable module in the form of logic unit and chip design provided by one party) are integrated on a single processor, and the number of corresponding IO (input and output) interfaces is also increasing, such as PCIe Gen5 (fifth generation peripheral component interconnect express) and DIMM (dual in-line memory module) interfaces, and the signal quality requirements for differential buses connected to processors are getting higher and higher, such as xHCL and PCIe Gen5 buses. Therefore, the need to verify processor functions and features is becoming more and more urgent at this stage. In processor design and verification, a motherboard is needed to implement and verify processor-related functions and features.

[0037] The Gen-Z connector involved in the utility model is a new type of connector, which adopts high-speed data transmission technology and can achieve ultra-high-speed data transmission. It is mainly used for connecting communication and data transmission between different devices. Its working principle is to achieve connection and communication between devices by transmitting data and power signals.

[0038] In a first aspect, an embodiment of the present invention provides a processor motherboard, see Figure 1 , Figure 2 and Figure 3The processor motherboard includes: a motherboard substrate 1, a first processor 21 and a second processor 22 fixedly arranged on the motherboard substrate 1, and the first processor 21 is electrically connected to the second processor 22; a plurality of connection ports 3 fixedly arranged on the motherboard substrate 1, and the plurality of connection ports 3 are electrically connected to the first processor 21 and the second processor 22 respectively; 16 memory slots 36 fixedly arranged on the motherboard substrate 1, 8 memory slots 36 of the 16 memory slots 36 are electrically connected to the first processor 21, and the other 8 memory slots 36 of the 16 memory slots 36 are electrically connected to the second processor 22; and an expansion connector 51 fixedly arranged on the motherboard substrate 1, the expansion connector 51 is electrically connected to the first processor 21, and the expansion connector 51 is used to connect an input and output board 52 of an external device.

[0039] In this embodiment, the mainboard substrate 1 is a printed circuit board, and the interfaces and electronic devices thereon can be electrically connected to each other through the circuit inside the mainboard substrate 1, and this embodiment does not make any specific limitation to this; the expansion connector 51 is a 2C version of the Gen-Z connector.

[0040] Specifically, the first processor 21 and the second processor 22 are the same processor. In this embodiment, the first processor 21 and the second processor 22 are CPU0 (central processing unit 0) and CPU1 respectively; each processor is configured with nine high-speed Serdes (serializer / deserializer) ports, namely G0, G1, G2, G3, G4, G5, P6, P7 and P8 ports. Among them, the P8 port on the first processor 21 and the second processor 22 (the P8 port on the second processor 22 is not shown in the figure) supports the PCIe Gen3 protocol, and is backward compatible with the PCIe Gen2 protocol and the PCIe Gen1 protocol. Figure 1 The P8 port of the second processor 22 is shown in the figure; the G0, G1, G2, G3, G4, G5, P6 and P7 ports on the first processor 21 and the second processor 22 all support PCIe Gen5, and are backward compatible with supporting PCIe Gen4, PCIe Gen3, PCIe Gen2 and PCIe Gen1.

[0041] In addition, the first processor 21 and the second processor 22 both support SATA rates of 1.5 Gbps, 3 Gbps, and 6 Gbps, support 4-port XGBE (10 Gigabit Ethernet), and both support three protocols: 10GBASE-KR (Gigabit Ethernet Physical Coding Sublayer / Physical Medium Access Layer), SFI (Simple Network Management) and SGMII (Serial Gigabit Media Independent Interface).

[0042] The detailed configuration specifications of the ports G0, G1, G2, G3, G4, G5, P6 and P7 on the first processor 21 and the second processor 22 are as follows:

[0043] The G0-G3 ports on CPU0 are configured as a protocol for communicating with the G0-G3 ports on CPU1, which is not specifically limited in this embodiment; the G4[15:0] port on CPU0 is configured as the PCIe protocol; the G5[15:0] port on CPU0 is configured as the PCIe protocol; the P6[7:0] port on CPU0 is configured as the SATA protocol; the P6[15:8] port on CPU0 is configured as the PCIe protocol; the P7[15:0] port on CPU0 is configured as the PCIe protocol; the P8[1:0] port on CPU0 is configured as the PCIe protocol; the G4[15:0] port on CPU1 is configured as the PCIe protocol; the G5[15:0] port on CPU1 is configured as the PCIe protocol; the P6[15:0] port on CPU1 is configured as the SATA protocol; and the P7[15:0] port on CPU1 is configured as the PCIe protocol.

[0044] Combination Figure 1 and Figure 2 The multiple connection ports 3 also include an OCP (Open Computing Project) connector 31, a SmartNIC (Smart Network Card) connector 32, a SlimLine (Slim Line Cable) connector 33, a USB (Universal Serial Bus) interface 34, a set of SATA (Serial Advanced Technology Attachment) physical slots 35 and multiple MCIO (Mini Cold Edge) physical slots 37.

[0045] Among them, an OCP connector 31 , a Smart NIC connector 32 , a SlimLine connector 33 , a USB interface 34 , and a group of SATA physical slots 35 are all electrically connected to the first processor 21 .

[0046] In this embodiment, the USB interface 34 is a USB2.0 Type A interface; a group of SATA physical slots 35 includes four SATA physical slots 35; and the number of the plurality of MCIO physical slots 37 is 13.

[0047] Among them, 6 MCIO physical slots 37 among the 13 MCIO physical slots 37 are electrically connected to the first processor 21 , another 6 MCIO physical slots 37 among the 13 MCIO physical slots 37 are electrically connected to the second processor 22 , and the remaining 1 MCIO physical slot 37 among the 13 MCIO physical slots 37 is electrically connected to the first processor 21 .

[0048] In this embodiment, the first processor 21 and the second processor 22 are both provided with 8 double data rate synchronous dynamic random access memory (DDR) 4 memory channels, and the 8 DDR4 memory channels on each processor are numbered CH A, CH B, CHC, CH D, CH E, CH F, CH G and CH H, respectively. Each DDR5 memory channel can support up to 3200MHz, and each DDR4 memory channel can be installed with up to two DIMMs (dual in-line memory modules), so that the processor motherboard supports a maximum of 16 memory sticks. Among them, the memory stick supports four types: RDIMM (registered DIMM), LRDIMM (load reduced DIMM), NVDIMM (non-volatile DIMM) and 3DSDIMM (three-dimensional stacked DIMM).

[0049] The specific connection relationship between each port on the first processor 21 and the second processor 22 and the multiple connection ports 3 is as follows:

[0050] The G4[15:0] port on CPU0 is connected using two standard MCIO physical slots with a specification of X8, so that the port can support PCIe device adaptation;

[0051] The G5[15:0] port on CPU0 is connected using two standard MCIO physical slots with a specification of X8, so that the port can support PCIe device adaptation;

[0052] The P6[15:8] port on CPU0 is connected using a 3.0 version OCP physical slot, so that the port can support PCIe device adaptation;

[0053] The P6[7:4] port on CPU0 is connected using a standard SlimLine connector 33 with a specification of X4, so that the port can support SATA device adaptation;

[0054] The P6[3:0] port on CPU0 is connected using four standard SATA physical slots 35, so that the port can support SATA device adaptation;

[0055] The P7[15:0] port on CPU0 is connected using two standard MCIO physical slots with a specification of X8, so that the port can support PCIe device adaptation;

[0056] The G4[15:8] port on CPU1 is connected using a standard MCIO physical slot with a specification of X8, so that the port can support PCIe device adaptation;

[0057] The G5[7:0] port on CPU1 is connected using a standard MCIO physical slot with a specification of X8, so that the port can support PCIe device adaptation;

[0058] The P6[15:0] port on CPU1 is connected using two standard MCIO physical slots with a specification of X8, so that the port can support PCIe device adaptation;

[0059] The P7[15:0] port on CPU1 is connected using two standard MCIO physical slots with a specification of X8, so that the port can support PCIe device adaptation.

[0060] In addition, P4[15:8] (not shown in the figure) in the tenth high-speed Serdes port on CPU1 is connected using a standard PCIeX8 physical slot, so that the port can support PCIe device adaptation.

[0061] It should be noted that connectors or physical slots of different specifications indicate different numbers of channels thereon. For example, an MCIO physical slot of X8 specification indicates that the MCIO physical slot has 8 channels. Similarly, an SATA physical slot 35 of X4 specification indicates that the SATA physical slot 35 has 4 channels.

[0062] In addition, the G0, G1, G2 and G3 ports on the first processor 21 and the second processor 22 are all configured as ports for interconnecting processing devices, wherein the G0 port on CPU0 can be interconnected with the G2 port on CPU1 via a cable, and the G2 port on CPU0 can be interconnected with the G0 port on CPU1 via a cable; the G1 port on CPU0 can be interconnected with the G3 port on CPU1 via a cable, and the G3 port on CPU0 can be interconnected with the G1 port on CPU1 via a cable.

[0063] The processor motherboard further includes: a BMC (baseboard management controller) chip 61 fixedly arranged on the motherboard substrate 1, the BMC chip 61 is electrically connected to the first processor 21, in this embodiment, the P8[0] port on the first processor 21 is connected to the onboard BMC chip 61, the BMC chip 61 can be used as a small operating system independent of the server system, and has an independent IP firmware system, which is not specifically limited in this embodiment; and a video graphics array switch (VGASW) module 62 fixedly arranged on the motherboard substrate 1, the video graphics array switch module 62 is electrically connected to the BMC chip 61 and the VGA interface 4 outside the board, respectively. Among them, the video graphics array switch module 62 is electrically connected to the VGA interface 4, and the VGA interface 4 is also electrically connected to the expansion connector 51.

[0064] Further, the VGA interface 4 includes: a front VGA sub-interface 41 and a rear VGA sub-interface 42;

[0065] The front VGA sub-interface 41 is fixedly arranged on the front side of the mainboard substrate 1, and the rear VGA sub-interface 42 is fixedly arranged on the rear side of the mainboard substrate 1. Both the front VGA sub-interface 41 and the rear VGA sub-interface 42 are electrically connected to the video graphics array switch module 62, and the rear VGA sub-interface 42 is electrically connected to the expansion connector 51. The front VGA sub-interface 41 is electrically connected to the MCIO physical slot 37 of specification X4, so that the MCIO physical slot 37 can support the VGA function.

[0066] Combination Figure 1 The expansion connector 51 is also electrically connected to the off-board PHY chip 63 and the input-output board 52 (IO board), and the PHY chip 63 is electrically connected to the BMC chip. In this embodiment, the input-output board 52 supports BMC network ports, m.2 (next generation size specification) devices, and USB devices. Figure 1 and Figure 3 The processor motherboard further includes: a power input connector 64 fixedly arranged on the motherboard substrate 1, the power input connector 64 is electrically connected to the first processor 21 and the second processor 22; and a MUX (multiplexer) chip 65 and a flash (flash memory) chip 66 fixedly arranged on the motherboard substrate 1, the flash chip 66 stores BIOS (basic input and output system) firmware, the flash chip 66 is electrically connected to the MUX chip 65, and the MUX chip 65 is selectively electrically connected to the first processor 21 and the BMC chip 61. The MUX chip 65 is used to select one of the BMC chip 61 and the first processor 21 to be electrically connected to the flash chip 66.

[0067] In this embodiment, the first processor 21 supports 4 groups of ports for USB 3.1 and 8 groups of ports for USB 2.0, and none of the USB ports in the second processor 22 are externally connected. In the first processor 21, 1 group of ports supporting USB 2.0 is connected to the BMC chip 61; 1 group of ports supporting USB 2.0 is fanned out to the OCP connector 31; 1 group of ports supporting USB 2.0 is fanned out to the Smart NIC connector 32; 2 groups of ports supporting USB 2.0 and 2 groups of ports supporting USB 3.1 are fanned out to the expansion connector 51; 2 groups of ports supporting USB 2.0 and 2 groups of ports supporting USB 3.1 are fanned out to the MCIO physical slot 37 with a specification of X4.

[0068] The processor motherboard provided in this embodiment supports dual-channel CPU interconnection, supports multiple IO devices, and supports DDR4 memory. The increase in the number of CPU cores and threads effectively improves the CPU processing performance, and can also meet the characteristic requirements of the signal quality of high-speed signal transmission lines. At the same time, it specifically includes managing the flash chip 66, controlling the remote system management network interface through the network, controlling the VGA display output of the system, and monitoring the system temperature and managing the fan strategy. In addition, the processor motherboard can support many IO devices, and can flexibly configure and expand the device through the PCIe, SATA, and XGBE differential buses on the interface of the motherboard substrate 1, which can effectively meet the needs of dual-channel servers in the industry, and is particularly suitable for applications in the Internet, storage, and GPU servers.

[0069] In a second aspect, the present invention provides a processor system, the processor system comprising: a processor mainboard as in the first aspect.

[0070] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0071] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0072] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A processor motherboard, characterized in that: The processor mainboard comprises: Main board substrate, A first processor and a second processor are fixedly arranged on the mainboard substrate, wherein the first processor is electrically connected to the second processor; A plurality of connection ports fixedly arranged on the mainboard substrate, the plurality of connection ports being electrically connected to the first processor and the second processor respectively; 16 memory slots fixedly arranged on the mainboard substrate, 8 of the 16 memory slots are electrically connected to the first processor, and the other 8 of the 16 memory slots are electrically connected to the second processor; and An expansion connector is fixedly arranged on the mainboard substrate, the expansion connector is electrically connected to the first processor, and the expansion connector is used to connect an input and output board of a peripheral device.

2. The processor motherboard according to claim 1, characterized in that: The processor motherboard also includes: A BMC chip fixedly disposed on the mainboard substrate, the BMC chip being electrically connected to the first processor; and A video graphics array switch module is fixedly arranged on the mainboard substrate, and the video graphics array switch module is connected to the BMC chip.

3. The processor motherboard according to claim 2, characterized in that: The expansion connector is also electrically connected to an off-board PHY chip, and the PHY chip is electrically connected to the BMC chip.

4. The processor motherboard according to claim 2, characterized in that: The processor motherboard also includes: A MUX chip and a flash chip are fixedly arranged on the mainboard substrate, the flash chip stores BIOS firmware, the flash chip is electrically connected to the MUX chip, and the MUX chip is selectively electrically connected to the first processor and the BMC chip.

5. The processor motherboard according to claim 1, characterized in that: The plurality of connection ports include a plurality of MCIO physical slots.

6. The processor motherboard according to claim 5, characterized in that: The number of the plurality of MCIO physical slots is 13; Seven of the 13 MCIO physical slots are electrically connected to the first processor, and the other six of the 13 MCIO physical slots are electrically connected to the second processor.

7. The processor motherboard according to claim 6, characterized in that: Among the seven MCIO physical slots electrically connected to the first processor, six are X8 MCIO physical slots and one is X4 MCIO physical slot; The six MCIO physical slots electrically connected to the second processor are all X8 MCIO physical slots.

8. The processor motherboard according to any one of claims 1 to 7, characterized in that: The plurality of connection ports also include an OCP connector, a Smart NIC connector, a SlimLine connector, a SATA physical slot, and a USB interface; The OCP connector, the Smart NIC connector, the SlimLine connector, the SATA physical slot and the USB interface are all electrically connected to the first processor.

9. The processor motherboard according to claim 8, characterized in that: The number of the OCP connector, the Smart NIC connector, the SlimLine connector, and the USB interface is one; The number of the SATA physical slots is four.

10. A processor system, characterized in that: The processor system comprises: a processor mainboard according to any one of claims 1 to 9.

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