Chip packaging structure

Abstract

The utility model belongs to the technical field of chip packaging, and specifically relates to a chip packaging structure comprising a substrate which comprises a first welding zone and a second welding zone; the first side of the power chip is provided with a first terminal array, and the first terminal array is electrically connected with the first welding area through flip-chip welding; the control driving chip is fixed on the second side of the power chip; a first pin is arranged on one side, opposite to the power chip, of the control chip, and the first pin is electrically connected with the second welding area through a first bonding wire. According to the chip packaging structure provided by the utility model, the power chip and the control driving chip are longitudinally stacked, the power chip is welded with the substrate by adopting a flip-chip process, and the control driving chip is welded with the substrate by adopting a bonding wire, so that the welding structure is simplified, the area of a bonding pad is reduced, and the manufacturing cost is reduced; meanwhile, due to the reduction of the area, the power density of the chip is also improved.

Description

Technical Field

[0001] The utility model belongs to the technical field of chip packaging, and in particular relates to a chip packaging structure. Background Art

[0002] Power management chips generally include power chips and control driver chips. In the prior art, the two chips are generally packaged independently and then connected through a circuit board, or the two chips are packaged on the same substrate. However, the packaging method in the prior art has a low degree of integration, and the pad structure of the substrate is too complicated, resulting in an increase in the manufacturing cost of the substrate. The complex pad structure may also cause electromigration, affecting the working performance of the chip. In addition, the existing chip packaging process cannot fully utilize the longitudinal space of the chip, resulting in a large package area, which affects the power density of the chip. Utility Model Content

[0003] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a chip packaging structure that can improve space utilization and simplify the substrate pad structure.

[0004] In order to achieve the above-mentioned object and other related objects, the utility model provides a chip packaging structure, including:

[0005] a substrate, the substrate comprising a first welding area and a second welding area;

[0006] A power chip, wherein a first terminal array is provided on a first side of the power chip, and the first terminal array is electrically connected to the first welding area through flip-chip welding;

[0007] A control driving chip is fixed to the second side of the power chip, the second side is the side facing away from the first side; a first pin is provided on the side of the control driving chip facing away from the power chip, the first pin is electrically connected to the second welding area through a first bonding wire.

[0008] In an optional embodiment of the utility model, a third welding area is provided on the substrate, a second terminal array is provided on the first side of the power chip, a second pin is provided on the side of the control driver chip facing away from the power chip, the second pin is electrically connected to the third welding area through a second bonding wire, and the second terminal array is electrically connected to the third welding area through flip-chip welding, so that the second pin is electrically connected to the second terminal array.

[0009] In an optional embodiment of the present invention, the first terminal array includes an input terminal and an output terminal, a first redistribution layer and a second redistribution layer are provided on the first side of the power chip, the input terminals are arranged into a plurality of first column units through the first redistribution layer, and the output terminals are arranged into a plurality of second column units through the second redistribution layer, and the first column units and the second column units are arranged alternately.

[0010] In an optional embodiment of the present invention, the first welding area includes a first sub-welding area and a second sub-welding area, the distribution pattern between the first sub-welding area and the second sub-welding area corresponds to the distribution pattern between the first column units and the second column units, the first column units are electrically connected to the first sub-welding area, and the second column units are electrically connected to the second sub-welding area.

[0011] In an optional embodiment of the present invention, a passivation layer and a protection layer are sequentially provided on the first side of the power chip, and the first redistribution layer and the second redistribution layer are arranged on the passivation layer and covered in the protection layer.

[0012] In an optional embodiment of the present invention, the input terminal and the output terminal are respectively provided with metal bumps, and the metal bumps are respectively protruded from the first redistribution layer and the second redistribution layer to the outside of the protective layer.

[0013] In an optional embodiment of the present invention, a distance between adjacent first redistribution layers and second redistribution layers is 20-50 μm.

[0014] In an optional embodiment of the present invention, a distance between adjacent first sub-welding areas and second sub-welding areas is 40-60 μm.

[0015] In an optional embodiment of the present invention, the substrate includes an insulating base, the first welding area and the second welding area are arranged on a first side of the insulating base, an I / O terminal is provided on the second side of the insulating base, an internal conductor is provided inside the insulating base, and the first welding area and the second welding area are electrically connected to the I / O terminal through the internal conductor respectively.

[0016] In an optional embodiment of the present invention, the internal conductor is provided in multiple layers along the thickness direction of the insulating substrate, and the internal conductors in each layer are interconnected.

[0017] In an optional embodiment of the present invention, the thickness of the first welding area and / or the second welding area and / or the internal conductor is 25-50 μm.

[0018] In an optional embodiment of the present invention, the spacing between the internal conductors of each two adjacent layers is 30-50 μm.

[0019] The technical effect of the utility model is that the chip packaging structure of the utility model stacks the power chip and the control driver chip vertically, wherein the power chip is welded to the substrate using a flip-chip process, and the control driver chip is welded to the substrate using bonding wires, which simplifies the welding structure, reduces the pad area, and reduces the manufacturing cost; at the same time, due to the reduction in area, the power density of the chip is also improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a three-dimensional diagram of a chip packaging structure provided by an embodiment of the utility model;

[0021] Figure 2 is a cross-sectional view of a chip packaging structure provided by an embodiment of the utility model;

[0022] Figure 3 is a partial cross-sectional view of a power chip provided by an embodiment of the utility model;

[0023] Figure 4 It is a schematic diagram of the terminal distribution structure of the first side of the power chip provided by an embodiment of the utility model;

[0024] Figure 5 It is a schematic diagram of the distribution of the substrate welding area provided by the embodiment of the utility model.

[0025] Explanation of the reference numerals: 10, substrate; 11, first welding area; 111, first sub-welding area; 112, second sub-welding area; 12, second welding area; 13, third welding area; 14, insulating base; 15, internal conductor; 16, I / O terminal; 20, power chip; 21, first terminal array; 211, first column unit; 2111, input terminal; 212, second column unit; 2121, output terminal; 22, second terminal array; 23, first redistribution layer; 24, second redistribution layer; 30, control driver chip; 31, first pin; 32, second pin; 40, first bonding wire; 50, second bonding wire; 60, plastic packaging part. DETAILED DESCRIPTION

[0026] The following describes the implementation of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0027] It should be noted that the illustrations provided in the following embodiments are only used to schematically illustrate the basic concept of the present invention, and thus the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0028] A power management chip (PMIC) is an integrated circuit chip used to manage the power supply and energy consumption of electronic devices. It is responsible for monitoring and controlling various aspects of the power management system to ensure stable operation of the device and optimize energy efficiency. Specifically, PMIC can, for example, convert the voltage of the power input to meet the needs of the internal circuit of the device. For example, it can convert high voltage to low voltage for use by various parts of the device. PMIC can also be responsible for monitoring the battery power and status, as well as the charging and discharging process. It can provide battery information, control the charging speed and discharge power, and protect the battery from damage caused by overcharging and over-discharging. The power management chip generally includes a power chip and a control driver chip. The two need to be connected not only to external electronic devices, but also to each other. The existing packaging structure generally welds the power chip and the control driver chip side by side on the substrate. This packaging method causes the pad structure of the substrate to be too complicated, and the manufacturing cost of the substrate increases. The complex pad structure may also cause electromigration, affecting the working performance of the chip. In addition, the existing chip packaging process cannot make full use of the longitudinal space of the chip, resulting in a large package area, which affects the power density of the chip. To this end, the utility model proposes a stacked packaging structure of a power management chip. The utility model stacks the power chip and the control driver chip vertically, wherein the power chip is welded to the substrate using a flip-chip process, and the control driver chip is welded to the substrate using bonding wires, which simplifies the welding structure, reduces the pad area, and reduces the manufacturing cost. At the same time, due to the reduction in area, the power density of the chip is also improved.

[0029] See also Figure 1-5 As shown, the technical solution of the utility model is described in detail below in conjunction with specific embodiments:

[0030] See also Figure 1, 2 As shown, the power management chip packaging structure provided by the embodiment of the utility model includes a substrate 10, a power chip 20 and a control driving chip 30; wherein the substrate 10 serves as a carrier of the power chip 20 and the control driving chip 30, and is provided with an I / O terminal 16 thereon.

[0031] In a specific embodiment, the substrate 10 includes an insulating base 14, a first welding area 11 and a second welding area 12 are provided on a first side of the insulating base 14, an I / O terminal 16 is provided on a second side of the insulating base 14, an internal conductor 15 is provided inside the insulating base 14, and the first welding area 11 and the second welding area 12 are electrically connected to the I / O terminal 16 through the internal conductor 15. The power management chip is electrically connected to an external device through the I / O terminal 16, for example, to a printed circuit board (PCB).

[0032] A first terminal array 21 is provided on the first side of the power chip 20, and the first terminal array 21 is electrically connected to the first welding area 11 through flip-chip welding; the control driving chip 30 is fixed to the second side of the power chip 20, and the second side is the side facing away from the first side; in a specific embodiment, the control driving chip 30 can be fixedly connected to the power chip 20 through an adhesive film, for example; a first pin 31 is provided on the side of the control driving chip 30 facing away from the power chip 20, and the first pin 31 is electrically connected to the second welding area 12 through a first bonding wire 40.

[0033] In a specific embodiment, in order to ensure product performance and improve the yield rate, certain restrictions may be imposed on the materials and dimensions of each structure. For example, the first bonding wire 40 may be a copper wire or a gold wire. The materials of the first welding area 11 and the second welding area 12 may be copper or other metal or non-metal materials with good electrical conductivity and convenient for welding. The thickness of the first welding area 11 and the second welding area 12 may be, for example, 25-50 μm, and the surface thereof may also be treated with corrosion protection, for example, an OSP (Organic solderability preservative) protective layer may be provided on the surface. The internal conductor 15 may be provided with multiple layers, for example, the internal conductor 15 may be provided with more than 4 layers to provide better electrical conductivity. The thickness of each layer of the internal conductor 15 may be, for example, 25-50 μm, and the spacing between two adjacent layers of the internal conductor 15 may be, for example, 30-50 μm, wherein the bottom layer of the internal conductor 15 is exposed on the second side of the substrate 10. In a further embodiment, in order to improve the corrosion resistance, oxidation resistance and electrical conductivity of the bottom layer of the internal conductor 15, a NiPdAu coating may be provided on the surface of the internal conductor 15.

[0034] The chip packaging structure of the utility model stacks the power chip 20 and the control driver chip 30 vertically, wherein the power chip 20 is welded to the substrate 10 using a flip-chip process, and the control driver chip 30 is welded to the substrate 10 using bonding wires, which simplifies the welding structure, reduces the pad area, and reduces the manufacturing cost; at the same time, due to the reduction in area, the power density of the chip is also improved.

[0035] See also Figure 1 , 4 As shown in Figure 5, in a further embodiment, a third welding area 13 is provided on the substrate 10, a second terminal array 22 is provided on the first side of the power chip 20, a second pin 32 is provided on the control driving chip 30 and the side facing away from the power chip 20, the second pin 32 is electrically connected to the third welding area 13 through a second bonding wire 50, and the second terminal array 22 is electrically connected to the third welding area 13 through flip-chip welding, so that the second pin 32 is electrically connected to the second terminal array 22.

[0036] It should be understood that the third welding area 13 is used to achieve electrical interconnection between the power chip 20 and the control driver chip 30; in a specific embodiment, the third welding area 13 can have a certain length of extension on the surface of the substrate 10, so that part of the third welding area 13 extends to the bottom of the power chip 20, and the remaining part of the area is exposed outside the power chip 20, wherein the area extending to the bottom of the power chip 20 is used to connect the second terminal array 22, and the welding between the second terminal array 22 and the third welding area 13 can be achieved simultaneously when the power chip 20 is flip-chip welded, and the area exposed outside the power chip 20 is used to connect the second pin 32 of the control driver chip 30, and when the control driver chip 30 and the substrate 10 are bonding wire welded, the bonding wire welding between the second pin 32 and the third welding area 13 can be performed simultaneously, which simplifies the welding operation process and improves the packaging efficiency.

[0037] See also Figure 4 As shown, in an optional embodiment of the present invention, the first terminal array 21 includes an input terminal 2111 and an output terminal 2121, a first redistribution layer 23 and a second redistribution layer 24 are provided on the first side of the power chip 20, the input terminal 2111 is arranged into a plurality of first column units 211 through the first redistribution layer 23, the output terminal 2121 is arranged into a plurality of second column units 212 through the second redistribution layer 24, and each first column unit 211 and each second column unit 212 are arranged alternately. Correspondingly, the first welding area 11 includes a first sub-welding area 111 and a second sub-welding area 112, the distribution mode between the first sub-welding area 111 and the second sub-welding area 112 corresponds to the distribution mode between the first column unit 211 and the second column unit 212, the first column unit 211 is electrically connected to the first sub-welding area 111, and the second column unit 212 is electrically connected to the second sub-welding area 112.

[0038] Overall, the input terminals 2111 and the output terminals 2121 are distributed in a rectangular array. Similarly, in order to ensure product performance and improve the yield rate, in a specific embodiment, the total density of the input terminals 2111 and the output terminals 2121 can be set to 20 / mm 2 ; The spacing between the first redistribution layer 23 and the second redistribution layer 24 can be 20-50μm; the spacing from the edge of the input terminal 2111 to the edge of the first redistribution layer 23 and the spacing from the edge of the output terminal 2121 to the edge of the second redistribution layer 24 can be 15-50μm; the spacing between each input terminal 2111 in the same first column unit 211 can be 100-150μm, and the spacing between each output terminal 2121 in the same second column unit 212 can be 100-150μm; the spacing between the first sub-welding area 111 and the second sub-welding area 112 is 40-60μm.

[0039] It should be noted that the redistribution layer (RDL) is an electrical extension and interconnection structure in wafer-level packaging. Its function is to change the contact position of the originally designed chip circuit through the wafer-level metal wiring process and the bump process, so that the chip can be suitable for different packaging forms.

[0040] The terminal layout of the present invention can make the pad structure of the substrate 10 more concise, which is convenient for processing the substrate 10; at the same time, the layout has good electrical interconnection performance and anti-electromigration capability.

[0041] See also Figure 3 As shown, in a further embodiment, a passivation layer 25 and a protective layer 26 are sequentially provided on the first side of the power chip 20, and the first redistribution layer 23 and the second redistribution layer 24 are arranged on the passivation layer 25 and covered in the protective layer 26; the input terminal 2111 and the output terminal 2121 are respectively provided with metal bumps, and the metal bumps protrude from the first redistribution layer 23 and the second redistribution layer 24 to the outside of the protective layer 26 respectively.

[0042] In a specific embodiment, the metal bumps may be copper bumps, for example, the thickness of the silicon wafer substrate of the power chip 20 may be 150-200 mm, the passivation layer 25 may be SiO and / or SiN, and the thickness of the passivation layer 25 may be 1-3 μm; the thickness of the first redistribution layer 23 and the second redistribution layer 24 may be 8-10 μm; the material of the protective layer 26 may be polyimide, and the thickness may be 10-12 μm; the metal bumps may be circular or elliptical, and the diameter or short side length may be 100-150 μm, and the height may be 40-70 μm; the solder 27 between the metal bumps and the substrate 10 may be SnAg alloy, and the thickness of the solder 27 may be 15-25 μm. The power management chip manufactured according to the above dimensions has good stress performance while ensuring good electrical interconnection performance.

[0043] See also Figure 1 As shown, it also includes a plastic sealing part 60, which can be formed on one side of the substrate 10 through an injection molding process. The power chip 20 and the control driver chip 30 are covered in the plastic sealing part 60. The plastic sealing part 60 is used to protect the power chip 20, the control driver chip 30 and related circuits.

[0044] To sum up, the chip packaging structure of the utility model stacks the power chip and the control driver chip vertically, wherein the power chip is welded to the substrate using a flip-chip process, and the control driver chip is welded to the substrate using bonding wires, which simplifies the welding structure, reduces the pad area, and reduces the manufacturing cost; at the same time, due to the reduction in area, the power density of the chip is also improved; the terminal layout method of the utility model can make the substrate pad structure matched therewith more concise and facilitate the processing of the substrate; at the same time, the terminal layout method has good electrical interconnection performance and anti-electromigration ability; the utility model optimizes the design of various chip sizes to ensure good electrical interconnection performance while having good stress performance.

[0045] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed in the present invention shall still be covered by the claims of the present invention.

[0046] In the description herein, many specific details, such as examples of components and / or methods, are provided to provide a complete understanding of the embodiments of the present invention. However, those skilled in the art will recognize that embodiments of the present invention may be practiced without one or more specific details or by other devices, systems, components, methods, components, materials, parts, etc. In other cases, well-known structures, materials, or operations are not specifically shown or described in detail to avoid obscuring aspects of the embodiments of the present invention.

Claims

1. A chip packaging structure, characterized in that: include: a substrate, the substrate comprising a first welding area and a second welding area; A power chip, wherein a first terminal array is provided on a first side of the power chip, and the first terminal array is electrically connected to the first welding area through flip-chip welding; A control driving chip is fixed to the second side of the power chip, the second side is the side facing away from the first side; a first pin is provided on the side of the control driving chip facing away from the power chip, the first pin is electrically connected to the second welding area through a first bonding wire.

2. The chip packaging structure according to claim 1, characterized in that: A third welding area is provided on the substrate, a second terminal array is provided on the first side of the power chip, a second pin is provided on the side of the control drive chip facing away from the power chip, the second pin is electrically connected to the third welding area through a second bonding wire, and the second terminal array is electrically connected to the third welding area through flip-chip welding, so that the second pin is electrically connected to the second terminal array.

3. The chip packaging structure according to claim 1, characterized in that: The first terminal array includes an input terminal and an output terminal. The first side of the power chip is provided with a first redistribution layer and a second redistribution layer. The input terminals are arranged into a plurality of first column units through the first redistribution layer. The output terminals are arranged into a plurality of second column units through the second redistribution layer. The first column units and the second column units are arranged alternately.

4. The chip packaging structure according to claim 3, characterized in that: The first welding area includes a first sub-welding area and a second sub-welding area. The distribution pattern between the first sub-welding area and the second sub-welding area corresponds to the distribution pattern between the first column units and the second column units. The first column units are electrically connected to the first sub-welding area, and the second column units are electrically connected to the second sub-welding area.

5. The chip packaging structure according to claim 3, characterized in that: A passivation layer and a protection layer are sequentially disposed on the first side of the power chip, and the first redistribution layer and the second redistribution layer are disposed on the passivation layer and covered in the protection layer.

6. The chip packaging structure according to claim 5, characterized in that: The input terminal and the output terminal are respectively provided with metal bumps, and the metal bumps are respectively protruded from the first redistribution layer and the second redistribution layer to the outside of the protection layer.

7. The chip packaging structure according to claim 3, characterized in that: The distance between the adjacent first redistribution layers and the second redistribution layers is 20-50 μm.

8. The chip packaging structure according to claim 4, characterized in that: The distance between the adjacent first sub-welding regions and the second sub-welding regions is 40-60 μm.

9. The chip packaging structure according to claim 1, characterized in that: The substrate includes an insulating base, the first welding area and the second welding area are arranged on a first side of the insulating base, an I / O terminal is arranged on the second side of the insulating base, an internal conductor is arranged inside the insulating base, and the first welding area and the second welding area are electrically connected to the I / O terminal through the internal conductor respectively.

10. The chip packaging structure according to claim 9, characterized in that: The internal conductors are arranged in multiple layers along the thickness direction of the insulating substrate, and the internal conductors in each layer are interconnected.

11. The chip packaging structure according to claim 9, characterized in that: The thickness of the first welding area and / or the second welding area and / or the inner conductor is 25-50 μm.

12. The chip packaging structure according to claim 10, characterized in that: The distance between the inner conductors of two adjacent layers is 30-50 μm.

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