Chip packaging structure
By opening channels on the substrate and installing the chip side into the channel, the electrical connection between the chip and the substrate is solved, and the problem of complex packaging processes in the prior art is achieved, and a smaller packaging volume and a simpler process flow is achieved.
Patent Information
- Application Number
- CN202421134136.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-22
- Publication Date
- 2025-02-11
- Estimated Expiration
- 2034-05-22
AI Technical Summary
When the existing chip packaging structure improves the functional integration, the production process is complicated and it is difficult to meet the requirements of lightness, thinness and shortness.
A chip packaging structure is designed. By opening a channel on the substrate, the chip side with elastic metal bumps on the front is installed into the channel, and the electrical connection between the chip and the substrate is realized, and the process flow is simplified.
This packaging structure reduces the packaging volume and makes the process simpler, and does not need to bury the chip inside the substrate, reducing the complexity of the substrate design.
Smart Images
Figure CN222462918U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of packaging, in particular to a chip packaging structure. Background Art
[0002] In response to the requirement of semiconductor packaging to be light, thin and short, current packaging structures are working towards two directions: 1. Reducing the package size; 2. Functional integration. As for reducing the package size, there is limited room for improvement, so the packaging industry focuses on improving functional integration, that is, embedding some functional components or other electronic devices into the substrate to expand the functional integration of the entire package. However, due to the complex design of the substrate circuit, the manufacturing process is more complex and the process requirements are relatively high. Utility Model Content
[0003] The utility model aims to overcome the problem of complicated manufacturing process for improving functional integration in the prior art and provides a chip packaging structure.
[0004] In order to achieve the above object, the utility model provides a chip packaging structure, including:
[0005] a substrate having a channel;
[0006] A first chip, wherein the first chip is fixed in the channel, the back side of the first chip is connected to the first surface area of the inner wall of the channel, and the front side of the first chip is connected to the second surface area of the inner wall of the channel via a first elastic metal bump, so that the first chip is electrically connected to the substrate via the first elastic metal bump; wherein the front side of the first chip is opposite to the back side of the first chip, and the first surface area of the inner wall of the channel is opposite to the second surface area of the inner wall of the channel.
[0007] As an implementation method, the first elastic metal protrusion is spring-shaped.
[0008] As an implementable embodiment, it also includes:
[0009] A second chip, wherein the second chip is fixed in the channel, and the back side of the first chip is connected to the first surface area of the inner wall of the channel through the second chip; wherein the front side of the second chip is opposite to the back side of the second chip, and the back side of the second chip is connected to the back side of the first chip, and the front side of the second chip is electrically connected to the second surface area of the inner wall of the channel through a second elastic metal bump, thereby realizing that the second chip is electrically connected to the substrate through the second elastic metal bump.
[0010] As an implementation method, the second elastic metal protrusion is spring-shaped.
[0011] As an implementation method, the back side of the second chip is connected to the back side of the first chip, including: the back side of the second chip is connected to the back side of the first chip via a first adhesive layer.
[0012] As an implementation method, the channel is a groove or a through hole.
[0013] As an implementation method, the channel is a square channel.
[0014] As an implementation method, the channel penetrates the side surface of the substrate.
[0015] As an implementation method, the back side of the first chip is connected to the inner wall of one side of the groove, including: the back side of the first chip is in contact with a first surface area of the inner wall of the channel to achieve connection.
[0016] As an implementation method, the substrate surface further has a third chip and / or passive components.
[0017] Beneficial effects of the utility model:
[0018] The utility model discloses a chip packaging structure, wherein a substrate is provided with a channel, and a first chip side having a first elastic metal bump on the front is loaded into the channel, and the first chip is electrically connected to the substrate through the first elastic metal bump, thereby reducing the packaging volume and simplifying the process. In the chip packaging structure provided by the utility model, the first elastic metal bump can elastically fix the chip in the groove of the substrate without adding other materials. In the chip packaging structure provided by the utility model, there is no need to integrate the chip inside the substrate in an embedded manner, and only the chip side is loaded into the groove of the substrate, thereby reducing the complexity of the substrate design. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1-Figure 4 A schematic diagram of a chip packaging structure provided by some embodiments of the present utility model. DETAILED DESCRIPTION
[0020] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
[0021] It should be understood that as used herein, terms such as "first", "second" and "third" describe various elements, components, regions, layers and / or sections, which should not be limited by these terms. These terms may only be used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. For example, terms such as "first", "second" and "third" do not imply order or sequence when used herein unless the context clearly indicates. For ease of description, spatially relative terms such as "below" may be used herein to describe the relationship between an element or feature and other elements or features as shown in the accompanying drawings. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientations shown in the accompanying drawings.
[0022] In this application document, unless otherwise clearly specified and limited, the terms "connected", "connection", etc. should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0023] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the utility model. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory. It should be noted that the terms "including" and "having" and their variations involved in this application are intended to cover non-exclusive inclusions.
[0024] See also Figure 1-Figure 4 Some embodiments of the present invention provide a chip packaging structure, including:
[0025] A substrate 100, wherein the substrate 100 has a channel 101;
[0026] A first chip 210, wherein the first chip 210 is fixed in the channel 101, the back side 2101 of the first chip is connected to the first surface area 112 of the inner wall of the channel, and the front side 2102 of the first chip is connected to the second surface area 111 of the inner wall of the channel via a first elastic metal bump 211, so that the first chip 210 is electrically connected to the substrate 100 via the first elastic metal bump 211; wherein the front side 2102 of the first chip and the back side 2101 of the first chip are opposite to each other, and the first surface area 112 of the inner wall of the channel and the second surface area 111 of the inner wall of the channel are opposite to each other.
[0027] The substrate 100 provided by the present invention is provided with a channel 101 , and the first chip 210 with a first elastic metal bump 211 on the front side can be side-mounted in the channel 101 , thereby reducing the packaging volume and making the process simpler.
[0028] In some embodiments, the substrate 100 may be a resin substrate, a ceramic substrate, a glass substrate, a silicon substrate, or a printed circuit board (PCB).
[0029] In some embodiments, see Figure 1 and Figure 2 The channel 101 may be a through hole that penetrates the thickness direction of the substrate 100, see Figure 3 and Figure 4 , the channel 101 may also be a groove located on the surface of the substrate 100. In some embodiments, the inner wall of the channel 101 is perpendicular to the surface of the substrate 100 outside the channel 101. In some embodiments, the channel 101 is a square channel. In some embodiments, the length and depth of the channel 101 may be set according to the size of the first chip 210. In one embodiment, the channel 101 runs through the side of the substrate 100.
[0030] In some embodiments, the first chip 210 may be a logic chip and a memory chip. In one embodiment, the logic chip may include a gate array, a cell substrate array, an embedded array, a structured application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a complex programmable logic device (CPLD), a central processing unit (CPU), a microprocessing unit (MPU), a microcontroller unit (MCU), a logic integrated circuit (IC), an application processor (AP), a display driver IC (DDI), a radio frequency (RF) chip, a power chip, or a complementary metal oxide semiconductor (CMOS) image sensor. In one embodiment, the memory chip may include a volatile memory chip (such as a dynamic random access memory (DRAM) or a static RAM (SRAM) or a non-volatile memory chip (such as a flash memory (F l ash), a phase change RAM (PCRAM), a magnetoresistive RAM (MRAM), a ferroelectric RAM (FeRAM), or a resistive RAM (ReRAM)).
[0031] In some embodiments, the front side 2102 of the first chip has a first elastic metal bump 211, the second surface area 111 of the inner wall of the channel has a second metal pad 110, and the first chip 210 is welded to the surface of the second metal pad 110 through the first elastic metal bump 211, so as to realize electrical connection between the first chip 210 and the substrate 100. In some embodiments, the first chip 210 having the first elastic metal bump 211 on the front side can be placed in the channel 101, and then the first elastic metal bump 211 and the second metal pad 120 can be welded to realize fixing the first chip 210 in the channel 101.
[0032] In some embodiments, see Figure 1 and Figure 3, the back side 2101 of the first chip and the first surface area 112 of the inner wall of the channel are connected, including: the back side 2101 of the first chip and the first surface area 112 of the inner wall of the channel are in contact to achieve connection. In some embodiments, by inserting the first chip 210 side into the channel 101, the first chip 210 can be stuck in the substrate 110 through the first elastic metal bump 211, and the first chip 210 is fixed in the channel 101 by the elastic force of the first elastic metal bump 211, and no other adhesive is required between the back side 2101 of the first chip and the first surface area 112 of the inner wall of the channel; but in other embodiments, adhesive can also be used for further fixing according to needs. In some embodiments, the first elastic metal bump 211 is spring-shaped or other elastic shapes. In some embodiments, the material of the first elastic metal bump 211 can be one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, and silver.
[0033] In some embodiments, see Figure 2 and Figure 4 A chip packaging structure provided by some embodiments of the utility model also includes: a second chip 220, the second chip 220 is fixed in the channel 101, and the back side 2101 of the first chip is connected to the first surface area 112 of the inner wall of the channel through the second chip 220; wherein the front side 2202 of the second chip is relative to the back side 2201 of the second chip: the back side 2201 of the second chip is connected to the back side 2101 of the first chip, and the front side 2202 of the second chip is electrically connected to the second surface area of the inner wall of the channel 101 through the second elastic metal bump 221, so that the second chip 220 is electrically connected to the substrate 100 through the second elastic metal bump 221.
[0034] In some embodiments, the second chip 220 may be a logic chip and a memory chip. In one embodiment, the logic chip may include a gate array, a cell substrate array, an embedded array, a structured application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a complex programmable logic device (CPLD), a central processing unit (CPU), a microprocessing unit (MPU), a microcontroller unit (MCU), a logic integrated circuit (IC), an application processor (AP), a display driver IC (DDI), a radio frequency (RF) chip, a power chip, or a complementary metal oxide semiconductor (CMOS) image sensor. In one embodiment, the memory chip may include a volatile memory chip (such as a dynamic random access memory (DRAM) or a static RAM (SRAM) or a non-volatile memory chip (such as a flash memory (F l ash), a phase change RAM (PCRAM), a magnetoresistive RAM (MRAM), a ferroelectric RAM (FeRAM), or a resistive RAM (ReRAM)).
[0035] In some embodiments, see Figure 2 and Figure 4 , the back side 2201 of the second chip and the back side 2101 of the first chip are connected, including: the back side 2201 of the second chip and the back side 2101 of the first chip are connected through the first adhesive layer 222. In some embodiments, the back side 2201 of the second chip and the back side 2101 of the first chip can be firstly pasted through the first adhesive layer 222, and then the first chip 210 and the second chip 220 are placed in the channel 101, and then the first elastic metal bump 211 and the second metal pad 110 are welded, and the second elastic metal bump 221 and the first metal pad 120 are welded, so as to fix the first chip 210 and the second chip 220 in the channel 101.
[0036] In some embodiments, the front side 2202 of the second chip has a second elastic metal bump 221, the first surface area 112 of the inner wall of the channel has a second metal pad 120, and the second chip 220 is welded on the surface of the second metal pad 120 through the second elastic metal bump 221, so that the second chip 220 and the substrate 100 are electrically connected. In some embodiments, the second elastic metal bump 221 is spring-shaped or has other elastic shapes. In some embodiments, the material of the second elastic metal bump 221 can be one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, and silver.
[0037] In some embodiments, the surface of the substrate 100 also has a third chip 230 and / or a passive device 240. In some embodiments, the third chip 230 can be a logic chip and a memory chip. In one embodiment, the logic chip can include a gate array, a cell substrate array, an embedded array, a structured application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a complex programmable logic device (CPLD), a central processing unit (CPU), a microprocessing unit (MPU), a microcontroller unit (MCU), a logic integrated circuit (IC), an application processor (AP), a display driver IC (DDI), a radio frequency (RF) chip, a power chip or a complementary metal oxide semiconductor (CMOS) image sensor. In one embodiment, the memory chip can include a volatile memory chip (such as a dynamic random access memory (DRAM) or a static RAM (SRAM) or a non-volatile memory chip (such as a flash memory (F l ash), a phase change RAM (PCRAM), a magnetoresistive RAM (MRAM), a ferroelectric RAM (FeRAM) or a resistive RAM (ReRAM)). In some embodiments, the passive device 240 can be one or more of a resistor, a capacitor, and an inductor.
[0038] In some embodiments, the substrate 100 further has a molding compound 300 on its surface. The molding compound 300 is located on the surface of the substrate 100 and molds the first chip 210, the second chip 220, the third chip 230 and the passive device 240. Figure 1 and Figure 2 The side bottom surfaces of the first chip 210 and the second chip 220 are exposed to the molding compound 300. In some embodiments, the molding compound 300 may be made of epoxy resin, polyimide resin, benzocyclobutene resin or polybenzoxazole resin, and the forming process may be an injection molding process or a transfer molding process.
[0039] Although the utility model has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the utility model. Any technical personnel in this field can make possible changes and modifications to the technical solution of the utility model by using the methods and technical contents disclosed above without departing from the spirit and scope of the utility model. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the utility model without departing from the content of the technical solution of the utility model are within the protection scope of the technical solution of the utility model.
Claims
1. A chip packaging structure, characterized in that: include: a substrate having a channel; A first chip, wherein the first chip is fixed in the channel, the back side of the first chip is connected to the first surface area of the inner wall of the channel, and the front side of the first chip is connected to the second surface area of the inner wall of the channel via a first elastic metal bump, so that the first chip is electrically connected to the substrate via the first elastic metal bump; wherein the front side of the first chip is opposite to the back side of the first chip, and the first surface area of the inner wall of the channel is opposite to the second surface area of the inner wall of the channel.
2. The chip packaging structure according to claim 1, characterized in that: The first elastic metal protrusion is spring-shaped.
3. The chip packaging structure according to claim 1, characterized in that: Also includes: A second chip, wherein the second chip is fixed in the channel, and the back side of the first chip is connected to the first surface area of the inner wall of the channel through the second chip; wherein the front side of the second chip is opposite to the back side of the second chip, and the back side of the second chip is connected to the back side of the first chip, and the front side of the second chip is electrically connected to the second surface area of the inner wall of the channel through a second elastic metal bump, thereby realizing that the second chip is electrically connected to the substrate through the second elastic metal bump.
4. The chip packaging structure according to claim 3, characterized in that: The second elastic metal protrusion is spring-shaped.
5. The chip packaging structure according to claim 3, characterized in that: The back side of the second chip is connected to the back side of the first chip, including: the back side of the second chip is connected to the back side of the first chip via a first adhesive layer.
6. The chip packaging structure according to claim 1, characterized in that: The channel is a groove or a through hole.
7. The chip packaging structure according to claim 1, characterized in that: The channel is a square channel.
8. The chip packaging structure according to claim 1, characterized in that: The channel penetrates through a side surface of the substrate.
9. The chip packaging structure according to claim 1, characterized in that: The back side of the first chip and the first surface area of the inner wall of the channel are connected, including: the back side of the first chip and the first surface area of the inner wall of the channel are in contact to achieve connection.
10. The chip packaging structure according to claim 1, characterized in that: The substrate surface also has a third chip and / or passive components.