Control circuit of expansion key
Through the combination of logic chip and interrupt control module, the problems of low efficiency and small number of extended button control circuits in the prior art are solved, and efficient control of multiple buttons and improved system efficiency are achieved.
Patent Information
- Application Number
- CN202421223311.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-30
- Publication Date
- 2025-02-11
- Estimated Expiration
- 2034-05-30
AI Technical Summary
The existing control circuit of extended buttons has problems such as low system efficiency, small number of drive buttons, and high requirements for the number of MCU GPIOs.
Using a combination of logic chips and interrupt control modules, an AND gate logic circuit is built through logic chips such as 74HC08, 74HC21, 74HC595 and 74HC165 to control multiple keys, and to use interrupt mechanisms to improve system efficiency.
It significantly expands the number of keys, improves system efficiency, enhances the interactivity and functionality of the device, and optimizes system performance and power consumption.
Smart Images
Figure CN222464597U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of electronic information, in particular to a control circuit for extending keys. Background Art
[0002] At present, the control circuit methods of extended keys mainly include integrated circuit methods, such as TM1628, TM1629 of Tianwei Semiconductor, GN1628, GN1629 of Jingxin Semiconductor, etc.; there are solutions that use GPIO to directly drive the extended keys, which is a good choice when the GPIO of the microcontroller or core board is relatively sufficient and the system timeliness requirements are not too high; there are also circuit solutions driven by logic chips, such as: 74HC595, 74HCT595 and other chips.
[0003] The driver control of the buttons is a relatively integrated chip with a relatively high price. The SPI bus protocol communication uses the system timer polling method, which will lead to low system efficiency and a relatively small number of driven buttons. Directly using GPIO to drive the extended buttons requires a lot of GPIOs of the MCU or core CPU module. Using the logic chip to expand the button circuit, this solution uses the SPI bus protocol communication like the first solution, and will encounter the same problem.
[0004] Therefore, it is necessary to propose a new technical solution to improve the above technical problems. Utility Model Content
[0005] In view of the defects in the prior art, the purpose of the utility model is to provide a control circuit for expanding keys.
[0006] According to a control circuit of an extended key provided by the utility model, the control circuit includes: a logic chip, multiple keys and an interrupt control module, wherein the logic chip is electrically connected to the multiple keys; the logic chip includes an AND gate logic circuit, and the AND gate logic circuit is electrically connected to the multiple keys and the interrupt control module respectively.
[0007] Preferably, the multiple keys include one or more matrix keys and / or one or more individual keys; the matrix keys are 4*4 matrix keys controlled by K1-K8, and the individual keys are individual keys controlled by KEY1-KEY4 and K9.
[0008] Preferably, the logic chip includes a 74HC08 AND gate logic circuit and a 74HC21 AND gate logic circuit, and a 74HC595 logic chip and a 74HC165 logic chip.
[0009] Preferably, the logic chip includes a 74HC165 logic chip of U1, a U2A 74HC21 AND gate logic chip of U2, a U2B 74HC21 AND gate logic chip, a U3A 74HC08 AND gate logic chip of U3, a U3B 74HC08 AND gate logic chip, a U3C 74HC08 AND gate logic chip, a U4 74HC165 logic chip, and a U5 74HC595 logic chip; the P0-P3 pins of the 74HC165 logic chip of U1 are respectively connected to the P0-P3 pins of the U2A 74HC08 AND gate logic chip, the U3B 74HC08 AND gate logic chip, the U3C 74HC08 AND gate logic chip, the U4 74HC165 logic chip, and the U5 74HC595 logic chip; The 74HC21 is connected to the A1, B1, C1, and D1 pins of the gate logic chip; the P4-P7 and SER pins of the 74HC165 logic chip of U1 are grounded; the CLK1 and CLK2 pins of the 74HC165 logic chip of U1 are respectively connected to the SRCLK and RCLK pins of the 74HC595 logic chip of U5; the high-level PL pin of the 74HC165 logic chip of U1 is connected to the high-level PL pin of the 74HC165 logic chip of U4; the low-level Q7 pin of the 74HC165 logic chip of U1 is connected to the core board and to the KeySO1 pin of the core board; the VCC pin of the 74HC165 logic chip of U1 is respectively connected to an external power supply and capacitor C5; the GND pin of the 74HC165 logic chip of U1 is connected to the other end of capacitor C5 and is grounded.
[0010] Preferably, the Y1 pin of the U2A 74HC21 AND gate logic chip is connected to the A1 pin of the U3A 74HC08 AND gate logic chip; the G pin of the U2A 74HC21 AND gate logic chip is grounded; and the V pin of the U2A 74HC21 AND gate logic chip is connected to an external power supply.
[0011] Preferably, the A2, B2, C2, D2 pins of the U2B 74HC21 AND gate logic chip are respectively connected to the P0-P3 pins of the 74HC165 logic chip of U4; the Y2 pin of the U2B 74HC21 AND gate logic chip is connected to the B1 pin of the U3A 74HC08 AND gate logic chip.
[0012] Preferably, the Y1 pin of the U3A 74HC08 AND gate logic chip is connected to the A3 pin of the U3C 74HC08 AND gate logic chip; the G pin of the U3A 74HC08 AND gate logic chip is grounded; the V pin of the U3A 74HC08 AND gate logic chip is connected to an external power supply;
[0013] The A2 and B2 pins of the U3B 74HC08 AND gate logic chip are connected to the P4 pin of the U4 74HC165 logic chip; the Y2 pin of the U3B 74HC08 AND gate logic chip is connected to the B3 pin of the U3C 74HC08 AND gate logic chip;
[0014] The Y3 pin of the U3C 74HC08 AND gate logic chip is connected to the KeyINT of the core board and is connected to a capacitor C6, and the other end of the capacitor C6 is grounded.
[0015] Preferably, the P5-P7 and SER pins of the 74HC165 logic chip of the U4 are grounded; the CLK1 pin of the 74HC165 logic chip of the U4 is connected to the KeySCLK pin of the core board; the CLK2 pin of the 74HC165 logic chip of the U4 is connected to the KeyCS pin of the core board; the high-level PL pin of the 74HC165 logic chip of the U4 is respectively connected to the collector of the resistor R1 and the transistor Q1; the other end of the resistor R1 is connected to an external power supply; the The emitter is grounded, and the base of the transistor Q1 is respectively connected to resistors R2 and R3, the other end of the resistor R3 is grounded, and the other end of the resistor R2 is connected to the KeyCS pin of the core board; the low-level Q7 pin of the 74HC165 logic chip of U4 is connected to the KeySO2 pin of the core board; the VCC pin of the 74HC165 logic chip of U4 is respectively connected to an external power supply and capacitor C7, and the other end of the capacitor C7 is grounded; the GND pin of the 74HC165 logic chip of U4 is grounded.
[0016] Preferably, the O0-O3 pins of the 74HC595 logic chip of the U5 are respectively connected to the pins 6 to 9 of the Header16 of the P1, and the O0-O3 pins of the 74HC595 logic chip of the U5 are respectively connected to the resistor RM5, and the other end of each resistor RM5 is grounded; the SER pin of the 74HC595 logic chip of the U5 is connected to the KeySSI pin of the core board; the SRCLK pin of the 74HC595 logic chip of the U5 is connected to the KeySCLK pin of the core board; the 74HC59 The high-level SRCLR pin of the 74HC595 logic chip of U5 is respectively connected to a capacitor C8 and a resistor R5, the other end of the capacitor C8 is grounded, and the other end of the resistor R5 is connected to an external power supply; the RCLK pin of the 74HC595 logic chip of U5 is connected to the KeyCS pin of the core board; the E pin of the 74HC595 logic chip of U5 is grounded; the VCC pin of the 74HC595 logic chip of U5 is respectively connected to an external power supply and a capacitor C10, and the other end of the capacitor C10 is grounded; the GND pin of the 74HC595 logic chip of U5 is grounded.
[0017] Preferably, pin 1 of the Header 16 of P1 is grounded; pins 2 to 5 of the Header 16 of P1 are respectively connected to pins P0 to P3 of the 74HC165 logic chip of U1, and pins 2 to 5 of the Header 16 of P1 are respectively connected to resistors RM3, and the other end of each resistor RM5 is connected to an external power supply; pin 10 of the Header 16 of P1 is respectively connected to resistors R6, R4 and capacitor C9, the other end of the resistor R6 is connected to an external power supply, and the other end of the resistor R4 is connected to the 74HC165 logic chip of U4. The P0 pin of the logic chip of U4 is connected; the other end of the capacitor C9 is grounded; the pin 11 of the Header16 of P1 is respectively connected to the resistor RM2, the capacitor CM1 and the resistor RM4; the other end of the resistor RM2 is connected to the external power supply; the other end of the capacitor CM1 is grounded; the other end of the resistor RM4 is connected to the P1 pin of the 74HC165 logic chip of U4; the pin 12 of the Header16 of P1 is respectively connected to the resistor RM2, the capacitor CM1 and the resistor RM4, and the other end of the resistor RM2 is connected to the external power supply; the capacitor CM1 The other end of the resistor RM4 is grounded; the other end of the resistor RM4 is connected to the P2 pin of the 74HC165 logic chip of U4; the pin 13 of the Header16 of P1 is respectively connected to the resistor RM2, the capacitor CM1 and the resistor RM4, and the other end of the resistor RM2 is connected to an external power supply; the other end of the capacitor CM1 is grounded; the other end of the resistor RM4 is connected to the P3 pin of the 74HC165 logic chip of U4; the pin 14 of the Header16 of P1 is respectively connected to the resistor RM2, the capacitor CM1 and the resistor RM4, and the other end of the resistor RM2 is connected to the ... One end is connected to an external power supply; the other end of the capacitor CM1 is grounded; the other end of the resistor RM4 is connected to the P4 pin of the 74HC165 logic chip of U4; the pin 15 of the Header16 of P1 is respectively connected to the resistor R7, the capacitor C11 and the resistor R8, the other end of the resistor R7 is grounded, the other end of the capacitor C11 is grounded, and the other end of the resistor R8 is connected to the WKUP output terminal; the pin 16 of the Header16 of P1 is connected to the resistor R9, and the other end of the resistor R9 is connected to the POWER_IN input terminal.
[0018] Compared with the prior art, the utility model has the following beneficial effects:
[0019] 1. Significantly expand the number of keys: Under limited GPIO resources, through the combination of logic chips and interrupt control modules, the utility model can significantly expand the number of keys, so that more function keys can be supported under limited resources, thereby enhancing the interactivity and functionality of the device;
[0020] 2. Improve system efficiency: Traditional key detection methods, such as polling, will continuously scan the status of all keys, and will occupy system resources even if no key is pressed. The utility model adopts an interrupt mechanism, and only when a key is pressed will the interrupt service program be triggered to scan and process the keys, thereby greatly reducing the occupation of system resources and improving the operating efficiency of the system;
[0021] 3. Enhance the reliability of key triggering: Through reasonable logic circuit design, the utility model can stably and reliably detect the state change of the key and trigger the interrupt signal, avoiding erroneous operation caused by signal interference or jitter, and improving the accuracy of key triggering;
[0022] 4. Flexibility and configurability: The utility model can flexibly adjust the number and function of buttons according to actual needs, which can be achieved by simply modifying the logic circuit and the corresponding software program. This flexibility and configurability make the utility model suitable for various types of equipment and application scenarios;
[0023] 5. Optimize system performance: Due to the use of interrupt mechanism and logic chip control method, the utility model can quickly respond and process when a key is pressed, thereby optimizing system performance. At the same time, due to reducing unnecessary system resource usage, the utility model can also reduce the power consumption and heat generation of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Other features, objects and advantages of the present invention will become more apparent by reading the detailed description of non-limiting embodiments with reference to the following drawings:
[0025] Figure 1 A circuit diagram of the utility model;
[0026] Figure 2 This is a button connection diagram of the utility model. DETAILED DESCRIPTION
[0027] The utility model is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the utility model, but do not limit the utility model in any form. It should be pointed out that for those of ordinary skill in the art, several changes and improvements can be made without departing from the concept of the utility model. These all belong to the protection scope of the utility model.
[0028] Embodiment 1:
[0029] Reference Figure 1 and Figure 2According to a control circuit of an extended key provided by the utility model, the control circuit includes: a logic chip, multiple keys and an interrupt control module, wherein the logic chip is electrically connected to the multiple keys; the logic chip includes an AND gate logic circuit, and the AND gate logic circuit is electrically connected to the multiple keys and the interrupt control module respectively.
[0030] The multiple keys include one or more matrix keys and / or one or more individual keys; the matrix keys are 4*4 matrix keys controlled by K1-K8, and the individual keys are individual keys controlled by KEY1-KEY4 and K9.
[0031] The logic chips include 74HC08 AND gate logic circuit and 74HC21 AND gate logic circuit, as well as 74HC595 logic chip and 74HC165 logic chip.
[0032] The logic chips include a 74HC165 logic chip of U1, a 74HC21 AND gate logic chip of U2A of U2, a 74HC21 AND gate logic chip of U2B, a 74HC08 AND gate logic chip of U3A of U3, a 74HC08 AND gate logic chip of U3B, a 74HC08 AND gate logic chip of U3C, a 74HC165 logic chip of U4, and a 74HC595 logic chip of U5; the P0-P3 pins of the 74HC165 logic chip of U1 are respectively connected to the P0-P3 pins of the 74HC165 logic chip of U2A The 74HC21 is connected to the A1, B1, C1, and D1 pins of the gate logic chip; the P4-P7 and SER pins of the 74HC165 logic chip of U1 are grounded; the CLK1 and CLK2 pins of the 74HC165 logic chip of U1 are respectively connected to the SRCLK and RCLK pins of the 74HC595 logic chip of U5; the high-level PL pin of the 74HC165 logic chip of U1 is connected to the high-level PL pin of the 74HC165 logic chip of U4; the low-level Q7 pin of the 74HC165 logic chip of U1 is connected to the core board and to the KeySO1 pin of the core board; the VCC pin of the 74HC165 logic chip of U1 is respectively connected to an external power supply and capacitor C5; the GND pin of the 74HC165 logic chip of U1 is connected to the other end of capacitor C5 and is grounded.
[0033] The Y1 pin of the U2A 74HC21 AND gate logic chip is connected to the A1 pin of the U3A 74HC08 AND gate logic chip; the G pin of the U2A 74HC21 AND gate logic chip is grounded; and the V pin of the U2A 74HC21 AND gate logic chip is connected to an external power supply.
[0034] The A2, B2, C2, and D2 pins of the U2B 74HC21 AND gate logic chip are respectively connected to the P0-P3 pins of the U4 74HC165 logic chip; the Y2 pin of the U2B 74HC21 AND gate logic chip is connected to the B1 pin of the U3A 74HC08 AND gate logic chip.
[0035] The Y1 pin of the U3A 74HC08 AND gate logic chip is connected to the A3 pin of the U3C 74HC08 AND gate logic chip; the G pin of the U3A 74HC08 AND gate logic chip is grounded; the V pin of the U3A 74HC08 AND gate logic chip is connected to an external power supply; the A2 and B2 pins of the U3B 74HC08 AND gate logic chip are connected to the P4 pin of the U4 74HC165 logic chip; the Y2 pin of the U3B 74HC08 AND gate logic chip is connected to the B3 pin of the U3C 74HC08 AND gate logic chip; the Y3 pin of the U3C 74HC08 AND gate logic chip is connected to the KeyINT of the core board, and is connected to a capacitor C6, and the other end of the capacitor C6 is grounded.
[0036] The P5-P7 and SER pins of the 74HC165 logic chip of U4 are grounded; the CLK1 pin of the 74HC165 logic chip of U4 is connected to the KeySCLK pin of the core board; the CLK2 pin of the 74HC165 logic chip of U4 is connected to the KeyCS pin of the core board; the high-level PL pin of the 74HC165 logic chip of U4 is respectively connected to the collector of the resistor R1 and the transistor Q1; the other end of the resistor R1 is connected to an external power supply; the emitter of the transistor Q1 is connected to the external power supply; Grounded, the base of the transistor Q1 is respectively connected to a resistor R2 and a resistor R3, the other end of the resistor R3 is grounded, and the other end of the resistor R2 is connected to the KeyCS pin of the core board; the low-level Q7 pin of the 74HC165 logic chip of U4 is connected to the KeySO2 pin of the core board; the VCC pin of the 74HC165 logic chip of U4 is respectively connected to an external power supply and a capacitor C7, and the other end of the capacitor C7 is grounded; the GND pin of the 74HC165 logic chip of U4 is grounded.
[0037] The O0-O3 pins of the 74HC595 logic chip of U5 are respectively connected to the pins 6 to 9 of the Header16 of P1, and the O0-O3 pins of the 74HC595 logic chip of U5 are respectively connected to the resistor RM5, and the other end of each resistor RM5 is grounded; the SER pin of the 74HC595 logic chip of U5 is connected to the KeySSI pin of the core board; the SRCLK pin of the 74HC595 logic chip of U5 is connected to the KeySCLK pin of the core board; the 74HC595 logic chip of U5 is connected to the KeySCLK pin of the core board; The high-level SRCLR pin of the chip is respectively connected to a capacitor C8 and a resistor R5, the other end of the capacitor C8 is grounded, and the other end of the resistor R5 is connected to an external power supply; the RCLK pin of the 74HC595 logic chip of the U5 is connected to the KeyCS pin of the core board; the E pin of the 74HC595 logic chip of the U5 is grounded; the VCC pin of the 74HC595 logic chip of the U5 is respectively connected to an external power supply and a capacitor C10, and the other end of the capacitor C10 is grounded; the GND pin of the 74HC595 logic chip of the U5 is grounded.
[0038] Pin 1 of Header 16 of P1 is grounded; Pin 2 to Pin 5 of Header 16 of P1 are respectively connected to Pins P0-P3 of 74HC165 logic chip of U1, and Pin 2 to Pin 5 of Header 16 of P1 are respectively connected to resistor RM3, and the other end of each resistor RM5 is connected to an external power supply; Pin 10 of Header 16 of P1 is respectively connected to resistor R6, resistor R4 and capacitor C9, the other end of resistor R6 is connected to an external power supply, and the other end of resistor R4 is connected to the 74HC165 logic chip of U4. The P0 pin is connected; the other end of the capacitor C9 is grounded; the pin 11 of the Header16 of P1 is respectively connected to the resistor RM2, the capacitor CM1 and the resistor RM4; the other end of the resistor RM2 is connected to an external power supply; the other end of the capacitor CM1 is grounded; the other end of the resistor RM4 is connected to the P1 pin of the 74HC165 logic chip of U4; the pin 12 of the Header16 of P1 is respectively connected to the resistor RM2, the capacitor CM1 and the resistor RM4, and the other end of the resistor RM2 is connected to an external power supply; the other end of the capacitor CM1 The other end of the resistor RM4 is connected to the P2 pin of the 74HC165 logic chip of U4; the pin 13 of the Header16 of P1 is respectively connected to the resistor RM2, the capacitor CM1 and the resistor RM4, and the other end of the resistor RM2 is connected to the external power supply; the other end of the capacitor CM1 is grounded; the other end of the resistor RM4 is connected to the P3 pin of the 74HC165 logic chip of U4; the pin 14 ... The end is connected to an external power supply; the other end of the capacitor CM1 is grounded; the other end of the resistor RM4 is connected to the P4 pin of the 74HC165 logic chip of U4; the pin 15 of the Header16 of P1 is respectively connected to the resistor R7, the capacitor C11 and the resistor R8, the other end of the resistor R7 is grounded, the other end of the capacitor C11 is grounded, and the other end of the resistor R8 is connected to the WKUP output terminal; the pin 16 of the Header16 of P1 is connected to the resistor R9, and the other end of the resistor R9 is connected to the POWER_IN input terminal.
[0039] Embodiment 2:
[0040] The principle of the utility model is to use interrupt and logic chip to design the extended key control circuit. Figure 1As shown, K1-K8, K1-K4, K9, KEY1-KEY4, KeyINT, KeySCLK, KeyCS, KeySSI, KeySO1, KeySO2 are network labels, 74HC08 and 74HC21 are AND gate logic circuits, the level conversion of 74HC08 and 74HC21 is about 500ns, and about 1us after cascading, which is the response time of key interrupt. K1-K4, K9, KEY1-KEY4 are high level by default, and after the AND gate, the interrupt output pin KeyINT is also high level. In this design, K1-K8 controls the 4*4 matrix keys, and KEY1-KEY4 and K9 control individual keys. Figure 2 , when any key in the key diagram is pressed, KeyINT becomes low level, an interrupt will be triggered, and the system will call the key scanning program. The scanning program is divided into 4*4 matrix key drivers, which control the key drivers separately. A single key trigger can be directly obtained by U4's 74HC165 through the SPI bus to execute the corresponding function block. The matrix keys need to be controlled by 74HC595 and 74HC165 together. In this way, the 6 GPIOs of the core board can realize the function control of 21 keys, and the execution takes up less system time. If no key is pressed, the key interrupt will not be triggered, and the system can efficiently execute other functions. In the current situation where GPIO is insufficient in the secondary development of the core board, more function keys can be expanded. On the basis of the above, the key trigger uses interrupts, the system efficiency is high, and the key trigger is reliable.
[0041] Those skilled in the art may understand this embodiment as a more specific description of Embodiment 1.
[0042] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essence of the present invention. In the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other at will.
Claims
1. A control circuit for an extended key, characterized in that: include: A logic chip, a plurality of buttons and an interrupt control module, wherein the logic chip is electrically connected to the plurality of buttons; the logic chip comprises an AND gate logic circuit, and the AND gate logic circuit is electrically connected to the plurality of buttons and the interrupt control module respectively.
2. The control circuit of the extended key according to claim 1, characterized in that: The multiple keys include one or more matrix keys and / or one or more individual keys; the matrix keys are 4*4 matrix keys controlled by K1-K8, and the individual keys are individual keys controlled by KEY1-KEY4 and K9.
3. The control circuit of the extended key according to claim 1, characterized in that: The logic chips include 74HC08 AND gate logic circuit and 74HC21 AND gate logic circuit, as well as 74HC595 logic chip and 74HC165 logic chip.
4. The control circuit of the extended key according to claim 1, characterized in that: The logic chip includes a 74HC165 logic chip of U1, a U2A 74HC21 AND gate logic chip of U2, a U2B 74HC21 AND gate logic chip, a U3A74HC08 AND gate logic chip of U3, a U3B 74HC08 AND gate logic chip, a U3C 74HC08 AND gate logic chip, a 74HC165 logic chip of U4, and a 74HC595 logic chip of U5; the P0-P3 pins of the 74HC165 logic chip of U1 are respectively connected to the A1, B1, C1, and D1 pins of the U2A74HC21 AND gate logic chip; the P4-P7 and SER pins of the 74HC165 logic chip of U1 are grounded; the CLK1 and CLK2 pins of the 74HC165 logic chip of U1 are respectively connected to the SRCLK pins of the 74HC595 logic chip of U5 , RCLK pins are connected; the high-level PL pin of the 74HC165 logic chip of U1 is connected to the high-level PL pin of the 74HC165 logic chip of U4; the low-level Q7 pin of the 74HC165 logic chip of U1 is connected to the core board and is connected to the KeySO1 pin of the core board; the VCC pin of the 74HC165 logic chip of U1 is respectively connected to an external power supply and capacitor C5; the GND pin of the 74HC165 logic chip of U1 is connected to the other end of the capacitor C5 and is grounded.
5. The control circuit of the extended key according to claim 4, characterized in that: The Y1 pin of the U2A 74HC21 AND gate logic chip is connected to the A1 pin of the U3A 74HC08 AND gate logic chip; the G pin of the U2A 74HC21 AND gate logic chip is grounded; and the V pin of the U2A 74HC21 AND gate logic chip is connected to an external power supply.
6. The control circuit of the extended key according to claim 4, characterized in that: The A2, B2, C2, and D2 pins of the U2B 74HC21 AND gate logic chip are respectively connected to the P0-P3 pins of the 74HC165 logic chip of U4; the Y2 pin of the U2B 74HC21 AND gate logic chip is connected to the B1 pin of the U3A 74HC08 AND gate logic chip.
7. The control circuit of the extended key according to claim 4, characterized in that: The Y1 pin of the U3A 74HC08 AND gate logic chip is connected to the A3 pin of the U3C 74HC08 AND gate logic chip; the G pin of the U3A 74HC08 AND gate logic chip is grounded; the V pin of the U3A 74HC08 AND gate logic chip is connected to an external power supply; The A2 and B2 pins of the U3B 74HC08 AND gate logic chip are connected to the P4 pin of the U4 74HC165 logic chip; the Y2 pin of the U3B 74HC08 AND gate logic chip is connected to the B3 pin of the U3C 74HC08 AND gate logic chip; The Y3 pin of the U3C 74HC08 AND gate logic chip is connected to the KeyINT of the core board and is connected to a capacitor C6, and the other end of the capacitor C6 is grounded.
8. The control circuit of the extended key according to claim 4, characterized in that: The P5-P7 and SER pins of the 74HC165 logic chip of U4 are grounded; the CLK1 pin of the 74HC165 logic chip of U4 is connected to the KeySCLK pin of the core board; the CLK2 pin of the 74HC165 logic chip of U4 is connected to the KeyCS pin of the core board; the high-level PL pin of the 74HC165 logic chip of U4 is respectively connected to the collector of the resistor R1 and the transistor Q1; the other end of the resistor R1 is connected to an external power supply; the emitter of the transistor Q1 is connected to the The base of the transistor Q1 is grounded, the base of the transistor Q1 is respectively connected to a resistor R2 and a resistor R3, the other end of the resistor R3 is grounded, and the other end of the resistor R2 is connected to the KeyCS pin of the core board; the low level Q7 pin of the 74HC165 logic chip of U4 is connected to the KeySO2 pin of the core board; the VCC pin of the 74HC165 logic chip of U4 is respectively connected to an external power supply and a capacitor C7, and the other end of the capacitor C7 is grounded; the GND pin of the 74HC165 logic chip of U4 is grounded.
9. The control circuit of the extended key according to claim 4, characterized in that: The O0-O3 pins of the 74HC595 logic chip of U5 are respectively connected to the pins 6 to 9 of the Header16 of P1, and the O0-O3 pins of the 74HC595 logic chip of U5 are respectively connected to the resistor RM5, and the other end of each resistor RM5 is grounded; the SER pin of the 74HC595 logic chip of U5 is connected to the KeySSI pin of the core board; the SRCLK pin of the 74HC595 logic chip of U5 is connected to the KeySCLK pin of the core board; the 74HC595 logic chip of U5 is connected to the KeySCLK pin of the core board; The high-level SRCLR pin of the logic chip is respectively connected to a capacitor C8 and a resistor R5, the other end of the capacitor C8 is grounded, and the other end of the resistor R5 is connected to an external power supply; the RCLK pin of the 74HC595 logic chip of the U5 is connected to the KeyCS pin of the core board; the E pin of the 74HC595 logic chip of the U5 is grounded; the VCC pin of the 74HC595 logic chip of the U5 is respectively connected to an external power supply and a capacitor C10, the other end of the capacitor C10 is grounded; the GND pin of the 74HC595 logic chip of the U5 is grounded.
10. The control circuit of the extended key according to claim 9, characterized in that: Pin 1 of the Header 16 of P1 is grounded; Pin 2 to Pin 5 of the Header 16 of P1 are respectively connected to the P0-P3 pins of the 74HC165 logic chip of U1, and Pin 2 to Pin 5 of the Header 16 of P1 are respectively connected to a resistor RM3, and the other end of each resistor RM5 is connected to an external power supply; Pin 10 of the Header 16 of P1 is respectively connected to a resistor R6, a resistor R4 and a capacitor C9, the other end of the resistor R6 is connected to an external power supply, and the other end of the resistor R4 is connected to the 74HC165 logic chip of U4. The P0 pin of the 74HC165 logic chip of U4 is connected to the P0 pin of the 74HC165 logic chip of U4; the other end of the capacitor C9 is grounded; the pin 11 of the Header16 of P1 is respectively connected to the resistor RM2, the capacitor CM1 and the resistor RM4; the other end of the resistor RM2 is connected to the external power supply; the other end of the capacitor CM1 is grounded; the other end of the resistor RM4 is connected to the P1 pin of the 74HC165 logic chip of U4; the pin 12 of the Header16 of P1 is respectively connected to the resistor RM2, the capacitor CM1 and the resistor RM4, and ... One end is grounded; the other end of the resistor RM4 is connected to the P2 pin of the 74HC165 logic chip of U4; the pin 13 of the Header16 of P1 is respectively connected to the resistor RM2, the capacitor CM1 and the resistor RM4, and the other end of the resistor RM2 is connected to an external power supply; the other end of the capacitor CM1 is grounded; the other end of the resistor RM4 is connected to the P3 pin of the 74HC165 logic chip of U4; the pin 14 of the Header16 of P1 is respectively connected to the resistor RM2, the capacitor CM1 and the resistor RM4, and the other end of the resistor RM2 is connected to the ... The end is connected to an external power supply; the other end of the capacitor CM1 is grounded; the other end of the resistor RM4 is connected to the P4 pin of the 74HC165 logic chip of U4; the pin 15 of the Header16 of P1 is respectively connected to the resistor R7, the capacitor C11 and the resistor R8, the other end of the resistor R7 is grounded, the other end of the capacitor C11 is grounded, and the other end of the resistor R8 is connected to the WKUP output terminal; the pin 16 of the Header16 of P1 is connected to the resistor R9, and the other end of the resistor R9 is connected to the POWER_IN input terminal.