Semiconductor device structure

Abstract

The embodiment of the utility model provides a semiconductor device structure. The semiconductor device structure comprises a plurality of semiconductor devices located on a substrate, a plurality of metal interconnection structures located in a plurality of dielectric material layers covering the semiconductor devices, and a non-ohmic voltage trigger switch. The non-ohmic voltage-triggered switch includes a first switch electrode electrically connected to one of the semiconductor devices via a subset of the metal interconnect structures, a second switch electrode electrically connected to the other of the semiconductor devices via a subset of the metal interconnect structures, and a non-ohmic switch material portion electrically connected to the other of the semiconductor devices via a subset of the metal interconnect structures. The non-ohmic switching material portion provides a non-ohmic current-voltage characteristic and is in contact with the first switching electrode and the second switching electrode. The non-ohmic voltage triggered switch may be used as an electrostatic discharge switch.

Description

Technical Field

[0001] The embodiments of the utility model relate to a semiconductor device structure, and more particularly to a semiconductor device structure of a direct non-ohmic switch for voltage instability protection. Background Art

[0002] Temporary voltage instabilities, such as electrostatic discharge (ESD) and potential-induced degradation (PID), are transient voltage changes that may damage devices and adversely affect circuit performance. It is desirable to provide appropriate protection against such temporary voltage instabilities to protect semiconductor devices from irreversible damage during operation of semiconductor circuits. Utility Model Content

[0003] An embodiment of the utility model provides a semiconductor device structure including: a plurality of semiconductor devices located on a substrate, a plurality of metal interconnect structures located in a plurality of dielectric material layers overlying the semiconductor devices, and a non-ohmic voltage-triggered switch. The non-ohmic voltage-triggered switch includes: a first switch electrode, a second switch electrode, and a non-ohmic switch material portion electrically connected to one of the semiconductor devices through a subset of the metal interconnect structures, the non-ohmic switch material portion electrically connected to the first switch electrode and the second switch electrode, wherein the non-ohmic switch material portion is configured to provide a non-ohmic current-voltage characteristic.

[0004] An embodiment of the utility model provides a semiconductor device structure including: a plurality of semiconductor devices located on a substrate, a first metal interconnect structure located in a first dielectric material layer overlying the semiconductor devices, an electrostatic discharge line overlying the first dielectric material layer, and an electrostatic discharge switch overlying the first dielectric material layer. The electrostatic discharge switch includes a first switch electrode electrically connected to one of the semiconductor devices through a subset of the first metal interconnect structure, a second switch electrode electrically connected to the electrostatic discharge line, and a non-ohmic switch material portion, the non-ohmic switch material portion providing a non-ohmic current-voltage characteristic and contacting the first switch electrode and the second switch electrode, wherein the non-ohmic switch material portion includes a bidirectional threshold material or a phase change memory material.

[0005] Based on the above, embodiments of the present invention are directed to direct non-ohmic switches that provide protection from voltage instability during operation of semiconductor devices. Specifically, the direct non-ohmic switch may use a non-ohmic switch material (e.g., a phase change material or a bidirectional switch material) that forms a conductive path when a voltage pulse having a magnitude exceeding a threshold voltage is applied. The direct non-ohmic switch may be formed directly between a signal input and a current discharge path within a metal interconnect level. Thus, the direct non-ohmic switch does not use any control device (e.g., a field effect transistor) and therefore does not use any semiconductor channel or pn junction. Generally, ESD protection schemes using field effect transistors require a large device area for the control transistor. The non-ohmic voltage-triggered switch of the embodiments does not require any transistors and may be constructed entirely within a dielectric material layer as a back-end structure. As such, the non-ohmic voltage-triggered switch may provide area-efficient ESD protection.

[0006] In order to make the above features and advantages of the embodiments of the present invention more obvious and easy to understand, embodiments are specifically cited below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1A to 1F are sequential vertical cross-sectional views of a first structure during formation of a device structure according to an embodiment of the present disclosure.

[0008] FIG. 2A to FIG. 2D are sequential vertical cross-sectional views of a second structure during formation of a device structure according to an embodiment of the present disclosure.

[0009] FIG. 3A to FIG. 3D are sequential vertical cross-sectional views of a third structure during formation of a device structure according to an embodiment of the present disclosure.

[0010] 4A to 4D are sequential vertical cross-sectional views of a fourth structure during formation of a device structure according to an embodiment of the present disclosure.

[0011] FIG. 5A to FIG. 5D are sequential vertical cross-sectional views of a fifth structure during formation of a device structure according to an embodiment of the present disclosure.

[0012] FIG. 6A to FIG. 6D are sequential vertical cross-sectional views of a sixth structure during formation of a device structure according to an embodiment of the present disclosure.

[0013] Figure 7 is a graph showing the current-voltage characteristics of the non-ohmic switching device of the present disclosure.

[0014] Figure 8 is a schematic diagram illustrating the operation of the non-ohmic switch device of the present disclosure as an electrostatic discharge (ESD) switch according to an embodiment of the present disclosure.

[0015] Fig. 9 is a flow chart illustrating general processing steps for fabricating a device structure according to an embodiment of the present disclosure.

[0016] Description of Reference Numerals

[0017] 8: substrate; 9: semiconductor material layer; 10: second switch electrode / non-ohmic voltage triggered switch; 12: non-ohmic switch material portion / non-ohmic voltage triggered switch; 18: first switch electrode / non-ohmic voltage triggered switch; 152: non-ohmic switch material through-hole structure / through-hole structure; 157, 757: photoresist layer; 159: through-hole opening; 162: through-hole liner; 162L: non-ohmic switch material layer; 168: non-ohmic switch material plate; 178: non-ohmic switch material through-hole structure; 179: through-hole cavity; 601: first dielectric material layer / contact level dielectric material layer / dielectric material layer; 610: first internal connection level dielectric material layer / dielectric material layer / first dielectric material layer; 612 : device contact via structure / metal interconnect structure / first metal interconnect structure; 618: first conductive line structure / metal interconnect structure / first metal interconnect structure; 620: second interconnect level dielectric material layer / dielectric material layer / first dielectric material layer; 622: first conductive via structure / metal interconnect structure / conductive via structure / first metal interconnect structure; 628: second conductive line structure / metal interconnect structure / conductive line structure / first metal interconnect structure; 630: third interconnect level dielectric material layer / dielectric material layer / first dielectric material layer; 632: second conductive via structure / metal interconnect structure / conductive via structure / first metal interconnect structure; 638: third conductive line structure / metal interconnect structure 640: fourth interconnection level dielectric material layer / dielectric material layer / first dielectric material layer; 642: third conductive hole structure / metal interconnection structure / conductive hole structure / first metal interconnection structure; 648: fourth conductive line structure / metal interconnection structure / conductive line structure / first metal interconnection structure; 648D: electrostatic discharge line; 650: fifth interconnection level dielectric material layer / dielectric material layer; 652: fourth conductive hole structure; 653: through hole level dielectric material layer; 655: line level dielectric material layer; 657: masking material layer; 658: fifth conductive line structure / conductive line structure; 659A: first metal plate / metal plate; 659B: second metal plate : metal plate / metal plate; 660: bonding level dielectric layer / dielectric material layer; 668: metal pad; 668D: electrostatic discharge pad; 668I: signal input pad; 700: CMOS circuit; 701: semiconductor device; 720: shallow trench isolation structure; 732: source electrode; 735: semiconductor channel; 738: drain electrode; 742: source side metal semiconductor alloy region; 748: drain side metal semiconductor alloy region; 750: gate structure; 752: gate dielectric layer; 754: gate electrode; 756: dielectric gate spacer; 758: gate cap dielectric; 910, 920, 930, 940: steps; GND: grounding; s: target spacing; V_th: threshold voltage. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to limit the scope of the present disclosure. For example, in the following description, a first feature is formed "above" or "on" a second feature, which may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present disclosure may reuse component numbers and / or letters in various examples. Such repetition is for the purpose of simplifying and clearly describing the present disclosure, rather than for defining the relationship between various embodiments and / or configurations.

[0019] In addition, for ease of description, spatially relative terms such as "under," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one component or feature shown in a figure to another (other) component or feature. In addition to the orientation shown in the figure, the spatially relative terms also cover different orientations of the device in use or operation. The device can have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptors used therein can also be interpreted in the same manner. Components with the same reference number refer to the same component and are assumed to have the same material composition and the same thickness range unless otherwise expressly stated.

[0020] Embodiments of the present invention are directed to direct non-ohmic switches that provide protection from voltage instabilities (e.g., transient voltage spikes) during operation of semiconductor devices. Specifically, various embodiments of direct non-ohmic switches disclosed herein may use non-ohmic switch materials (e.g., phase change materials or bidirectional switch materials) that form a conductive path when a voltage pulse having a magnitude exceeding a threshold voltage is applied. Various embodiments of direct non-ohmic switches disclosed herein may be formed directly between a signal input and a current discharge path within a metal interconnect level. Thus, various embodiments of direct non-ohmic switches disclosed herein do not use any control device (e.g., a field effect transistor) and therefore do not use any semiconductor channel or pn junction. Various embodiments of direct non-ohmic switches disclosed herein may include a first metal material portion, a non-ohmic switch material portion in direct contact with the first metal material portion, and a second metal material portion in direct contact with the non-ohmic switch material portion. The non-ohmic switching material portion may be formed within the metal interconnect level and may include a via structure as a via liner structure, a plate in contact with a conductive line, a plate in contact with at least one self-aligned plated material portion, a via structure in contact with a sidewall of a conductive line, or a via structure in contact with at least one self-aligned plated material portion. Various embodiments of the present disclosure are now described with reference to the drawings.

[0021] Reference Figure 1A , showing a first embodiment structure of the present disclosure. The first embodiment structure includes a substrate 8, which may be a semiconductor substrate, such as a commercially available silicon substrate. The substrate 8 may include a semiconductor material layer 9 at least at its upper portion. The semiconductor material layer 9 may be a surface portion of a bulk semiconductor substrate or may be a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate. In one embodiment, the semiconductor material layer 9 includes a single crystal semiconductor material, such as single crystal silicon. In one embodiment, the substrate 8 may include a single crystal silicon substrate including a single crystal silicon material.

[0022] A shallow trench isolation structure 720 including a dielectric material such as silicon oxide may be formed in an upper portion of the semiconductor material layer 9. Appropriate doped semiconductor wells, such as a p-type well and an n-type well, may be formed in each region laterally enclosed by a portion of the shallow trench isolation structure 720. A semiconductor device 701 such as a field effect transistor may be formed over the top surface of the semiconductor material layer 9. For example, each field effect transistor may include: a source electrode 732, a drain electrode 738, a semiconductor channel 735 including a surface portion of the substrate 8 extending between the source electrode 732 and the drain electrode 738, and a gate structure 750. The semiconductor channel 735 may include a single crystalline semiconductor material. Each gate structure 750 may include a gate dielectric layer 752, a gate electrode 754, a gate cap dielectric 758, and a dielectric gate spacer 756. A source-side metal semiconductor alloy region 742 may be formed on each source electrode 732, and a drain-side metal semiconductor alloy region 748 may be formed on each drain electrode 738. The devices formed on the top surface of the semiconductor material layer 9 may include complementary metal-oxide-semiconductor (CMOS) transistors and optional additional semiconductor devices (eg, resistors, diodes, capacitor circuits, etc.) and are collectively referred to as CMOS circuits 700 .

[0023] One or more of the field effect transistors in the CMOS circuit 700 may include a semiconductor channel 735, which includes a portion of a semiconductor material layer 9 located in the substrate 8. In an embodiment in which the semiconductor material layer 9 includes a single crystalline semiconductor material such as single crystalline silicon, the semiconductor channel 735 of each field effect transistor in the CMOS circuit 700 may include a single crystalline semiconductor channel such as a single crystalline silicon channel. In an embodiment, a subset of the field effect transistors in the CMOS circuit 700 may include a corresponding node, which is then electrically connected to a node of an energy harvesting device and / or is then electrically connected to a battery structure to be formed later.

[0024] In one embodiment, the substrate 8 may include a single crystal silicon substrate, and the field effect transistor 701 may include a corresponding portion of the single crystal silicon substrate as a semiconducting channel. As used herein, a "semiconducting" device refers to a device having a capacitance between 1.0×10 -6 Siemens / cm to 1.0×10 5 Siemens / cm. As used herein, "semiconductor material" refers to a semiconductor material having an electrical conductivity in the range of 1.0×10 -6 Siemens / cm to 1.0×10 5Siemens / cm range, and can be produced with conductivity ranging from 1.0 Siemens / cm to 1.0×10 5 Doped materials with electrical conductivities in the range of Siemens / cm.

[0025] Various metal interconnect structures formed in the dielectric material layer may then be formed on the substrate 8 and the semiconductor device 701 (e.g., a field effect transistor) located on the substrate. In an illustrative example, the dielectric material layer may include, for example, a first dielectric material layer 601 (the first dielectric material layer 601 may be a layer surrounding a contact structure connected to a source and a drain) (sometimes referred to as a contact-level dielectric material layer 601), a first interconnect-level dielectric material layer 610, a second interconnect-level dielectric material layer 620, a third interconnect-level dielectric material layer 630, and a fourth interconnect-level dielectric material layer 640. The metal interconnect structure may include: a device contact through-hole structure 612 formed in the first dielectric material layer 601 and contacting the corresponding components of the CMOS circuit 700, a first conductive line structure 618 formed in the first interconnect level dielectric material layer 610, a first conductive via structure 622 formed in the lower portion of the second interconnect level dielectric material layer 620, a second conductive line structure 628 formed in the upper portion of the second interconnect level dielectric material layer 620, a second conductive via structure 632 formed in the lower portion of the third interconnect level dielectric material layer 630, a third conductive line structure 638 formed in the upper portion of the third interconnect level dielectric material layer 630, a third conductive via structure 642 formed in the lower portion of the fourth interconnect level dielectric material layer 640, and a fourth conductive line structure 648 formed in the upper portion of the fourth interconnect level dielectric material layer 640. Although the present disclosure is described using embodiments in which four levels of conductive line structures are formed in a dielectric material layer, embodiments in which fewer or greater numbers of conductive line structures are formed in a dielectric material layer are expressly contemplated herein.

[0026] Each of the dielectric material layers (601, 610, 620, 630, 640) may include a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) may include at least one conductive material, which may be a combination of a metal liner material (e.g., a metal nitride or a metal carbide) and a metal filler material. Each metal liner may include TiN, TaN, WN, TiC, TaC, and WC, and each metal filler material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable metal liner materials and metal filler materials within the contemplation of the present disclosure may also be used. In one embodiment, the first conductive via structure 622 and the second conductive line structure 628 can be formed as an integrated line and via structure by a dual damascene process. In general, any contiguous set of conductive line structures (628, 638, 648) and at least one underlying conductive via structure (622, 632, 642) can be formed as an integrated line and via structure.

[0027] Generally, semiconductor device 701 may be formed on substrate 8, and metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) and dielectric material layers (601, 610, 620, 630, 640) may be formed on semiconductor device 701. Metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) may be formed in dielectric material layers (601, 610, 620, 630, 640) and may be electrically connected to the semiconductor device.

[0028] A subset of the metal interconnect structures at the topmost level of the dielectric material layers (601, 610, 620, 630, 640) may include switch electrodes of a non-Ohmic voltage-triggered switch to be formed later. For example, one of the fourth conductive line structures 648 may include a switch electrode, which is referred to herein as a second switch electrode 10. In one embodiment, the second switch electrode 10 may be an electrostatic discharge (ESD) line 648D, which is configured to carry high transient currents during an electrostatic discharge event. In one embodiment, the second switch electrode 10 may be formed as a conductive line.

[0029] According to the disclosed aspect, the second switch electrode 10 includes a material that resists electromigration and outdiffusion of the material under an external electrical bias voltage. For example, the second switch electrode 10 may include the following materials and / or may be essentially composed of the following materials: at least one metal barrier material, at least one refractory metal, a highly conductive metal, a conductive metal oxide, a heavily doped semiconductor material, an alloy or compound thereof, and / or a stack thereof. Non-limiting exemplary metal barrier materials that can be used for the second switch electrode 10 include TiN, TaN, WN, MoN, TiC, TaC, WC, etc. Refractory metals include W, Ta, Re, Mo, and Nb. Non-limiting examples of highly conductive metals include Os, Ir, Pt, Au, Pd, Ni, Al, Ti, etc. A non-limiting example of a conductive metal oxide is iridium oxide (IrO2). Non-limiting examples of heavily doped semiconductor materials include heavily p-doped polysilicon, heavily n-doped polysilicon, heavily doped silicon-germanium alloys, etc. As used herein, heavily doped semiconductor material refers to a semiconductor material containing atoms at a concentration greater than 1.0×10 20 / cubic centimeter of electrical dopant semiconductor material.

[0030] In some embodiments, the second switch electrode 10 may include a lower portion consisting of copper or aluminum or may not include a lower portion consisting of copper or aluminum. In one embodiment, the fourth conductive line structure 648 other than the second switch electrode 10 may include copper or aluminum, and the second switch electrode 10 may include a lower portion consisting of copper or aluminum. In one embodiment, the second switch electrode 10 may include an upper portion including a conductive material different from copper or aluminum. In this embodiment, the fourth conductive line structure 648 other than the second switch electrode 10 may include a conductive material of the upper portion of the second switch electrode 10 or may not include a conductive material of the upper portion of the second switch electrode 10. In one embodiment, the second switch electrode 10 may include a conductive material different from copper or aluminum and / or may consist essentially of a conductive material different from copper or aluminum, and the fourth conductive line structure 648 other than the second switch electrode 10 may include a material different from the conductive material of the second switch electrode 10. In one embodiment, the fourth conductive line structure 648 except the second switch electrode 10 may include copper and / or aluminum, and the second switch electrode 10 may not include copper and / or aluminum.

[0031] The height of the second switch electrode 10 may be in the range of 30 nm to 500 nm (e.g., 50 nm to 300 nm), but smaller or larger thicknesses may also be used. In one embodiment, the top surface of the second switch electrode 10 may be located in a horizontal plane including the top surface of the fourth interconnect level dielectric material layer 640.

[0032] Reference Figure 1B, a via-level dielectric material layer 653 may be deposited over the fourth interconnect-level dielectric material layer 640. The via-level dielectric material layer 653 includes a dielectric material, such as undoped silicate glass, doped silicate glass, silicon nitride, silicon carbonitride, or a stack thereof. The via-level dielectric material layer 653 may be formed by chemical vapor deposition. The via-level dielectric material layer 653 may have a thickness ranging from 30 nanometers to 500 nanometers (e.g., from 60 nanometers to 300 nanometers), although lesser or greater thicknesses may also be used.

[0033] A through-hole opening (not shown) may be formed on a corresponding one of the fourth conductive line structures 648 through the through-hole level dielectric material layer 653. At least one through-hole opening may be formed on the second switch electrode 10. For example, a photoresist layer (not shown) may be applied on the through-hole level dielectric material layer 653, and the photoresist layer may be patterned photolithographically to form discrete openings in the photoresist layer. An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the through-hole level dielectric material layer 653. Each volume in which a portion of the through-hole level dielectric material layer 653 is removed constitutes a through-hole opening. The top surface of the fourth conductive line structure 648 or the second switch electrode 10 may be physically exposed at the bottom of each through-hole opening. The photoresist layer may then be removed, for example, by ashing.

[0034] At least one conductive material, which may be at least one metal material, may be deposited in the via opening. Excessive portions of the at least one conductive material may be removed from above a horizontal plane including the top surface of the via-level dielectric material layer 653. Each remaining portion of the at least one conductive material that fills the corresponding via opening constitutes a via structure, which is referred to herein as a fourth via structure 652. Each fourth via structure 652 may contact the top surface of the fourth conductive line structure 648 or the second switch electrode 10. In one embodiment, each fourth via structure 652 may include a metal barrier liner and a metal filling material portion. The metal barrier liner may include a metal barrier material, such as TiN, TaN, WN, MoN, TiC, TaC, WC, or a combination thereof. The metal filling material portion may include Cu, Al, Ru, W, Mo, Co, or a combination thereof. In one embodiment, the metal filling material may include Cu or Al. The top surface of the fourth via structure 652 may be formed in a horizontal plane including the top surface of the via-level dielectric material layer 653.

[0035] Reference Figure 1CA photoresist layer (not shown) may be applied over the via-level dielectric material layer 653 and may be patterned photolithographically to form discrete openings in the photoresist layer. An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the via-level dielectric material layer 653. The volume in which a portion of the via-level dielectric material layer 653 is removed constitutes the via opening 159. The top surface of the second switch electrode 10 may be physically exposed at the bottom of the via opening 159. The photoresist layer may then be removed, for example, by ashing.

[0036] Reference Figure 1D , at least one non-ohmic switching material may be deposited in the via opening 159, and excess portions of the at least one non-ohmic switching material may be removed from outside the via opening 159 (i.e., from above the horizontal plane including the top surface of the via-level dielectric material layer 653). As used herein, a non-ohmic switching material refers to a material that exhibits nonlinear current characteristics that vary with an applied external voltage. As used herein, a non-ohmic switching material refers to a non-ohmic switching material that exhibits a higher effective resistivity (i.e., resistance divided by distance multiplied by area) at a low applied voltage and exhibits a low effective resistivity at a high applied voltage. The highest voltage at which the non-ohmic switching material exhibits a higher effective resistivity is referred to herein as a critical voltage. In general, a non-ohmic switching material has an inherent critical electric field, at which the characteristics of the non-ohmic switching material change from a high resistivity state to a low resistivity state as the external electric field increases. The critical voltage is typically the product of the inherent critical electric field and the thickness (or dimension along the electric field) of the non-ohmic switching material.

[0037] The remaining portion of the at least one non-ohmic switching material that fills the via opening 159 constitutes a non-ohmic switching material portion 12 as a non-ohmic switching material via structure 152. The non-ohmic switching material via structure 152 may be formed on the top surface of each of the second switch electrodes 10. The non-ohmic switching material portion 12 includes and / or essentially consists of at least one non-ohmic switching material. The non-ohmic switching material portion 12 has a threshold voltage at which the electrical property of the non-ohmic switching material portion 12 changes from a non-conductive state to a conductive state.

[0038] Generally speaking, the non-ohmic switching material portion 12 includes and / or essentially consists of at least one bidirectional threshold material and / or at least one phase change memory material.

[0039] In one embodiment, the non-ohmic switch material portion 12 includes and / or consists essentially of at least one bidirectional threshold material, such as germanium-antimony-tellurium compound, germanium-tellurium compound, germanium-antimony compound, antimony-tellurium compound, germanium-selenium compound, germanium-selenium-nitrogen compound, germanium-selenium-arsenic compound, germanium-selenium-antimony compound, silicon-tellurium compound, zinc-tellurium compound, carbon-tellurium compound, boron-tellurium compound, germanium-arsenic-tellurium compound, etc. The bidirectional threshold material may be doped with at least one dopant atom or may not be doped with at least one dopant atom to enhance electrical properties, such as switching properties. The at least one dopant atom may include one or more of Si, N, O, Ni, Al, Ti, W, Cu, C, B, Sn, In, Ag, etc.

[0040] Alternatively or additionally, the non-ohmic switching material portion 12 may include at least one phase change memory material and / or may be essentially composed of at least one phase change memory material. As used herein, "phase change memory material" refers to a material having at least two different phases that provide different resistivities. Phase change memory (PCM) materials can be used to store information as a resistivity state of a material, which can be in different resistivity states corresponding to the differences in the material. Different phases may include an amorphous state with a high resistivity and a crystalline state with a low resistivity (i.e., a resistivity lower than that of the amorphous state). Exemplary phase change memory materials include, but are not limited to, germanium antimonytelluride (GST) compounds, such as Ge2Sb2Te5 or GeSb2Te4, germanium antimony compounds, indium germanium telluride compounds, aluminum telluride selenide compounds, indium telluride selenide compounds, and aluminum indium telluride selenide compounds. In general, a phase change memory material may or may not be a bidirectional threshold material, and a bidirectional threshold material may or may not be a phase change memory material.

[0041] The top surface of the non-ohmic switching material portion 12 including the non-ohmic switching material via structure 152 may be formed within a horizontal plane including the top surface of the via-level dielectric material layer 653 .

[0042] Reference Figure 1E , a line-level dielectric material layer 655 and a fifth conductive line structure 658 may be formed on the via-level dielectric material layer 653. The combination of the via-level dielectric material layer 653 and the line-level dielectric material layer 655 is referred to herein as an interconnect-level dielectric layer or a fifth interconnect-level dielectric material layer 650. The fifth conductive line structure 658 is a conductive line structure formed in the fifth interconnect-level dielectric material layer 650, such as a metal line structure.

[0043] The fifth conductive line structures 658 may include: a first subset of the fifth conductive line structures 658 that do not contact the non-ohmic switching material portion 12 (including the non-ohmic switching material via structure 152) and serve as metal interconnect routing of the semiconductor device 701; and a second subset of the fifth conductive line structures 658 that serve as the first switch electrodes 18 and directly contact the top surface of the non-ohmic switching material portion 12 and the top surface of at least one fourth conductive via structure 652. In one embodiment, one fifth conductive line structure 658, a plurality of fifth conductive line structures 658, and / or each of the fifth conductive line structures 658 in the first subset of the fifth conductive line structures 658 may contact the top surface of the corresponding fourth conductive via structure 652.

[0044] The first subset of the fifth conductive line structure 658 and the second subset of the fifth conductive line structure 658 may include the same set of conductive materials or may not include the same set of conductive materials. For example, the first subset of the fifth conductive line structure 658 may include a copper-based metal portion and / or an aluminum-based metal portion. The second subset of the fifth conductive line structure 658, which may include the first switch electrode 18, may include any material that can be used for the second switch electrode 10 as discussed above.

[0045] In one embodiment, the first switch electrode 18 may be electrically connected to at least one semiconductor device 701 located on the substrate 8. In one embodiment, the node of the semiconductor device 701 electrically connected to the first switch electrode 18 may include an input node of the semiconductor device 701, such as a gate electrode of a field effect transistor. In this embodiment, the conductive path between the first switch electrode 18 and the input node of the semiconductor device 701 includes an input signal path formed by a metal interconnect structure.

[0046] Optionally, at least one of the fourth via structures 652 and / or at least one of the fifth conductive line structures 658 may be electrically connected to the second switch electrode 10 , which also serves as the electrostatic discharge line 648D and may be used as a component of the electrostatic discharge path.

[0047] According to aspects of the present disclosure, the first switch electrode 18 includes a material that resists electromigration and outdiffusion of the material under an external electrical bias voltage. For example, the first switch electrode 18 may include and / or may consist essentially of at least one metal barrier material, at least one refractory metal, a highly conductive metal, a conductive metal oxide, a heavily doped semiconductor material, an alloy or compound thereof, and / or a stack thereof.

[0048] In some embodiments, each of the first switch electrodes 18 may include a corresponding upper portion composed of copper or aluminum or may not include a corresponding upper portion composed of copper or aluminum. In one embodiment, a first subset of the fifth conductive line structures 658 that do not contact the non-ohmic switching material portion 12 may include copper or aluminum, and the first switch electrodes 18 may include a corresponding upper portion composed of copper or aluminum. In one embodiment, the first switch electrode 18 may include a lower portion that includes a conductive material different from copper or aluminum. In this embodiment, a first subset of the fifth conductive line structures 658 that do not contact the non-ohmic switching material portion 12 may include a conductive material of the lower portion of the first switch electrode 18 or may not include a conductive material of the lower portion of the first switch electrode 18. In one embodiment, the first switch electrode 18 may include a conductive material different from copper or aluminum and / or may be mainly composed of a conductive material different from copper or aluminum, and the first subset of the fifth conductive line structures 658 may include a material different from the conductive material of the first switch electrode 18. In one embodiment, the first subset of the fifth conductive line structure 658 may include copper and / or aluminum, and the first switch electrode 18 may not include copper and / or aluminum.

[0049] The height of the first switch electrode 18 may be in a range from 30 nm to 500 nm (e.g., from 50 nm to 300 nm), but smaller or larger thicknesses may also be used. In one embodiment, the top surface of the first switch electrode 18 may be located in a horizontal plane including the top surface of the fifth interconnect level dielectric material layer 650.

[0050] Reference Figure 1F , a bonding level dielectric layer 660 may be formed on the fifth interconnect level dielectric layer 650. Optionally, before forming the bonding level dielectric layer 660, at least one additional interconnect level dielectric material layer (not shown) and an additional metal interconnect structure (not shown) may be formed on the fifth interconnect level dielectric layer 650. A pad cavity may be formed in the bonding level dielectric layer 660, and a metal pad 668 may be formed in the pad cavity. The metal pad 668 may include a signal input pad 668I and an electrostatic discharge pad 668D. The signal input pad 668I may be electrically connected to the first switch electrode 18 and / or may contact the first switch electrode 18. The electrostatic discharge pad 668D may be electrically connected to the electrostatic discharge line 648D via a set of metal interconnect structures, and form a component of the electrostatic discharge path. An alternative electrostatic discharge structure (e.g., an electrostatic discharge line, an electrostatic discharge plate, an electrostatic discharge metal frame, etc.) may be used to replace the electrostatic discharge pad 668D.

[0051] Generally, an electrostatic discharge (ESD) switch may be formed on top of the dielectric material layer (601, 610, 620, 630, 640). The first embodiment structure includes a device structure, which includes: a semiconductor device 701 located on a substrate 8, a metal interconnect structure (612, 618, 622, 628, 632, 638, 642, 648) located in a dielectric material layer (601, 610, 620, 630, 640, 650, 660) overlying the semiconductor device 701, and a non-ohmic voltage-triggered switch (18, 12, 10), wherein the non-ohmic voltage-triggered switch includes a first switch electrode 18, a second switch electrode 10, and a non-ohmic switch material portion 12, wherein the first switch electrode 18 is electrically connected to one of the semiconductor devices 701 through a subset of the metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648), and the non-ohmic switch material portion 12 provides a non-ohmic current-voltage characteristic and contacts the first switch electrode 18 and the second switch electrode 10.

[0052] In one embodiment, the non-ohmic switching material portion 12 comprises a bidirectional threshold material or a phase change memory material. In one embodiment, the non-ohmic switching material portion 12 comprises a sidewall surface segment in contact with a first dielectric material layer (e.g., via-level dielectric material layer 653) selected from the dielectric material layers (601, 610, 620, 630, 640, 650, 660).

[0053] In one embodiment, the non-ohmic switching material portion 12 includes a through-hole structure 152 and the entire top surface of the non-ohmic switching material portion 12 contacts a section of the bottom surface of the first switch electrode 18. In one embodiment, the second switch electrode 10 is formed of a first conductive line, the non-ohmic switching material portion 12 is formed as a through-hole structure 152 directly on the top surface of the second switch electrode 10, and the first switch electrode 18 is formed as a second conductive line on the top surface of the non-ohmic switching material portion 12. In one embodiment, the first switch electrode 18 contacts the top surface of the non-ohmic switching material portion 12 and the second switch electrode 10 contacts the bottom surface of the non-ohmic switching material portion 12. The threshold voltage of the non-ohmic switching material portion 12 can be controlled by the height of the through-hole structure 152.

[0054] According to aspects of the present disclosure, the device structure of the present disclosure may include: a semiconductor device 701 located on a substrate 8, a first metal interconnect structure (612, 618, 622, 628, 632, 638, 642, 648) located in a first dielectric material layer (601, 610, 620, 630, 640) overlying the semiconductor device 701, an electrostatic discharge line 648D overlying the first dielectric material layer (601, 610, 620, 630, 640), and an electrostatic discharge (ESD) switch overlying the first dielectric material layer (601, 610, 620, 630, 640). The electrostatic discharge (ESD) switch includes a first switch electrode 18, a second switch electrode 10 and a non-ohmic switch material portion 12. The first switch electrode 18 is electrically connected to one of the semiconductor devices 701 through a subset of metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648). The second switch electrode 10 is electrically connected to the electrostatic discharge line 648D. The non-ohmic switch material portion 12 provides non-ohmic current-voltage characteristics and contacts the first switch electrode 18 and the second switch electrode 10, wherein the non-ohmic switch material portion 12 includes a bidirectional threshold material or a phase change memory material.

[0055] In one embodiment, the second switch electrode 10 includes a first conductive line, the first switch electrode 18 includes a second conductive line, and the non-ohmic switch material portion 12 includes a via structure 152 laterally surrounded by a second dielectric material layer (e.g., a via-level dielectric material layer 653), the second dielectric material layer overlying the first dielectric material layer (601, 610, 620, 630, 640) and contacting the bottom surface of the first switch electrode 18 and the top surface of the second switch electrode 10. The electrostatic discharge line 648D is electrically connected to the second switch electrode 10.

[0056] FIG. 2A to FIG. 2D 2 is a series of vertical cross-sectional views of a second embodiment of the structure during formation of a device structure of the present disclosure.

[0057] Reference Figure 2A , the at least one non-ohmic switching material may be deposited so that the at least one non-ohmic switching material does not completely cover the through hole opening 159 ( Figure 1C The volume shown in Figure 1C The first embodiment structure shown in the figure is obtained to obtain the second embodiment structure. The at least one non-ohmic switching material forms a non-ohmic switching material layer 162L. There is a gap at the central portion of the through hole opening 159 that is not filled by the non-ohmic switching material layer 162L. The non-ohmic switching material layer 162L may include a Figure 1DAny of the materials described for the non-ohmic switching material portion 12. The non-ohmic switching material layer 162L may be deposited over the via level dielectric material layer 653 in a conformal manner or in a non-conformal manner.

[0058] Reference Figure 2B , a photoresist layer 157 may be applied over the non-ohmic switching material layer 162L, and the photoresist layer 157 may be patterned photolithographically to form discrete photoresist material portions covering the entire area of ​​the through-hole opening. The periphery of the discrete photoresist material portion may be laterally offset outwardly from the upper periphery of the through-hole opening by a lateral offset distance, and the lateral offset distance may be in a range from 3 nanometers to 100 nanometers (e.g., from 6 nanometers to 50 nanometers). An etching process may be performed to remove the unmasked portion of the non-ohmic switching material layer 162L. The patterned remainder of the non-ohmic switching material layer 162L constitutes the non-ohmic switching material portion 12, which may include a through-hole liner 162, which contacts the sidewall of the through-hole opening through the through-hole level dielectric material layer 653. In one embodiment, the via liner 162 may include a horizontally extending portion (which may be an annular plate portion) in contact with a surface segment of the top surface of the via-level dielectric material layer 653. The thickness of the horizontally extending portion of the via liner 162 in contact with the top surface of the second switch electrode 10 may be in a range from 10 nanometers to 100 nanometers (e.g., from 20 nanometers to 60 nanometers), but smaller or larger thicknesses may also be used. The photoresist layer 157 may be removed selectively relative to the via liner 162, for example, by ashing.

[0059] Reference Figure 2C A fifth conductive line structure 658 may be formed on the via level dielectric material layer 653, the non-ohmic switch material portion (including the via liner 162) and the fourth via structure 652. The fifth conductive line structure 658 is a conductive line structure, such as a metal line structure.

[0060] The fifth conductive line structures 658 may include: a first subset of the fifth conductive line structures 658, which do not contact the non-ohmic switching material portion 12 (including the via liner 162) and serve as metal interconnect traces of the semiconductor device 701, and a second subset of the fifth conductive line structures 658, which serve as first switch electrodes 18 and directly contact the top surface of the non-ohmic switching material portion 12 and the top surface of at least one fourth conductive via structure 652. In one embodiment, one fifth conductive line structure 658, a plurality of fifth conductive line structures 658, and / or each of the fifth conductive line structures 658 in the first subset of the fifth conductive line structures 658 may contact the top surface of the corresponding fourth conductive via structure 652.

[0061] The first subset of the fifth conductive line structure 658 and the second subset of the fifth conductive line structure 658 may include the same set of conductive materials or may not include the same set of conductive materials. For example, the first subset of the fifth conductive line structure 658 may include a copper-based metal portion and / or an aluminum-based metal portion. The second subset of the fifth conductive line structure 658 including the first switch electrode 18 may include any material that can be used for the second switch electrode 10 as discussed above.

[0062] In one embodiment, the first switch electrode 18 is electrically connected to at least one semiconductor device 701 located on the substrate 8. In one embodiment, the node of the semiconductor device 701 electrically connected to the first switch electrode 18 may include an input node of the semiconductor device 701, such as a gate electrode of a field effect transistor. In this embodiment, the conductive path between the first switch electrode 18 and the input node of the semiconductor device 701 includes an input signal path formed by a metal interconnect structure.

[0063] Optionally, at least one of the fourth via structures 652 and / or at least one of the fifth conductive line structures 658 may be electrically connected to the second switch electrode 10 , which also serves as the electrostatic discharge line 648D and may be used as a component of the electrostatic discharge path.

[0064] According to aspects of the present disclosure, the first switch electrode 18 includes a material that resists electromigration and outdiffusion of the material under an external electrical bias voltage. Generally speaking, the materials that can be used for the first switch electrode 18 and for the first subset of the fifth conductive line structure 658 that does not contact the non-ohmic switch material portion 12 can be the same as described with reference to the first embodiment structure.

[0065] The height of the first switch electrode 18 may be in a range from 30 nm to 500 nm (e.g., from 50 nm to 300 nm), but smaller or larger thicknesses may also be used. In one embodiment, the top surface of the first switch electrode 18 may be located in a horizontal plane including the top surface of the fifth interconnect level dielectric material layer 650.

[0066] Reference Figure 2D A line-level dielectric material layer 655 may be formed over the fifth conductive line structure 658. The combination of the via-level dielectric material layer 653 and the line-level dielectric material layer 655 is referred to herein as an interconnect-level dielectric layer or a fifth interconnect-level dielectric material layer 650.

[0067] Then, reference can be made Figure 1F The processing steps are described to form the bonding level dielectric layer 660 and the metal pads 668. The metal pads 668 may include a signal input pad 668I and an electrostatic discharge pad 668D.

[0068] In general, the second embodiment structure may provide the same features as the first embodiment structure, except that the non-ohmic switching material portion 12 includes a via liner 162 instead of the non-ohmic switching material via structure 152. In addition, the first switch electrode 18 may include a downwardly protruding portion that protrudes into the volume of the via opening where the via liner 162 is located. The downwardly protruding portion of the first switch electrode 18 may contact the inner sidewall of the via liner 162. The threshold voltage of the non-ohmic switching material portion 12 may be controlled by the thickness of the horizontally extending portion of the via liner 162 located at the bottom portion of the via opening.

[0069] In one embodiment, the non-ohmic switching material portion 12 (including the via liner 162) includes a sidewall surface segment in contact with a first dielectric material layer (e.g., via level dielectric material layer 653) selected from the dielectric material layers (601, 610, 620, 630, 640, 650, 660) of the second embodiment structure.

[0070] In one embodiment, the first switch electrode 18 contacts the top surface of the non-ohmic switching material portion 12 and the second switch electrode 10 contacts the bottom surface of the non-ohmic switching material portion 12. In one embodiment, the non-ohmic switching material portion 12 includes a via liner 162 located in a peripheral portion of the via opening and the second switch electrode 10 includes a portion located in an inner portion of the via opening and contacting an inner sidewall of the via liner 162.

[0071] In one embodiment, the second switch electrode 10 includes a first conductive line, the non-ohmic switching material portion 12 includes a through-hole liner 162, and the through-hole liner 162 is located in a peripheral portion of a through-hole opening 159 in a second dielectric material layer overlying the first dielectric material layer (601, 610, 620, 630, 640), and the second switch electrode 18 includes a second conductive line, the second conductive line includes a downward protruding portion, the downward protruding portion is located in an inner portion of the through-hole opening 159 and contacts the inner side wall of the through-hole liner 162.

[0072] FIG. 3A to FIG. 3D are sequential vertical cross-sectional views of a third embodiment of the structure during formation of a device structure of the present disclosure.

[0073] Reference Figure 3A The fourth conductive via structure 652 can be formed at the location where the non-ohmic switch material via structure 152 of the first embodiment is subsequently formed. Figure 1B The illustrated embodiment structure obtains the third embodiment structure. In other words, an additional fourth via structure 652 is formed to replace the non-ohmic switching material via structure 152 of the first embodiment structure.

[0074] Reference Figure 3B, a line-level dielectric material layer 655 and a fifth conductive line structure 658 may be formed on the via-level dielectric material layer 653. The combination of the via-level dielectric material layer 653 and the line-level dielectric material layer 655 is referred to herein as an interconnect-level dielectric layer or a fifth interconnect-level dielectric material layer 650. The fifth conductive line structure 658 is a conductive line structure formed in the fifth interconnect-level dielectric material layer 650, such as a metal line structure.

[0075] The fifth conductive line structures 658 may include: a first subset of the fifth conductive line structures 658 that are not electrically connected to the non-ohmic switching material portion to be formed later, and a second subset of the fifth conductive line structures 658 that serve as a combination of the first switch electrode 18 and the second switch electrode 10. In one embodiment, one fifth conductive line structure 658, a plurality of fifth conductive line structures 658, and / or each of the fifth conductive line structures 658 in the first subset of the fifth conductive line structures 658 may contact the top surface of the corresponding fourth via structure 652.

[0076] The first subset of the fifth conductive line structure 658 and the second subset of the fifth conductive line structure 658 may include the same set of conductive materials or may not include the same set of conductive materials. For example, the first subset of the fifth conductive line structure 658 may include a copper-based metal portion and / or an aluminum-based metal portion. The second subset of the fifth conductive line structure 658 including a combination of the first switch electrode 18 and the second switch electrode may include any material that can be used for the second switch electrode 10 in the first embodiment structure.

[0077] According to aspects of the present disclosure, the first switch electrode 18 and the second switch electrode 10 include materials that resist electromigration and out-diffusion of materials under an external electrical bias voltage. The first switch electrode 18 and the second switch electrode 10 may include at least one conductive material of the same group, and the at least one conductive material may be any material that can be used for the second switch electrode 10 in the first embodiment structure. The height of the first switch electrode 18 and the second switch electrode 10 may be in the range of from 30 nanometers to 500 nanometers (e.g., from 50 nanometers to 300 nanometers), but smaller or larger thicknesses may also be used. In one embodiment, the top surface of the first switch electrode 18 and the top surface of the second switch electrode 10 may be located in a horizontal plane including the top surface of the fifth interconnect level dielectric material layer 650.

[0078] In one embodiment, the first switch electrode 18 is electrically connected to at least one semiconductor device 701 located on the substrate 8. In one embodiment, the node of the semiconductor device 701 electrically connected to the first switch electrode 18 may include an input node of the semiconductor device 701, such as a gate electrode of a field effect transistor. In this embodiment, the conductive path between the first switch electrode 18 and the input node of the semiconductor device 701 includes an input signal path formed by a metal interconnect structure.

[0079] Reference Figure 3C A non-ohmic switching material layer may be deposited on the top surfaces of the fifth interconnection level dielectric material layer 650, the first switch electrode 18, and the second switch electrode 10. The material of the non-ohmic switching material layer may include a Figure 1D Any of the materials described for the non-ohmic switching material portion 12. The thickness of the non-ohmic switching material layer may range from 30 nm to 500 nm, such as from 60 nm to 300 nm, although lesser or greater thicknesses may also be used.

[0080] The non-ohmic switching material layer may be patterned photolithographically to form a non-ohmic switching material portion 12, the non-ohmic switching material portion 12 including a non-ohmic switching material plate 168 having a uniform thickness throughout. For example, a photoresist layer (not shown) may be applied over the non-ohmic switching material layer, and the photoresist layer may be patterned photolithographically to form discrete photoresist material portions extending between the first switch electrode 18 and the second switch electrode 10 and covering the end portion of the first switch electrode 18 and the end portion of the second switch electrode 10. An etching process may be performed to remove portions of the non-ohmic switching material layer that are not covered by the discrete photoresist material portions. The photoresist material portions may then be removed, for example, by ashing. The remainder of the non-ohmic switching material layer constitutes the non-ohmic switching material portion 12 (including the non-ohmic switching material plate 168).

[0081] In the third embodiment structure, the non-ohmic switching material portion 12 may be formed into a plate structure having a uniform thickness throughout, contacting a top surface section of the first switch electrode 18 , and contacting a top surface section of the second switch electrode 10 .

[0082] Reference Figure 3D , which can be implemented as a reference Figure 1F The processing steps are described to form the bonding level dielectric layer 660 and the metal pads 668. The metal pads 668 may include a signal input pad 668I and an electrostatic discharge pad 668D.

[0083] Generally speaking, the third embodiment structure can provide the same features as the first embodiment structure, except that the non-ohmic switch material portion 12 includes a non-ohmic switch material plate 168 instead of the non-ohmic switch material through-hole structure 152. In addition, the first switch electrode 18 and the second switch electrode 10 are formed on the same horizontal plane and can have the same thickness and the same material composition. The threshold voltage of the non-ohmic switch material portion 12 can be controlled by the lateral spacing between the first switch electrode 18 and the second switch electrode 10.

[0084] In one embodiment, the non-ohmic switching material portion 12 (including the non-ohmic switching material plate 168) includes a sidewall surface segment in contact with a first dielectric material layer (e.g., a bonding-level dielectric layer 660) selected from the dielectric material layers (601, 610, 620, 630, 640, 650, 660) of the third embodiment structure.

[0085] In one embodiment, the first switch electrode 18 contacts a first bottom surface segment of the non-ohmic switch material portion 12 and the second switch electrode 10 contacts a second bottom surface segment of the non-ohmic switch material portion 12. In one embodiment, the non-ohmic switch material portion 12 includes a non-ohmic switch material plate 168, which is located above a horizontal plane including a top surface of the first switch electrode 18 and a top surface of the second switch electrode 10. In one embodiment, the first switch electrode 18 and the second switch electrode 10 have top surface segments located in the horizontal plane, and the non-ohmic switch material portion 12 (including the non-ohmic switch material plate 168) includes a bottom surface that contacts the top surface segment of the first switch electrode 18 and the top surface segment of the second switch electrode 10. In one embodiment, the entire non-ohmic switch material portion 12 (including the non-ohmic switch material plate 168) has a uniform vertical thickness throughout.

[0086] 4A to 4D are sequential vertical cross-sectional views of a fourth embodiment structure of the present disclosure during formation of a device structure.

[0087] Reference Figure 4A , can be Figure 3B . In the fourth embodiment structure, all fifth conductive line structures 658 may be formed using the same material composition, which may be any material composition that may be used for the first conductive line structure 618, the second conductive line structure 628, the third conductive line structure 638, and / or the fourth conductive line structure 648. In an exemplary embodiment, the fifth conductive line structure 658 may include a combination of a metal barrier material (e.g., TiN, TaN, WN, MoN, TiC, TaC, WC, etc.) and a metal filling material (e.g., Cu, Al, Mo, W, Co, Ru, Ti, Ta, etc.).

[0088] A masking material layer 657 may be applied over the fifth interconnect level dielectric material layer 650. The masking material layer 657 may be a photoresist layer or may be a hard mask layer such as a silicon nitride layer. The masking material layer 657 may be patterned to cover all of the fifth conductive line structures 658, except for the conductive line structure 658 electrically connected to the semiconductor device 701 that needs to be protected from electrostatic discharge events and another conductive line structure 658 that forms a component within an electrostatic discharge path. In general, the conductive line structure 658 electrically connected to the semiconductor device 701 that needs to be protected from electrostatic discharge events and the conductive line structure 658 that forms a component within the electrostatic discharge path are laterally spaced apart by a lateral spacing that may be in a range from 30 nanometers to 1,000 nanometers (e.g., from 60 nanometers to 500 nanometers). The top surface of the conductive line structure 658 (electrically connected to the semiconductor device 701 to be protected from electrostatic discharge events) and the top surface of the conductive line structure 658 (forming a component in the electrostatic discharge path) are exposed adjacent to the lateral spacing between the two conductive line structures 658. The top surfaces of the two conductive line structures 658 may be fully or partially exposed to the opening in the masking material layer 657.

[0089] Reference Figure 4B , a selective metal deposition process may be performed to anisotropically grow metal plates (659A, 659B) from the physically exposed surfaces of the two conductive line structures 658. The selective metal deposition process may include at least one electroplating process or an area selective deposition (ASD) process, wherein the area selective deposition process deposits metal material only from the physically exposed metal surfaces while suppressing the growth of metal material from the physically exposed surfaces of the fifth interconnect level dielectric material layer 650 and the masking material layer 657.

[0090] A first switch electrode 18 is grown from a physically exposed top surface of a conductive line structure 658 that is electrically connected to a semiconductor device 701 that needs to be protected from electrostatic discharge events. A second switch electrode 10 is grown from a physically exposed top surface of a conductive line structure 658 that forms a component within an electrostatic discharge path. The first switch electrode 18 includes a first metal plate 659A, and the second switch electrode 10 includes a second metal plate 659B. In general, the first switch electrode 18 and the second switch electrode 10 may include any conductive material that can be selectively grown from the surfaces of the two conductive line structures 658. In one embodiment, the first switch electrode 18 and the second switch electrode 10 may include a metal material that can be electroplated. In one embodiment, the first switch electrode 18 and the second switch electrode 10 may include a conductive material that can be formed by an area selective deposition (ASD) process known to those skilled in the art. In one embodiment, the first switch electrode 18 and the second switch electrode 10 may be selected from reference Figure 1A The material used for the second switch electrode 10 of the structure of the first embodiment described above, and for the material, the electroplating process or the area selective deposition process are known.

[0091] According to aspects of the present disclosure, the growth of the first switch electrode 18 and the second switch electrode 10 can be continued until the lateral spacing between the first switch electrode 18 and the second switch electrode 10 reaches a target spacing s, which can be in the range of 20 nanometers to 300 nanometers (e.g., 40 nanometers to 100 nanometers), although smaller or larger target spacings can also be used. The masking material layer 657 can then be removed, for example, by ashing or by a wet etching process.

[0092] Reference Figure 4C , which can be implemented as a reference Figure 3C The processing steps described above are to form the non-ohmic switching material plate 168. Specifically, a non-ohmic switching material layer may be deposited and patterned to form the non-ohmic switching material plate 168 constituting the non-ohmic switching material portion 12. Thus, the non-ohmic switching material portion 12 may be formed into a plate structure having a downwardly protruding portion between the first switch electrode 18 and the second switch electrode 10. The non-ohmic switching material portion 12 contacts a top surface segment of the first switch electrode 18 and contacts a top surface segment of the second switch electrode 10.

[0093] Generally speaking, a pair of conductive lines (e.g., a pair of fifth conductive line structures 658) may be formed on the dielectric material layer (601, 610, 620, 630, 640), and the first switch electrode 18 and the second switch electrode 10 may be formed into metal plates (659A, 659B) by depositing metal material on the pair of conductive lines. The non-ohmic switch material portion 12 may be formed into a plate structure (e.g., non-ohmic switch material plate 168) between the first switch electrode 18 and the second switch electrode 10.

[0094] Reference Figure 4D , which can be implemented as a reference Figure 1F The processing steps are described to form the bonding level dielectric layer 660 and the metal pads 668. The metal pads 668 may include a signal input pad 668I and an electrostatic discharge pad 668D.

[0095] In general, the fourth embodiment structure can provide the same features as the third embodiment structure, except that the first switch electrode 18 is formed as a first metal plate 659A and the second switch electrode 10 is formed as a second metal plate 659B. In addition, the non-ohmic switch material portion 12 can be formed as a plate structure having a downwardly protruding portion located between the first switch electrode 18 and the second switch electrode 10. The non-ohmic switch material portion 12 contacts the top surface segment of the first switch electrode 18 and contacts the top surface segment of the second switch electrode 10. The first switch electrode 18 and the second switch electrode 10 are formed at the same level and can have the same thickness and the same material composition. The threshold voltage of the non-ohmic switch material portion 12 can be controlled by the lateral spacing between the first switch electrode 18 and the second switch electrode 10.

[0096] In one embodiment, the non-ohmic switching material portion 12 (including the non-ohmic switching material plate 168) includes a sidewall surface segment in contact with a first dielectric material layer (e.g., a bonding-level dielectric layer 660) selected from the dielectric material layers (601, 610, 620, 630, 640, 650, 660) of the fourth embodiment structure.

[0097] In one embodiment, the first switch electrode 18 contacts a first bottom surface segment of the non-ohmic switch material portion 12 and the second switch electrode 10 contacts a second bottom surface segment of the non-ohmic switch material portion 12. In one embodiment, the non-ohmic switch material portion 12 includes a non-ohmic switch material plate 168, which is located above a horizontal plane including the bottom surface of the first switch electrode 18 and the bottom surface of the second switch electrode 10. In one embodiment, the first switch electrode 18 and the second switch electrode 10 have bottom surface segments located in a horizontal plane (e.g., a horizontal plane including the top surface of the fifth interconnect level dielectric material layer 650), and the non-ohmic switch material portion 12 (including the non-ohmic switch material plate 168) includes a wavy bottom surface that contacts the top surface segments of the first switch electrode 18 and the second switch electrode 10. In one embodiment, a portion of the non-ohmic switching material portion 12 protrudes downward below a horizontal plane including top surface segments of the first switch electrode 18 and the second switch electrode and contacts side wall surface segments of the first switch electrode 18 and the second switch electrode 10 .

[0098] FIG. 5A to FIG. 5D are sequential vertical cross-sectional views of a fifth embodiment structure of the present disclosure during device formation.

[0099] Reference Figure 5A The structure of the fifth embodiment can be Figure 3B The structure of the third embodiment shown in FIG.

[0100] Reference Figure 5B A photoresist layer 757 may be applied over the top surface of the fifth interconnect level dielectric material layer 650 and the fifth conductive line structure 658, and the photoresist layer 757 may be patterned by photolithography to form discrete openings overlying the gap between the first switch electrode 18 (which is the fifth conductive line structure 658) and the second switch electrode 10 (which is another fifth conductive line structure 658). The lateral distance between the first switch electrode 18 and the second switch electrode 10 may be adjusted to optimize the threshold voltage of the non-ohmic switch material portion to be formed subsequently. The photoresist layer 757 may cover areas other than the combined area of ​​the first switch electrode 18, the second switch electrode 10, and the gap.

[0101] An etching process may be performed to remove the upper portion of the fifth interconnect level dielectric material layer 650 that is not masked by the photoresist layer 757. The etching process may include an anisotropic etching process (e.g., a reactive ion etching process) or an isotropic etching process (e.g., a wet etching process). A via cavity 179 is formed in each volume in which the material of the fifth interconnect level dielectric material layer 650 is removed. The sidewalls of the first switch electrode 18 and the sidewalls of the second switch electrode 10 may be physically exposed around the via cavity 179. The depth of the via cavity 179 may be greater than, less than, or equal to the height of the first switch electrode 18 and the second switch electrode 10. The photoresist layer 757 may then be removed, for example, by ashing.

[0102] Reference Figure 5C At least one non-ohmic switching material may be deposited in the via cavity 179, and excess portions of the at least one non-ohmic switching material may be removed from outside the via cavity 179 (i.e., from above the horizontal plane including the top surface of the fifth interconnection level dielectric material layer 650). The at least one non-ohmic switching material used in the structure of the fifth embodiment may be a material that can be used for reference. Figure 1D Any material among the non-ohmic switching materials of the non-ohmic switching material portion 12 is illustrated.

[0103] The remaining portion of the at least one non-ohmic switching material that fills the via cavity 179 constitutes a non-ohmic switching material portion 12, which is a non-ohmic switching material via structure 178 having a bottom surface that contacts the dielectric surface of the fifth interconnect level dielectric material layer 650. In one embodiment, the non-ohmic switching material via structure 178 may have a horizontal top surface that is completely located within a horizontal plane including the top surface of the fifth interconnect level dielectric material layer 650. The non-ohmic switching material via structure 178 may contact the sidewalls of the first switch electrode 18 and the sidewalls of the second switch electrode 10.

[0104] Generally speaking, the lateral dimensions and / or material composition of the non-ohmic switching material via structure 12 may be selected to optimize the threshold voltage of the non-ohmic switching material via structure 12 for switching from an off state to an on state.

[0105] Reference Figure 5D , which can be implemented as a reference Figure 1F The processing steps are described to form the bonding level dielectric layer 660 and the metal pads 668. The metal pads 668 may include a signal input pad 668I and an electrostatic discharge pad 668D.

[0106] In general, the fifth embodiment structure may provide the same features as the third embodiment structure, except that the non-ohmic switching material portion 12 is formed as a through-hole structure that contacts the sidewalls of the first switch electrode 18 and the sidewalls of the second switch electrode 10. The top surface of the non-ohmic switching material portion 12 (including the non-ohmic switching material through-hole structure 178) may be formed in the same horizontal plane as the top surface of the first switch electrode 18 and the top surface of the second switch electrode 10. The threshold voltage of the non-ohmic switching material portion 12 may be controlled by the lateral spacing between the first switch electrode 18 and the second switch electrode 10.

[0107] In one embodiment, the non-ohmic switching material portion 12 (including the non-ohmic switching material through-hole structure 178) includes a sidewall surface segment in contact with a first dielectric material layer (e.g., the fifth interconnection level dielectric material layer 650) selected from the dielectric material layers (601, 610, 620, 630, 640, 650, 660) of the fifth embodiment structure. In one embodiment, the non-ohmic switching material portion 12 includes: a first additional sidewall surface segment in contact with the sidewall of the first switch electrode 18 and a second additional sidewall surface segment in contact with the sidewall of the second switch electrode 10. In one embodiment, the non-ohmic switching material portion 12 has a top surface located at a horizontal plane including the top surface of the first switch electrode 18 and the top surface of the second switch electrode 10.

[0108] FIG. 6A to FIG. 6D are sequential vertical cross-sectional views of a sixth embodiment structure of the present disclosure during formation of a device structure.

[0109] Reference Fig. 6A , the pattern of the masking material layer 657 can be modified to match Figure 5B The pattern of the photoresist layer 757 in the fifth embodiment structure shown in FIG. Figure 4A The structure of the sixth embodiment is obtained by converting the structure of the fourth embodiment shown in FIG. Figure 5B The processing steps are described to form the via cavity 179. The photoresist layer 757 may then be removed, for example by ashing.

[0110] Reference Figure 6B , which can be implemented as a reference Figure 4B The processing steps are described to form the first switch electrode 18 and the second switch electrode 10 into the first metal plate 659A and the second metal plate 659B, respectively. In the sixth embodiment structure, the first switch electrode 18 is grown from the physically exposed top surface and physically exposed sidewalls of the conductive line structure 658 that is electrically connected to the semiconductor device 701 to be protected from electrostatic discharge events. The second switch electrode 10 is grown from the physically exposed top surface and physically exposed sidewalls of the conductive line structure 658 that form a component within the electrostatic discharge path.

[0111] According to aspects of the present disclosure, the growth of the first switch electrode 18 and the second switch electrode 10 can be continued until the lateral spacing between the first switch electrode 18 and the second switch electrode 10 reaches a target spacing s, which can be in a range from 20 nanometers to 300 nanometers (e.g., from 40 nanometers to 100 nanometers), although smaller or larger target spacings s can also be used. The masking material layer 657 can then be removed, for example, by ashing or by a wet etching process.

[0112] Reference Figure 6C At least one non-ohmic switching material may be deposited in the through hole cavity 179, and an excess portion of the at least one non-ohmic switching material may be removed from outside the through hole cavity 179 by performing a planarization process. The planarization process may include a chemical mechanical polishing process and / or a recess etching process. The at least one non-ohmic switching material used in the sixth embodiment structure may be a Figure 1D Any material among the non-ohmic switching materials of the non-ohmic switching material portion 12 is illustrated.

[0113] The remaining portion of the at least one non-ohmic switching material that fills the via cavity 179 constitutes a non-ohmic switching material portion 12, which is a non-ohmic switching material via structure 178 having a bottom surface that contacts the dielectric surface of the fifth interconnect level dielectric material layer 650. In one embodiment, depending on the recess depth of the non-ohmic switching material via structure 178 during the planarization process, the non-ohmic switching material via structure 178 may have a horizontal top surface that is completely above, below, or at a horizontal plane that includes the top surface of the fifth interconnect level dielectric material layer 650. The non-ohmic switching material via structure 178 may contact the sidewalls of the first switch electrode 18 and the sidewalls of the second switch electrode 10.

[0114] Generally speaking, the lateral dimensions and / or material composition of the non-ohmic switching material via structure 12 may be selected to optimize the threshold voltage of the non-ohmic switching material via structure 12 for switching from an off state to an on state.

[0115] Reference Fig.6D , which can be implemented as a reference Figure 1F The processing steps are described to form the bonding level dielectric layer 660 and the metal pads 668. The metal pads 668 may include a signal input pad 668I and an electrostatic discharge pad 668D.

[0116] In general, the sixth embodiment structure can provide the same features as the fourth embodiment structure, except that the non-ohmic switching material portion 12 is formed as a through-hole structure that contacts the sidewalls of the first switch electrode 18 and the sidewalls of the second switch electrode 10. The top surface of the non-ohmic switching material portion 12 (including the non-ohmic switching material through-hole structure 178) can be formed in a horizontal plane that is the top surface of the first switch electrode 18 and the top surface of the second switch electrode 10 or can be formed below the horizontal plane. The threshold voltage of the non-ohmic switching material portion 12 can be controlled by the lateral spacing between the first switch electrode 18 and the second switch electrode 10.

[0117] In one embodiment, the non-ohmic switching material portion 12 (including the non-ohmic switching material through-hole structure 178) includes a sidewall surface segment in contact with a first dielectric material layer (e.g., the fifth interconnection level dielectric material layer 650) selected from the dielectric material layers (601, 610, 620, 630, 640, 650, 660) of the fifth embodiment structure. In one embodiment, the non-ohmic switching material portion 12 includes: a first additional sidewall surface segment in contact with the sidewall of the first switch electrode 18 and a second additional sidewall surface segment in contact with the sidewall of the second switch electrode 10. In one embodiment, the non-ohmic switching material portion 12 has a top surface located at or below a horizontal plane including the top surface of the first switch electrode 18 and the top surface of the second switch electrode 10.

[0118] Common Reference FIG. 1A to FIG. 6D , the continuous combination of the first switch electrode 18, the second switch electrode 10 and the non-ohmic switch material portion 12 constitutes an electrostatic discharge (ESD) switch. In general, the electrostatic discharge (ESD) switch can be formed on a first dielectric material layer (601, 610, 620, 630, 640). The ESD switch includes: a first switch electrode 18, electrically connected to one of the semiconductor devices 701 through a subset of metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648); a second switch electrode 10, electrically isolated from the semiconductor device 701; and a non-ohmic switch material portion 12, providing non-ohmic current-voltage characteristics and contacting the first switch electrode 18 and the second switch electrode 10. The non-ohmic switch material portion 12 includes a bidirectional threshold material or a phase change memory material. Electrostatic discharge lines (e.g. Figure 1F and Figure 2D The electrostatic discharge line 648D shown in FIG. 1 or in other embodiments including a conductive line structure electrically connected to the electrostatic discharge pad 668D may be electrically connected to the second switch electrode 10 .

[0119] Reference Figure 7, a graph illustrates the current-voltage characteristics of the disclosed non-ohmic voltage-triggered switch (18, 12, 10) that can be used as an electrostatic discharge (ESD) switch. The disclosed non-ohmic voltage-triggered switch (18, 12, 10) is used as a passive self-turning device that turns on when an external voltage pulse having a magnitude exceeding a threshold voltage V_th of the non-ohmic switching material portion 12 is applied. The threshold voltage V_th can range from 3 volts to 50 volts, such as from 5 volts to 30 volts and / or 8 volts to 15 volts, although smaller or larger voltages can also be used.

[0120] In general, the non-ohmic voltage-triggered switch (18, 12, 10) includes: a first switch electrode 18 electrically connected to one of the semiconductor devices 701 by a subset of metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648), a second switch electrode 10, and a non-ohmic switch material portion 12 that provides non-ohmic current-voltage characteristics and contacts the first switch electrode 18 and the second switch electrode 10. When the applied external voltage does not exceed the threshold voltage V_th, the non-ohmic voltage-triggered switch (18, 12, 10) of the present disclosure functions as a high-resistance resistor. Once the magnitude of the applied external voltage exceeds the threshold voltage V_th, the non-ohmic voltage-triggered switch (18, 12, 10) transitions to an on state (i.e., a low-resistance state), which provides high conductivity and effectively functions as a conductor.

[0121] Various mechanisms may be used to effect transitions between high resistance and low resistance states of the non-ohmic voltage triggered switch (18, 12, 10). The present disclosure is not limited by any particular mechanism of operation of the non-ohmic switching material.

[0122] Reference Figure 8, illustrating the operation of the non-ohmic voltage-triggered switch (18, 12, 10) of the present disclosure as an electrostatic discharge (ESD) switch. The non-ohmic voltage-triggered switch (18, 12, 10) used as an ESD protection device is normally in an off state and does not affect the operation of a semiconductor circuit. In the case where a transient voltage having a magnitude greater than a threshold voltage of the non-ohmic voltage-triggered switch (18, 12, 10) is applied across the non-ohmic voltage-triggered switch (18, 12, 10), the non-ohmic voltage-triggered switch (18, 12, 10) is turned on (i.e., transitioned to a low-resistivity state). A transient current flows through the non-ohmic voltage-triggered switch (18, 12, 10) and can be directed to an electrical ground GND or a negative power supply voltage (e.g., V_ss) via an electrostatic discharge line. The input voltage transmitted to the semiconductor circuit is clamped at the threshold voltage of the non-ohmic voltage-triggered switch (18, 12, 10). In this way, the input voltage transmitted to the semiconductor circuit is clamped at the threshold voltage of the non-ohmic voltage-triggered switch (18, 12, 10), thereby protecting the semiconductor device in the semiconductor circuit.

[0123] The non-ohmic voltage-triggered switch (18, 12, 10) disclosed herein is a passive circuit that does not require any control device (e.g., field effect transistor). Generally speaking, a switch transistor that can handle large currents (e.g., handle transient currents during an ESD event) requires a large area. An ESD event as used herein refers to any transient charging event, including all ESD events and potential-induced degradation (PID) events. Therefore, an ESD protection scheme using a field effect transistor requires a large device area for controlling the transistor. The non-ohmic voltage-triggered switch (18, 12, 10) disclosed herein does not require any transistors and can be constructed entirely within a dielectric material layer as a back-end structure. In this way, the non-ohmic voltage-triggered switch (18, 12, 10) can provide area-efficient ESD protection.

[0124] Fig. 9 is a flow chart illustrating general processing steps for fabricating a device structure according to an embodiment of the present disclosure.

[0125] Refer to step 910 and Figure 1A , a semiconductor device 701 can be formed on the substrate 8.

[0126] Refer to step 920 and Figure 1A , a first metal interconnect structure ( 612 , 618 , 622 , 628 , 632 , 638 , 642 , 648 ) and a first dielectric material layer ( 601 , 610 , 620 , 630 , 640 ) may be formed on the semiconductor device 701 .

[0127] Refer to step 930 and Figure 1B As for 1E, FIG. 2A to FIG. 2C , FIG. 3A to FIG. 3C , FIG. 4A to FIG. 4C , FIG. 5A to FIG. 5C and FIG. 6A to FIG. 6C , an electrostatic discharge (ESD) switch (18, 12, 10) can be formed on the first dielectric material layer (601, 610, 620, 630, 640). The ESD switch (18, 12, 10) includes: a first switch electrode 18 electrically connected to one of the semiconductor devices 701 through a subset of metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648), a second switch electrode 10 electrically isolated from the semiconductor device 701, and a non-ohmic switch material portion 12 that provides non-ohmic current-voltage characteristics and contacts the first switch electrode 18 and the second switch electrode 10. In one embodiment, the non-ohmic switch material portion 12 includes a bidirectional threshold material or a phase change memory material.

[0128] Refer to step 940 and Figure 1F , Figure 2D , Figure 3D , Figure 4D , Figure 5D and Fig.6D , an electrostatic discharge line can be formed. The electrostatic discharge line is electrically connected to the second switch electrode 10. The electrostatic discharge line can be used as any set of metal interconnect structures electrically connected (i.e., electrically short-circuited) to the electrostatic discharge pad 668D or can be used as any alternative electrostatic discharge structure, such as an electrostatic discharge line, an electrostatic discharge plate, an electrostatic discharge metal frame, etc.

[0129] Referring to all the drawings and according to various embodiments of the present disclosure, a device structure is provided, including: a semiconductor device 701 located on a substrate 8, a metal interconnect structure (612, 618, 622, 628, 632, 638, 642, 648) located in a dielectric material layer (601, 610, 620, 630, 640, 650, 660) overlying the semiconductor device 701, and a non-ohmic voltage-triggered switch (18, 12, 10), wherein the non-ohmic voltage-triggered switch The switch includes a first switch electrode 18, a second switch electrode 10 and a non-ohmic switch material portion 12, the first switch electrode 18 is electrically connected to one of the semiconductor devices 701 via a subset of metal internal connection structures (612, 618, 622, 628, 632, 638, 642, 648), and the non-ohmic switch material portion 12 is electrically connected to the first switch electrode 18 and the second switch electrode 10, wherein the non-ohmic switch material portion 12 can be configured to provide non-ohmic current-voltage characteristics.

[0130] In one embodiment, the non-ohmic switching material portion 12 includes a sidewall surface segment in contact with a first dielectric material layer selected from the dielectric material layers ( 601 , 610 , 620 , 630 , 640 , 650 , 660 ).

[0131] In an embodiment, the first switch electrode 18 contacts a top surface of the non-ohmic switching material portion 12 , and the second switch electrode 10 contacts a bottom surface of the non-ohmic switching material portion 12 .

[0132] In one embodiment, the non-ohmic switching material portion 12 includes the through-hole structure 652 , and the entire top surface of the non-ohmic switching material portion 12 contacts a section of the bottom surface of the first switching electrode 18 .

[0133] In one embodiment, the non-ohmic switching material portion 12 includes a via liner 162 located in a peripheral portion of the via opening 159 , and the second switch electrode 10 includes a portion located in an inner portion of the via opening 159 and contacting an inner sidewall of the via liner 162 .

[0134] In one embodiment, the first switch electrode 18 and the second switch electrode 10 have top surface segments located in a horizontal plane, and the non-ohmic switching material portion 12 includes a bottom surface in contact with the top surface segment of the first switch electrode 18 .

[0135] In one embodiment, the entire non-ohmic switching material portion 12 has a uniform vertical thickness throughout.

[0136] In one embodiment, a portion of the non-ohmic switching material portion 12 protrudes downward below a horizontal plane including top surface segments of the first switch electrode 18 and the second switch electrode and contacts side wall surface segments of the first switch electrode 18 and the second switch electrode 10 .

[0137] In an embodiment, the non-ohmic switching material portion 12 includes a first additional sidewall surface segment contacting a sidewall of the first switch electrode 18 and a second additional sidewall surface segment contacting a sidewall of the second switch electrode 10 .

[0138] In an embodiment, the non-ohmic switching material portion 12 has a top surface located at or below a horizontal plane including a top surface of the first switch electrode 18 and a top surface of the second switch electrode 10 .

[0139] In one embodiment, the non-ohmic switching material portion 12 includes a bidirectional threshold material or a phase change memory material.

[0140] According to another aspect of the present disclosure, a device structure is provided, the device structure comprising: a semiconductor device 701 located on a substrate 8, a first metal interconnect structure (612, 618, 622, 628, 632, 638, 642, 648) located in a first dielectric material layer (601, 610, 620, 630, 640) overlying the semiconductor device 701, an electrostatic discharge line (which may be an electrostatic discharge pad 668D or any alternative electrostatic discharge structure, such as an electrostatic discharge line, an electrostatic discharge plate, an electrostatic discharge metal frame, etc.) overlying the first dielectric material layer (601, 610, 620, 630, 640), and a first metal interconnect structure (612, 618, 622, 628, 632, 638, 642, 648) overlying the first dielectric material layer (601, 610, 620, 630, 640). An electrostatic discharge (ESD) switch on the semiconductor device 701 is provided with a first switch electrode 18, a second switch electrode 10 and a non-ohmic switch material portion 12. The first switch electrode 18 is electrically connected to one of the semiconductor devices 701 through a subset of the first metal interconnect structure (612, 618, 622, 628, 632, 638, 642, 648). The second switch electrode 10 is electrically connected to the electrostatic discharge line 668D. The non-ohmic switch material portion 12 provides non-ohmic current-voltage characteristics and contacts the first switch electrode 18 and the second switch electrode 10, wherein the non-ohmic switch material portion 12 includes a bidirectional threshold material or a phase change memory material.

[0141] In one embodiment, the second switch electrode 10 includes a first conductive wire; the first switch electrode 18 includes a second conductive wire, and the non-ohmic switch material portion 12 includes a through-hole structure 152 that is laterally surrounded by a second dielectric material layer, the second dielectric material layer overlying the first dielectric material layer (601, 610, 620, 630, 640) and contacting the bottom surface of the first switch electrode 18 and contacting the top surface of the second switch electrode 10.

[0142] In one embodiment, the second switch electrode 10 includes: a first conductive line; a non-ohmic switching material portion 12, including a through-hole liner 162, which is located in a peripheral portion of a through-hole opening 159 in a second dielectric material layer overlying the first dielectric material layer (601, 610, 620, 630, 640), and the first switch electrode 18 includes a second conductive line, which includes a downward protruding portion, which is located in an inner portion of the through-hole opening 159 and contacts the inner side wall of the through-hole liner 162.

[0143] In one embodiment, the first switch electrode 18 and the second switch electrode 10 include a conductive wire, which is overlying a first dielectric material layer (601, 610, 620, 630, 640) and the first switch electrode 18 and the second switch electrode 10 have a top surface segment located in a horizontal plane, and the non-ohmic switching material portion 12 includes a plate structure 168 or a through-hole structure 152 located between the first switch electrode 18 and the second switch electrode 10.

[0144] In one embodiment, the first switch electrode 18 and the second switch electrode 10 include metal plates (659A, 659B) located on corresponding conductive lines, the metal plates (659A, 659B) are overlying a first dielectric material layer (601, 610, 620, 630, 640), and the non-ohmic switching material portion 12 contacts the side walls of the first switch electrode 18 and the side walls of the second switch electrode 10.

[0145] According to some embodiments, a method for forming a semiconductor device structure includes: forming a plurality of semiconductor devices on a substrate; forming a first metal interconnect structure and a first dielectric material layer above the semiconductor devices; forming an electrostatic discharge switch above the first dielectric material layer, wherein the electrostatic discharge switch includes a first switch electrode, a second switch electrode, and a non-ohmic switch material portion, the first switch electrode being electrically connected to one of the semiconductor devices via a subset of the first metal interconnect structure, the second switch electrode being electrically isolated from the semiconductor device, the non-ohmic switch material portion providing a non-ohmic current-voltage characteristic and contacting the first switch electrode and the second switch electrode, wherein the non-ohmic switch material portion includes a bidirectional threshold material or a phase change memory material; and forming an electrostatic discharge line, wherein the electrostatic discharge line is electrically connected to the second switch electrode.

[0146] In some embodiments, the second switch electrode is formed as a first conductive line, the non-ohmic switch material portion is formed as a through-hole structure directly on the top surface of the second switch electrode, and the first switch electrode is formed as a second conductive line on the top surface of the non-ohmic switch material portion. In some embodiments, the first switch electrode and the second switch electrode are formed as conductive lines overlying the first dielectric material layer, and the non-ohmic switch material portion is formed as a plate structure or a through-hole structure between the first switch electrode and the second switch electrode. In some embodiments, the method further includes: forming a pair of conductive lines on the first dielectric material layer; forming the first switch electrode and the second switch electrode into metal plates by depositing a metal material on the pair of conductive lines; and the non-ohmic switch material portion is formed as a plate structure or a through-hole structure between the first switch electrode and the second switch electrode.

[0147] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the utility model, rather than to limit them. Although the embodiments of the utility model are described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the embodiments of the utility model.

Claims

1. A semiconductor device structure, characterized in that: include: a plurality of semiconductor devices disposed on a substrate; a plurality of metal interconnect structures disposed in a plurality of dielectric material layers overlying the semiconductor device; as well as Non-ohmic voltage-triggered switches, including: a first switch electrode electrically connected to one of the semiconductor devices via a subset of the metal interconnect structures; a second switch electrode; and A non-ohmic switching material portion is electrically connected to the first switch electrode and the second switch electrode, wherein the non-ohmic switching material portion is configured to provide a non-ohmic current-voltage characteristic.

2. The semiconductor device structure according to claim 1, wherein: The non-ohmic switching material portion includes a sidewall surface segment in contact with a first dielectric material layer selected from the dielectric material layers.

3. The semiconductor device structure according to claim 2, wherein: in: The first switch electrode contacts a top surface of the non-ohmic switch material portion; as well as The second switching electrode contacts a bottom surface of the non-ohmic switching material portion.

4. The semiconductor device structure according to claim 2, wherein: in: The first switch electrode and the second switch electrode have top surface segments that lie in a horizontal plane; and The non-ohmic switching material portion includes a bottom surface in contact with the top surface segment of the first switching electrode.

5. The semiconductor device structure according to claim 2, wherein: The non-ohmic switch material part comprises: a first additional sidewall surface segment contacting a sidewall of the first switch electrode; and A second additional side wall surface segment contacts a side wall of the second switch electrode.

6. A semiconductor device structure, characterized in that: include: a plurality of semiconductor devices disposed on a substrate; A first metal interconnect structure located in a first dielectric material layer overlying the semiconductor device; an electrostatic discharge line, overlying the first dielectric material layer; as well as An electrostatic discharge switch, overlying the first dielectric material layer, the electrostatic discharge switch comprising: a first switch electrode electrically connected to one of the semiconductor devices via a subset of the first metal interconnect structures; A second switch electrode electrically connected to the electrostatic discharge line; and The non-ohmic switch material portion provides a non-ohmic current-voltage characteristic and contacts the first switch electrode and the second switch electrode, wherein the non-ohmic switch material portion includes a bidirectional threshold material or a phase change memory material.

7. The semiconductor device structure according to claim 6, wherein: in: The second switch electrode includes a first conductive line; The first switch electrode includes a second conductive line; and The non-ohmic switching material portion includes a via structure laterally surrounded by a second dielectric material layer, the second dielectric material layer overlying the first dielectric material layer and contacting a bottom surface of the first switch electrode and contacting a top surface of the second switch electrode.

8. The semiconductor device structure according to claim 6, wherein: in: The second switch electrode includes a first conductive line; the non-ohmic switching material portion comprising a via liner located in a peripheral portion of a via opening in a second dielectric material layer overlying the first dielectric material layer; as well as The first switch electrode includes a second conductive line including a downwardly protruding portion located in an inner portion of the via opening and contacting an inner sidewall of the via liner.

9. The semiconductor device structure according to claim 6, wherein: in: The first switch electrode and the second switch electrode include a conductive line, the conductive line overlies the first dielectric material layer and the first switch electrode and the second switch electrode have a top surface segment located in a horizontal plane; as well as The non-ohmic switching material portion includes a plate structure or a via structure between the first switching electrode and the second switching electrode.

10. The semiconductor device structure according to claim 6, wherein: in: The first switch electrode and the second switch electrode include metal plates located on corresponding conductive lines, and the metal plates are overlaid on the first dielectric material layer; as well as The non-ohmic switching material partially contacts a sidewall of the first switch electrode and a sidewall of the second switch electrode.

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