Ripple compensation circuit suitable for RB-COT control architecture BUCK converter

Abstract

The utility model provides a ripple compensation circuit suitable for an RB-COT control architecture BUCK converter, and relates to the technical field of power electronics. Comprising an inductive current ripple sampling circuit and a direct current offset elimination circuit. The inductive current ripple sampling circuit samples inductive current and inputs the sampled inductive current into the direct current offset elimination circuit; the direct current offset elimination circuit eliminates the direct current offset existing in the sampled inductive current ripple signal, so that only the alternating current in the inductive current ripple information is superposed on the feedback voltage. The superposed inductive current ripples and ESR resistance ripples have the same frequency and the same phase, so that the converter has good stability even if the external capacitance ESR is very small, and the ripples processed by the direct current offset elimination circuit do not contain direct current offset, and can meet the requirement of high-precision output voltage.

Description

Technical Field

[0001] The utility model relates to the technical field of power electronics, and in particular to a ripple compensation circuit suitable for a BUCK converter of a RB-COT control architecture. Background Art

[0002] With the rapid development of science and technology, multifunctional electronic products realized by integrated circuits have quickly penetrated into people's lives. These electronic devices need an efficient and reliable power supply solution to support the normal operation of the equipment. Among various power supply solutions, the DC-DC converter has the most significant advantage. It can provide a large load current driving capability, consume less static current and have high conversion efficiency. In recent years, the RB-COT control architecture applied to DC-DC converters has been widely used because of its higher light-load efficiency, faster transient response speed and wider bandwidth.

[0003] like Figure 1 The principle block diagram and key waveform diagram of the traditional RB-COT control architecture BUCK converter. Its trigger mechanism is that when the feedback voltage V FB Touch V REF When the comparator flips, the upper power tube S1 turns on, and the turn-on time is determined by the timer in the COT generation circuit. The traditional RB-COT control architecture requires a large output voltage ripple to stabilize the loop. This ripple is generated by the ESR resistor, which makes the control architecture dependent on a large ESR resistor. However, with the demand for integration, low ESR and small chip capacitors have become the mainstream, which limits the applicability of the RB-COT control architecture. Therefore, an internal ripple compensation circuit can be configured for the RB-COT control architecture, but it is inevitable that the compensated ripple will bring DC offset to the loop and affect the accuracy of the output voltage.

[0004] In the existing related technologies, the ripple compensation circuit usually lacks a high-precision DC offset elimination circuit, which causes the output voltage to have a large DC offset, and ultimately it is difficult to meet the requirements of high-precision output voltage. Utility Model Content

[0005] In order to solve the above problems existing in the existing RB-COT control architecture BUCK converter, the utility model proposes a ripple compensation circuit suitable for the RB-COT control architecture BUCK converter, aiming to ensure the stability of the converter while eliminating DC offset and improving the accuracy of the output voltage.

[0006] In order to achieve the above purpose, the utility model provides the following technical solutions:

[0007] A ripple compensation circuit suitable for a RB-COT control architecture BUCK converter includes an inductor current ripple sampling circuit and a DC offset elimination circuit. The inductor current ripple sampling circuit samples the inductor current and inputs it into the DC offset elimination circuit; the DC offset elimination circuit eliminates the DC offset in the sampled inductor current ripple signal, so that only the AC quantity in the inductor current ripple information is superimposed on the feedback voltage. The superimposed ripple improves the stability of the circuit by equivalently increasing the ESR resistance, and the ripple processed by the DC offset elimination circuit does not contain the DC offset, which can meet the requirements of high-precision output voltage.

[0008] Specifically, the inductor current ripple sampling circuit includes: an inductor L, an inductor series R L , sampling resistor R sense , sampling capacitor C sense The switch node SW is connected to one end of the inductor L and the sampling resistor R sense The other end of the inductor L is connected to the inductor series resistor R L ; Inductor series R L The other end of the sampling capacitor C sense connected, and its connection point is connected to the output voltage terminal V out ; Sampling resistor R sense The other end of the sampling capacitor C sense The other end is connected to the node V s , V s Serves as a connection node between the inductor current ripple sampling circuit and the DC offset elimination circuit.

[0009] Specifically, the DC offset elimination circuit includes: feedback resistor R2, feedback resistor R3, low-pass filter LPF1, low-pass filter LPF2, adder SUM1, adder SUM2, adder SUM3, operational amplifier A, NMOS tube MEX1, NMOS tube MEX2 and resistor R9. One end of the feedback resistor R2 is connected to the output voltage terminal V out The other end of the feedback resistor R2, one end of the feedback resistor R3, and the positive input end of the superimposer SUM3 are connected to the input end of the low-pass filter LPF2, and the connection point is used as the feedback voltage node V FB ; The other end of the feedback resistor R3 is grounded GND; The output end V of the low-pass filter LPF2 is connected to FB（dc） As the negative input terminal of the adder SUM3 and the negative input terminal of the adder SUM2; the output terminal of the adder SUM3 is connected to the positive input terminal of the adder SUM1; the other positive input terminal of the adder SUM2 is connected to the reference voltage V REF The input of the low-pass filter LPF1, the positive input of the adder SUM1, the drain of the NMOS tube MEX2 and the positive input of the operational amplifier are connected to the node VS The gate of the NMOS tube MEX2 and the gate of the NMOS tube MEX1 are connected to the output end of the operational amplifier A; the source of the NMOS tube MEX2 and the source of the NMOS tube MEX1 are connected to the ground GND; one end of the resistor R9 is connected to the output voltage terminal V out ; The other end of the resistor R9 and the drain of the NMOS tube MEX1 are connected to the negative input terminal of the operational amplifier A; the output terminal of the low-pass filter LPF1 is connected to the other positive input terminal of the adder SUM2; the output terminal of the adder SUM2 is connected to the positive terminal of the comparator; the output terminal of the adder SUM1 is connected to the negative terminal of the comparator.

[0010] Specifically, the low-pass filter LPF1 is composed of a resistor R7 and a capacitor C4.

[0011] Specifically, the low-pass filter LPF2 is composed of a resistor R8 and a capacitor C5.

[0012] Specifically, the resistor R9 and the sampling resistor R sense The resistance values ​​are equal.

[0013] Specifically, the width-to-length ratios of the NMOS tube MEX1 and the NMOS tube MEX2 are equal.

[0014] Specifically, the adder SUM1 includes two positive input terminals; the adder SUM2 includes two positive input terminals and one negative input terminal; and the adder SUM3 includes one positive input terminal and one negative input terminal.

[0015] Compared with the prior art, the utility model has the following beneficial effects: the utility model provides a ripple compensation circuit suitable for a RB-COT control architecture BUCK converter, which collects information about the inductor current ripple through an inductor current ripple sampling circuit to obtain a sampling circuit that is in a certain proportional relationship with the inductor current, thereby ensuring that the sampling current and the inductor current have the same phase information, and at the same time, the ratio of the sampling current to the inductor current is a fixed constant, which is independent of the on-resistance impedance of the power tube, that is, the influence of the process and temperature is eliminated, and finally the sampling current is input into a DC offset elimination circuit; the DC offset elimination circuit first extracts the DC amount in the inductor current ripple and the feedback voltage respectively through two low-pass filters, and then directly eliminates the DC amount in the inductor current ripple based on the equation relationship between the three adders, so that only the AC amount in the inductor current ripple and the reference voltage are superimposed on the input end of the comparator, and the clamping relationship of the operational amplifier A is utilized, by designing the resistor R9 and the sampling resistor R senseThe resistance value can extract the DC amount in the inductor current ripple that is not removed by the filter, further ensuring that the superimposed inductor current ripple only contains AC amount and no DC amount. Therefore, by superimposing the inductor current ripple on the reference voltage, the ESR resistance R of the output capacitor is equivalently increased. ESR , eliminating the ESR The phase lag phenomenon caused by the smaller ripple can improve the stability of the system, thereby solving the subharmonic oscillation problem of the converter, and the DC offset elimination circuit can make the output voltage have high accuracy, solving the DC offset problem caused by the traditional ripple compensation circuit. In the entire ripple compensation circuit, all circuits have a large linear input range, ensuring that the ripple compensation is not affected in the application of large current and high power tube on-resistance, and the parameters of each device can be easily selected, which greatly improves the applicability of the RB-COT architecture BUCK converter. The ripple compensation circuit suitable for the RB-COT control architecture BUCK converter provided by the embodiment of the utility model overcomes the subharmonic oscillation problem of the RB-COT control architecture BUCK converter, maintains good stability, and improves the DC offset caused by the traditional ripple compensation method, greatly improving the circuit accuracy. Compared with the traditional RB-COT control architecture BUCK converter, the utility model gets rid of the dependence on the ESR resistance of the output capacitor, broadens the optional range of the output capacitor, and increases the flexibility of circuit design; compared with the off-chip ripple compensation circuit, it reduces the use of components and reduces the cost; compared with other on-chip compensation circuits, while ensuring the stability of the system, it also improves the circuit accuracy, so that the accuracy of the output voltage is not affected by the on-chip ripple compensation circuit, and the scope of application of the circuit is increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is the system block diagram and key waveform diagram of the traditional RB-COT control architecture BUCK converter.

[0017] Figure 2 The utility model provides a ripple compensation circuit system block diagram suitable for a BUCK converter with an RB-COT control architecture.

[0018] Figure 3 The utility model provides a ripple compensation circuit implementation diagram suitable for a BUCK converter with an RB-COT control architecture.

[0019] FIG4(a) is a simulation waveform diagram of a ripple compensation circuit suitable for a RB-COT control architecture BUCK converter provided by the present invention; FIG4(b) is a simulation waveform diagram under the same parameters without adding the ripple compensation circuit provided by the present invention. DETAILED DESCRIPTION

[0020] The utility model is further described below in conjunction with the accompanying drawings and specific embodiments.

[0021] The utility model proposes a ripple compensation circuit system block diagram suitable for RB-COT control architecture BUCK converter Figure 2 As shown, it mainly consists of two parts: the inductor current ripple sampling circuit and the DC offset elimination circuit. The inductor current ripple sampling circuit samples the inductor current and inputs it into the DC offset elimination circuit; the DC offset elimination circuit eliminates the DC offset in the sampled inductor current ripple signal, so that only the AC quantity in the inductor current ripple information is superimposed on the feedback voltage. The superimposed ripple improves the stability of the circuit by equivalently increasing the ESR, and the ripple after being processed by the DC offset elimination circuit does not contain the DC offset, which can meet the requirements of high-precision output voltage. The specific functions and principles of each part of the circuit will be described in detail in combination with the following actual circuit.

[0022] The inductor current ripple sampling circuit is as follows Figure 3 The ripple sampling part of the circuit implementation diagram is shown as follows, including: inductor L, inductor series resistor R L , sampling resistor R sense , sampling capacitor C sense The switch node SW is connected to one end of the inductor L and the sampling resistor R sense The other end of the inductor L is connected to the inductor parasitic resistance R L ; Inductor parasitic resistance R L The other end of the sampling capacitor C sense connected, and its connection point is connected to the output voltage terminal V out ; Sampling resistor R sense The other end of the sampling capacitor C sense The other end is connected to the node V s , V s As the connection node between the inductor current ripple sampling circuit and the DC offset elimination circuit. Considering that the phase of the inductor current is 90° different from the phase of the capacitor ripple, and the inductor current and the resistor ripple are in phase, it is possible to collect the ripple information on the inductor and inject it into the feedback voltage V FB The above method can increase ESR equivalently to improve the stability of the system. Among them:

[0023]

[0024] When R S C S =L / R L When the voltage on the sampling capacitor is equal to R LThe voltage on the inductor can be accurately sampled without reducing the conversion efficiency of the system when the time constant is matched. However, it is inevitable that the sampled inductor current includes a DC component in addition to the AC component, which will cause the output voltage to shift. From the time domain analysis, combined with the relevant formula of the valley control BUCK converter, and let k be the voltage division ratio of the output voltage: V FB =KV OUT , we can get:

[0025]

[0026] The output voltage is:

[0027]

[0028] It can be seen that the inductor current ripple sampling circuit can sample the ripple of the inductor current. This ripple has the same frequency and phase as the ESR resistance ripple. Therefore, after it is superimposed on the feedback voltage, it is equivalent to increasing the ESR resistance, which improves the stability of the converter. However, it will bring a DC offset factor V to the converter that affects the output voltage accuracy. Sence（dc） .

[0029] The DC offset elimination circuit is as follows Figure 3 The circuit implementation diagram shows the DC offset elimination part, including: feedback resistor R2, feedback resistor R3, low-pass filter LPF1, low-pass filter LPF2, superimposer SUM1, superimposer SUM2, superimposer SUM3, operational amplifier A, NMOS tube MEX1, NMOS tube MEX2 and resistor R9. One end of the feedback resistor R2 is connected to the output voltage terminal V out The other end of the feedback resistor R2, one end of the feedback resistor R3, and the positive input end of the superimposer SUM3 are connected to the input end of the low-pass filter LPF2, and the connection point is used as the feedback voltage node V FB ; The other end of the feedback resistor R3 is grounded GND; The output end V of the low-pass filter LPF2 is connected to FB（dc） As the negative input terminal of the adder SUM3 and the negative input terminal of the adder SUM2; the output terminal of the adder SUM3 is connected to the positive input terminal of the adder SUM1; the other positive input terminal of the adder SUM2 is connected to the reference voltage V REF The input of the low-pass filter LPF1, the positive input of the adder SUM1, the drain of the NMOS tube MEX2 and the positive input of the operational amplifier are connected to the node V S The gate of the NMOS tube MEX2 and the gate of the NMOS tube MEX1 are connected to the output end of the operational amplifier A; the source of the NMOS tube MEX2 and the source of the NMOS tube MEX1 are connected to the ground GND; one end of the resistor R9 is connected to the output voltage terminal V out; The other end of the resistor R9 and the drain of the NMOS tube MEX1 are connected to the negative input end of the operational amplifier A; the output end of the low-pass filter LPF1 is connected to the other positive input end of the superimposer SUM2; the output end of the superimposer SUM2 is connected to the positive end of the comparator; the output end of the superimposer SUM1 is connected to the negative end of the comparator. Among them, the low-pass filter LPF1 is composed of a resistor R7 and a capacitor C4, the low-pass filter LPF2 is composed of a resistor R8 and a capacitor C5, the width-to-length ratio of the NMOS tube MEX1 is equal to that of the NMOS tube MEX2, and the resistor R9 and the sampling resistor R sense The resistance values ​​are equal, the adder SUM1 includes two positive input terminals, the adder SUM2 includes two positive input terminals and one negative input terminal, and the adder SUM3 includes one positive input terminal and one negative input terminal. s As the sampling point, the detection signal V sense and V out composition:

[0030]

[0031] Low-pass filters LPF1 and LPF2 remove V S and V FB The DC component in the summation is:

[0032]

[0033]

[0034]

[0035] The output voltage at this time can be obtained as:

[0036]

[0037] It can be seen that the output voltage does not include V sense（dc） The term is used to offset the DC offset after adding ripple compensation, and the problem of insufficient ripple compensation can be solved, so that the system can be applied to low ESR situations. Operational amplifier A, NMOS tube MEX1, NMOS tube MEX2 and resistor R9 are used to extract V s The DC offset that cannot be removed due to the limitation of filter parameter selection makes the parameter selection range of filter LPF1 and filter LPF2 wider and more applicable. Among them, the width-to-length ratio of NMOS tube MEX1 and NMOS tube MEX2 is the same, and the gate voltage and source voltage are also the same, which can make the current I1 flowing through NMOS tube MEX1 equal to the current I2 flowing through NMOS tube MEX2. Combined with the positive and negative terminal clamping effect of operational amplifier A, the current can be obtained:

[0038]

[0039]

[0040] At this time, the DC amount that has not been filtered out of the current I3 can be extracted, and only the AC amount is sense It charges and generates an inductor current ripple with the same frequency and phase as the ESR ripple.

[0041] FIG4(a) is a simulation waveform diagram of the ripple compensation circuit designed by the present invention applied to the RB-COT control architecture BUCK converter under the actual ultra-low ESR resistance condition, and FIG4(b) is a simulation waveform diagram under the same parameter conditions without the ripple compensation circuit designed by the present invention. By comparing the two, it can be seen that: when the ripple compensation circuit is not added, the converter cannot generate sufficient output voltage ripple to support the stable operation of the converter due to the low ESR, thereby causing multiple pulse bursts and subharmonic oscillations; after adding the ripple compensation circuit designed by the present invention, the inductor current ripple with the same frequency and phase as the ESR resistance is superimposed on the feedback voltage, which can make the converter still have sufficient feedback voltage ripple to support its stable operation even under the ultra-low ESR resistance condition, and will not cause multiple pulse bursts and subharmonic oscillations, and the output voltage ripple is less than 2mV, which can be regarded as the DC offset only existing in the converter main circuit itself, but not in the ripple compensation circuit, that is, the ripple compensation circuit designed by the present invention will not introduce new DC offset to the converter. Therefore, based on the analysis of the simulation waveform, it can be seen that after the converter is added with the ripple compensation circuit designed by the utility model, it still has good stability and high output voltage accuracy even under ultra-low ESR resistance conditions.

[0042] The utility model designs a ripple compensation circuit suitable for RB-COT control architecture BUCK converter. This ripple compensation circuit makes the RB-COT control architecture BUCK converter no longer dependent on the size of the output capacitor ESR, and broadens the optional range of output capacitor components. The ripple compensation technology proposed by the utility model avoids the large off-chip resistors and large capacitors required by the traditional slope compensation technology; at the same time, the compensated inductor current ripple and the ESR resistor ripple are in the same frequency and phase, so that the converter can remain stable even under very small ESR conditions; in addition, the DC offset elimination circuit improves the DC offset error caused by the traditional ripple compensation method and improves the circuit accuracy.

[0043] Finally, it should be noted that the embodiments described above are only used to help readers understand the working principle of the utility model, rather than to limit it; ordinary technicians in this field should understand that under the idea of ​​this utility model, the technical features in the embodiments described above can also be combined, or some of the technical features can be replaced, and these combinations and replacements are still within the protection scope of the utility model.

Claims

1. A ripple compensation circuit suitable for a RB-COT control architecture BUCK converter, comprising an inductor current ripple sampling circuit and a DC offset elimination circuit, characterized in that: The DC offset elimination circuit comprises: a feedback resistor R2, a feedback resistor R3, a low-pass filter LPF1, a low-pass filter LPF2, a superimposer SUM1, a superimposer SUM2 and a superimposer SUM3; one end of the feedback resistor R2 is connected to the output voltage terminal V out The other end of the feedback resistor R2, one end of the feedback resistor R3, and the positive input end of the superimposer SUM3 are connected to the input end of the low-pass filter LPF2, and the connection point is used as the feedback voltage node V FB ; The other end of the feedback resistor R3 is grounded GND; The output end V of the low-pass filter LPF2 is connected to FB As the negative input terminal of the adder SUM3 and the negative input terminal of the adder SUM2; the output terminal of the adder SUM3 is connected to the positive input terminal of the adder SUM1; the other positive input terminal of the adder SUM2 is connected to the reference voltage V REF The input of the low-pass filter LPF1 and the positive input of the adder SUM1 are connected to the node V S The low-pass filter LPF1 is composed of a resistor R7 and a capacitor C4; the low-pass filter LPF2 is composed of a resistor R8 and a capacitor C5.

2. A ripple compensation circuit suitable for a RB-COT control architecture BUCK converter according to claim 1, characterized in that: The adder SUM1 includes two positive input terminals; the adder SUM2 includes two positive input terminals and one negative input terminal; the adder SUM3 includes one positive input terminal and one negative input terminal.

3. A ripple compensation circuit suitable for a RB-COT control architecture BUCK converter according to claim 2, characterized in that: The DC offset elimination circuit also includes an operational amplifier A, an NMOS tube MEX1, an NMOS tube MEX2 and a resistor R9.

4. A ripple compensation circuit suitable for a RB-COT control architecture BUCK converter according to claim 3, characterized in that: The drain of NMOS tube MEX2 and the positive input terminal of the operational amplifier are connected to the node V S The gate of the NMOS tube MEX2 and the gate of the NMOS tube MEX1 are connected to the output end of the operational amplifier A; the source of the NMOS tube MEX2 and the source of the NMOS tube MEX1 are connected to the ground GND; one end of the resistor R9 is connected to the output voltage terminal V out The other end of the resistor R9 and the drain of the NMOS tube MEX1 are connected to the negative input terminal of the operational amplifier A.

5. The ripple compensation circuit suitable for RB-COT control architecture BUCK converter according to claim 3, characterized in that: The width-to-length ratios of the NMOS tube MEX1 and the NMOS tube MEX2 are equal, so that the current flowing through the NMOS tube MEX1 is equal to the current flowing through the NMOS tube MEX2.

6. A ripple compensation circuit suitable for a RB-COT control architecture BUCK converter according to claim 3, characterized in that: The inductor current ripple sampling circuit comprises: an inductor L, an inductor series resistor R L , sampling resistor R sense and sampling capacitor C sense .

7. A ripple compensation circuit suitable for a RB-COT control architecture BUCK converter according to claim 6, characterized in that: One end of the inductor L and the sampling resistor R sense One end of the inductor L is connected to the switch node SW; the other end of the inductor L is connected to the inductor series resistor R L ; Inductor series resistance R L The other end of the sampling capacitor C sense connected, and its connection point is connected to the output voltage terminal V out ; Sampling resistor R sense The other end of the sampling capacitor C sense The other end is connected to the node V s .

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