LLC synchronous rectification circuit

Abstract

According to the LLC synchronous rectification circuit provided by the utility model, the voltage of an LLC secondary winding can be sampled through the first driving circuit and the second driving circuit, and then the first field effect transistor and the second field effect transistor are reversely driven to realize a synchronous rectification effect, so that the overall efficiency of a power supply is improved; the LLC double-tube synchronous rectification chip is composed of common triodes and diodes, is low in price, is free of out-of-stock worries, can adjust parameters according to working conditions and elements, is high in adaptability, can reduce the cost, improves the reliability of a supply chain, optimizes the performance and adaptability of a circuit, improves the layout design, and improves the efficiency. According to the circuit design, the triodes and the diodes which are more common and low in price are adopted, and the delay of the return period caused by supply shortage is eliminated.

Description

Technical Field

[0001] The utility model relates to the technical field of switching power supplies, in particular to an LLC synchronous rectification circuit. Background Art

[0002] The LLC topology provides efficient power conversion, enabling the chip to excel in high-power density applications. LLC two-switch synchronous rectifier chips can operate at high frequencies, making the overall power system more compact and suitable for scenarios requiring high performance and small size. Currently, commonly used LLC two-switch synchronous rectifier chips are expensive, have long return cycles, and are limited in variety and selection, hindering their adoption. Utility Model Content

[0003] In order to overcome the above technical defects, the present invention provides an LLC synchronous rectification circuit, which can reduce costs, improve supply chain reliability, optimize circuit performance and adaptability, improve layout design, and improve performance and efficiency.

[0004] In order to solve the above problems, the present invention is implemented according to the following technical solutions:

[0005] The utility model provides an LLC synchronous rectification circuit, comprising a transformer, a first drive circuit, a second drive circuit, a first field-effect transistor, a second field-effect transistor, a first resistor, and a second resistor. The transformer comprises a main winding and a secondary winding; a first end of the first drive circuit and a drain of the first field-effect transistor are both connected to a first tap of the secondary winding, a second end of the first drive circuit is connected to a gate of the first field-effect transistor, and two ends of the first resistor are respectively connected to the gate and source of the first field-effect transistor;

[0006] The second end of the second driving circuit and the drain of the second field effect transistor are both connected to the second tap of the secondary winding, the second end of the second driving circuit is connected to the gate of the second field effect transistor, and the two ends of the second resistor are respectively connected to the gate and source of the second field effect transistor;

[0007] A common terminal of the source of the first field effect transistor and the source of the second field effect transistor is grounded, and a third tap of the secondary winding is connected to a power supply.

[0008] As an improvement to the above solution, the first drive circuit includes an input first level detection circuit, a first level inverting circuit, and a first push-pull drive circuit, wherein a first end of the first level detection circuit is connected to a first tap of the secondary winding, a second end of the first level detection circuit is connected to a first end of the first level inverting circuit, a second end of the first level inverting circuit is connected to a first end of the first push-pull drive circuit, a second end of the first push-pull drive circuit is connected to a gate of the first field effect transistor, a third end of the first level detection circuit, a third end of the first level inverting circuit, and a third end of the first push-pull drive circuit are all connected to a first power supply, and a fourth end of the first level inverting circuit and a fourth end of the first push-pull drive circuit are commonly grounded;

[0009] The second drive circuit includes an input second level detection circuit, a second level inverting circuit and a second push-pull drive circuit, wherein the first end of the second level detection circuit is connected to the second tap of the secondary winding, the second end of the second level detection circuit is connected to the first end of the second level inverting circuit, the second end of the second level inverting circuit is connected to the first end of the second push-pull drive circuit, the second end of the second push-pull drive circuit is connected to the gate of the second field effect transistor, the third end of the second level detection circuit, the third end of the second level inverting circuit and the third end of the second push-pull drive circuit are all connected to the second power supply, and the fourth end of the second level inverting circuit and the fourth end of the second push-pull drive circuit are commonly grounded.

[0010] As an improvement to the above solution, the first level detection circuit includes a first diode, a first transistor, and a third resistor, wherein the cathode of the first diode is connected to the first tap of the secondary winding, the anode of the first diode is connected to the emitter of the first transistor, the base of the first transistor is connected to the first end of the third resistor, the collector of the first transistor is connected to the first level inverting circuit, and the second end of the third resistor is connected to the first power supply;

[0011] The second level detection circuit includes a second diode, a second transistor, and a fourth resistor, wherein the cathode of the second diode is connected to the second tap of the secondary winding, the anode of the second diode is connected to the emitter of the second transistor, the base of the second transistor is connected to the first end of the fourth resistor, the collector of the second transistor is connected to the second level reverse circuit, and the second end of the fourth resistor is connected to the second power supply;

[0012] Wherein, the first transistor and the second transistor are NPN transistors.

[0013] As an improvement to the above solution, the first level inversion circuit includes a third diode, a third transistor, and a fifth resistor, wherein the anode of the third diode and the base of the third transistor are both connected to the first level detection circuit, the cathode of the third diode, the collector of the third transistor, and the first end of the fifth resistor are all connected to the first push-pull drive circuit, the second end of the fifth resistor is connected to the first power supply, and the emitter of the third transistor is grounded;

[0014] The second level reverse circuit includes a fourth diode, a fourth transistor, and a sixth resistor, wherein the anode of the fourth diode and the base of the fourth transistor are both connected to the second level detection circuit, the cathode of the fourth diode, the collector of the fourth transistor, and the first end of the sixth resistor are all connected to the second push-pull drive circuit, the second end of the sixth resistor is connected to the second power supply, and the emitter of the fourth transistor is grounded;

[0015] Wherein, the third transistor and the fourth transistor are NPN transistors.

[0016] As an improvement to the above solution, the first push-pull drive circuit includes a fifth transistor, a sixth transistor, and a seventh resistor, wherein the base of the fifth transistor and the base of the sixth transistor are connected to the first level inversion circuit, the common end of the emitter of the fifth transistor and the collector of the sixth transistor are connected to the gate of the first field effect transistor, the two ends of the seventh resistor are respectively connected to the first power supply and the collector of the fifth transistor, and the emitter of the sixth transistor is grounded;

[0017] The second push-pull driving circuit includes a seventh transistor, an eighth transistor, and an eighth resistor, the base of the seventh transistor and the base of the eighth transistor are connected to the second level inversion circuit, the common end of the emitter of the seventh transistor and the collector of the eighth transistor is connected to the gate of the second field effect transistor, the two ends of the eighth resistor are respectively connected to the second power supply and the collector of the seventh transistor, and the emitter of the eighth transistor is grounded;

[0018] Wherein, the fifth transistor and the seventh transistor are NPN transistors.

[0019] As an improvement of the above solution, the sixth transistor and the eighth transistor are NPN transistors.

[0020] As an improvement of the above solution, it also includes a first capacitor, the positive electrode of the first capacitor is connected to the third tap of the secondary winding and the common end of the power supply, and the negative electrode of the first capacitor is grounded

[0021] As an improvement to the above solution, the third tap of the secondary winding is located between the first tap of the secondary winding and the second tap of the secondary winding.

[0022] As an improvement to the above solution, the first diode and the second diode are Schottky diodes.

[0023] As an improvement to the above solution, the third diode and the fourth diode are Schottky diodes.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] This application can sample the LLC secondary winding voltage (the secondary winding of the transformer) through the first drive circuit and the second drive circuit, and then reversely drive the first field-effect transistor and the second field-effect transistor to achieve the effect of synchronous rectification, thereby improving the overall efficiency of the power supply; this application uses common transistors and diodes to form a low-price component, without concerns about shortages, and can adjust parameters according to working conditions and components. It has strong adaptability, can reduce costs, improve supply chain reliability, optimize circuit performance and adaptability, improve board design, and improve performance and efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, wherein:

[0027] Figure 1 This is a structural diagram of an LLC synchronous rectification circuit in one embodiment of the present application;

[0028] Figure 2 This is a circuit schematic diagram of a first driving circuit in one embodiment of the present application;

[0029] Figure 3 1 is a circuit schematic diagram of an LLC synchronous rectification circuit in one embodiment of the present application;

[0030] Figure 4 This is a schematic diagram of a push-pull driving circuit in one embodiment of the present application. DETAILED DESCRIPTION

[0031] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure of the present application.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0033] In the case of using “including,” “having,” and “comprising” described herein, another component may be added unless a clear limiting term such as “only,” “consisting of,” etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as having one number.

[0034] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this application.

[0035] In this application, unless otherwise specified or limited, the terms "connected" and "connection" should be understood in a broad sense. For example, they can refer to direct connection or indirect connection through an intermediate medium, internal communication between two elements, or interaction between two elements. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0036] In order to illustrate the above technical solutions of the present application, specific embodiments are provided below.

[0037] In one embodiment, Figure 1 As shown, an LLC synchronous rectification circuit is provided, including a transformer, a first drive circuit, a second drive circuit, a first field-effect transistor Q11, a second field-effect transistor Q12, a first resistor R1, and a second resistor R2. The transformer includes a main winding and a secondary winding; a first end of the first drive circuit and a drain of the first field-effect transistor Q11 are both connected to a first tap of the secondary winding, a second end of the first drive circuit is connected to a gate of the first field-effect transistor Q11, and two ends of the first resistor R1 are respectively connected to the gate and source of the first field-effect transistor Q11;

[0038] The second end of the second driving circuit and the drain of the second field effect transistor Q12 are both connected to the second tap of the secondary winding, the second end of the second driving circuit is connected to the gate of the second field effect transistor Q12, and the two ends of the second resistor R2 are respectively connected to the gate and source of the second field effect transistor Q12;

[0039] A common terminal of the source of the first field effect transistor Q11 and the source of the second field effect transistor Q12 is grounded, and a third tap of the secondary winding is connected to a power supply.

[0040] Specifically, it further includes a first capacitor C1 , wherein the positive electrode of the first capacitor C1 is connected to the third tap of the secondary winding and the common end of the power supply, and the negative electrode of the first capacitor C1 is grounded.

[0041] Specifically, the LLC secondary winding voltage (the secondary winding of the transformer) can be sampled by the first drive circuit and the second drive circuit, and then the first field effect transistor Q11 and the second field effect transistor Q12 are reversely driven to achieve the effect of synchronous rectification, thereby improving the overall efficiency of the power supply.

[0042] In one embodiment, Figure 2 and Figure 3 As shown, the first driving circuit includes an input first level detection circuit, a first level inverting circuit, and a first push-pull driving circuit. The first end of the first level detection circuit is connected to the first tap of the secondary winding, the second end of the first level detection circuit is connected to the first end of the first level inverting circuit, the second end of the first level inverting circuit is connected to the first end of the first push-pull driving circuit, the second end of the first push-pull driving circuit is connected to the gate of the first field effect transistor Q11, the third end of the first level detection circuit, the third end of the first level inverting circuit, and the third end of the first push-pull driving circuit are all connected to a first power supply, and the fourth end of the first level inverting circuit and the fourth end of the first push-pull driving circuit are commonly grounded.

[0043] The second drive circuit includes an input second level detection circuit, a second level inverting circuit and a second push-pull drive circuit, wherein the first end of the second level detection circuit is connected to the second tap of the secondary winding, the second end of the second level detection circuit is connected to the first end of the second level inverting circuit, the second end of the second level inverting circuit is connected to the first end of the second push-pull drive circuit, the second end of the second push-pull drive circuit is connected to the gate of the second field effect transistor Q12, the third end of the second level detection circuit, the third end of the second level inverting circuit and the third end of the second push-pull drive circuit are all connected to the second power supply, and the fourth end of the second level inverting circuit and the fourth end of the second push-pull drive circuit are commonly grounded.

[0044] For more details, please see Figure 2 and Figure 3As shown, the first level detection circuit includes a first diode D1, a first transistor Q1, and a third resistor R3, wherein the cathode of the first diode D1 is connected to the first tap of the secondary winding, the anode of the first diode D1 is connected to the emitter of the first transistor Q1, the base of the first transistor Q1 is connected to the first end of the third resistor R3, the collector of the first transistor is connected to the first level reverse circuit, and the second end of the third resistor R3 is connected to the first power supply;

[0045] The second level detection circuit includes a second diode D2, a second transistor Q2, and a fourth resistor R4, wherein the cathode of the second diode D2 is connected to the second tap of the secondary winding, the anode of the second diode D2 is connected to the emitter of the second transistor Q2, the base of the second transistor Q2 is connected to the first end of the fourth resistor R4, the collector of the second transistor is connected to the second level reverse circuit, and the second end of the fourth resistor R4 is connected to the second power supply;

[0046] The first transistor Q1 and the second transistor Q2 are NPN transistors.

[0047] It can be understood that in this embodiment, the first transistor Q1 utilizes the characteristics of an NPN transistor (two PN junctions with a common anode) to detect the high and low levels of the input voltage.

[0048] For more details, please refer to Figure 2 and Figure 3 As shown, the first level inverting circuit includes a third diode D3, a third triode Q3 and a fifth resistor R5, the anode of the third diode D3 and the base of the third triode Q3 are both connected to the first level detection circuit, the cathode of the third diode D3, the collector of the third triode Q3 and the first end of the fifth resistor R5 are all connected to the first push-pull driving circuit, the second end of the fifth resistor R5 is connected to the first power supply, and the emitter of the third triode Q3 is grounded;

[0049] The second level reverse circuit includes a fourth diode D4, a fourth transistor Q4 and a sixth resistor R6, wherein the anode of the fourth diode D4 and the base of the fourth transistor Q4 are both connected to the second level detection circuit, the cathode of the fourth diode D4, the collector of the fourth transistor Q4 and the first end of the sixth resistor R6 are all connected to the second push-pull drive circuit, the second end of the sixth resistor R6 is connected to the second power supply, and the emitter of the fourth transistor Q4 is grounded;

[0050] Wherein, the third transistor Q3 and the fourth transistor Q4 are NPN transistors.

[0051] It can be understood that in this embodiment, the Schottky diode D1 is connected in parallel to the base and collector of the third transistor Q3, which can reduce the saturation level of the third transistor Q3, increase the switching speed, and improve the sensitivity of the circuit.

[0052] For more details, please refer to Figure 2 and Figure 3 As shown, the first push-pull driving circuit includes a fifth transistor Q5, a sixth transistor Q6, and a seventh resistor. The base of the fifth transistor Q5 and the base of the sixth transistor Q6 are connected to the first level inversion circuit. The common end of the emitter of the fifth transistor Q5 and the collector of the sixth transistor Q6 is connected to the gate of the first field effect transistor Q11. The two ends of the seventh resistor are respectively connected to the first power supply and the collector of the fifth transistor Q5. The emitter of the sixth transistor Q6 is grounded.

[0053] The second push-pull drive circuit includes a seventh transistor Q7, an eighth transistor Q8, and an eighth resistor, the base of the seventh transistor Q7 and the base of the eighth transistor Q8 are connected to the second level inversion circuit, the common end of the emitter of the seventh transistor Q7 and the collector of the eighth transistor Q8 are connected to the gate of the second field effect transistor Q12, the two ends of the eighth resistor are respectively connected to the second power supply and the collector of the seventh transistor Q7, and the emitter of the eighth transistor Q8 is grounded;

[0054] It can be understood that in the embodiment of the present application, the fifth transistor Q5 and the sixth transistor Q6 are used at the output end of the circuit to form a push-pull drive circuit, which improves the driving capability of the circuit and can drive commonly used MOS tubes.

[0055] refer to Figure 1 and Figure 3 It can be understood that the present invention connects the cathode of the first diode D1 to the L-terminal of the LLC transformer's secondary winding. Assuming the L-terminal is at a high level, the first diode D1 and the first transistor Q1 are turned off. The Vbc of the first transistor Q1 and the Vbe of the third transistor Q3 are forward biased, and the third transistor Q3 is saturated and turned on. The Vce of the third transistor Q3 is approximately equal to 0V. After passing through the push-pull circuit formed by the fifth transistor Q5 and the sixth transistor Q6, VG1 = 0V, and the first field-effect transistor Q11 is turned off. When L = 0V (which is less than 0V when the L-terminal is actually at a low level), the first diode D1 and the first transistor Q1 are turned on, and the base of the third transistor Q3 is pulled down and turned off. The Vce of the third transistor Q3 is 12V. After passing through the push-pull circuit formed by the fifth transistor Q5 and the sixth transistor Q6, VG1 = 12V, and the first field-effect transistor Q11 is turned on. The operating principle of the drive circuit at the other end N is the same. The working principle of this circuit conforms to the working sequence of LLC secondary rectification and can realize synchronous rectification.

[0056] In some embodiments, as Figure 4 As shown, the sixth transistor Q6 and the eighth transistor Q8 are NPN transistors.

[0057] Specifically, in the embodiment of the present application, the sixth transistor Q6 and the eighth transistor Q8 may be NPN transistors or PNP transistors. It should be noted that: Figure 4 It can be the first driving circuit or the second driving circuit. The difference between the sixth transistor Q6 and the eighth transistor Q8 changes the driving mode of the field effect transistor.

[0058] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0059] The above-described embodiments merely represent several implementations of the present invention. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the utility model patent. It should be noted that a person skilled in the art would be able to make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements fall within the scope of protection of the present invention. Therefore, the scope of protection of the present utility model patent shall be determined by the appended claims.

Claims

1. An LLC synchronous rectification circuit, characterized in that: The invention comprises a transformer, a first drive circuit, a second drive circuit, a first field effect transistor, a second field effect transistor, a first resistor and a second resistor, wherein the transformer comprises a main winding and a secondary winding; a first end of the first drive circuit and a drain of the first field effect transistor are both connected to a first tap of the secondary winding, a second end of the first drive circuit is connected to a gate of the first field effect transistor, and two ends of the first resistor are respectively connected to a gate and a source of the first field effect transistor; The second end of the second driving circuit and the drain of the second field effect transistor are both connected to the second tap of the secondary winding, the second end of the second driving circuit is connected to the gate of the second field effect transistor, and the two ends of the second resistor are respectively connected to the gate and the source of the second field effect transistor; A common terminal of the source of the first field effect transistor and the source of the second field effect transistor is grounded, and a third tap of the secondary winding is connected to a power supply.

2. The LLC synchronous rectification circuit according to claim 1, characterized in that: The first driving circuit comprises an input first level detection circuit, a first level inversion circuit and a first push-pull driving circuit, wherein a first end of the first level detection circuit is connected to a first tap of the secondary winding, a second end of the first level detection circuit is connected to a first end of the first level inversion circuit, a second end of the first level inversion circuit is connected to a first end of the first push-pull driving circuit, a second end of the first push-pull driving circuit is connected to a gate of the first field effect transistor, a third end of the first level detection circuit, a third end of the first level inversion circuit and a third end of the first push-pull driving circuit are all connected to a first power supply, and a fourth end of the first level inversion circuit and a fourth end of the first push-pull driving circuit are commonly grounded; The second driving circuit includes an input second level detection circuit, a second level inversion circuit and a second push-pull driving circuit, wherein a first end of the second level detection circuit is connected to a second tap of the secondary winding, a second end of the second level detection circuit is connected to a first end of the second level inversion circuit, a second end of the second level inversion circuit is connected to a first end of the second push-pull driving circuit, a second end of the second push-pull driving circuit is connected to a gate of the second field effect transistor, a third end of the second level detection circuit, a third end of the second level inversion circuit and a third end of the second push-pull driving circuit are all connected to a second power supply, and a fourth end of the second level inversion circuit and a fourth end of the second push-pull driving circuit are commonly grounded.

3. The LLC synchronous rectification circuit according to claim 2, characterized in that: The first level detection circuit includes a first diode, a first transistor, and a third resistor, wherein the cathode of the first diode is connected to the first tap of the secondary winding, the anode of the first diode is connected to the emitter of the first transistor, the base of the first transistor is connected to the first end of the third resistor, the collector of the first transistor is connected to the first level reverse circuit, and the second end of the third resistor is connected to the first power supply; The second level detection circuit comprises a second diode, a second triode, and a fourth resistor, wherein the cathode of the second diode is connected to the second tap of the secondary winding, the anode of the second diode is connected to the emitter of the second triode, the base of the second triode is connected to the first end of the fourth resistor, the collector of the second triode is connected to the second level reverse circuit, and the second end of the fourth resistor is connected to the second power supply; Wherein, the first transistor and the second transistor are NPN transistors.

4. The LLC synchronous rectification circuit according to claim 2, characterized in that: The first level reverse circuit comprises a third diode, a third triode and a fifth resistor, the anode of the third diode and the base of the third triode are both connected to the first level detection circuit, the cathode of the third diode, the collector of the third triode and the first end of the fifth resistor are all connected to the first push-pull driving circuit, the second end of the fifth resistor is connected to the first power supply, and the emitter of the third triode is grounded; The second level reverse circuit comprises a fourth diode, a fourth transistor and a sixth resistor, the anode of the fourth diode and the base of the fourth transistor are both connected to the second level detection circuit, the cathode of the fourth diode, the collector of the fourth transistor and the first end of the sixth resistor are all connected to the second push-pull driving circuit, the second end of the sixth resistor is connected to the second power supply, and the emitter of the fourth transistor is grounded; Wherein, the third transistor and the fourth transistor are NPN transistors.

5. The LLC synchronous rectification circuit according to claim 2, characterized in that: The first push-pull driving circuit comprises a fifth transistor, a sixth transistor and a seventh resistor, the base of the fifth transistor and the base of the sixth transistor are connected to the first level inversion circuit, the common end of the emitter of the fifth transistor and the collector of the sixth transistor is connected to the gate of the first field effect transistor, the two ends of the seventh resistor are respectively connected to the first power supply and the collector of the fifth transistor, and the emitter of the sixth transistor is grounded; The second push-pull driving circuit comprises a seventh transistor, an eighth transistor and an eighth resistor, the base of the seventh transistor and the base of the eighth transistor are connected to the second level inversion circuit, the common end of the emitter of the seventh transistor and the collector of the eighth transistor is connected to the gate of the second field effect transistor, the two ends of the eighth resistor are respectively connected to the second power supply and the collector of the seventh transistor, and the emitter of the eighth transistor is grounded; Wherein, the fifth transistor and the seventh transistor are NPN transistors.

6. The LLC synchronous rectification circuit according to claim 5, characterized in that: The sixth transistor and the eighth transistor are NPN transistors.

7. The LLC synchronous rectification circuit according to claim 1, characterized in that: It also includes a first capacitor, wherein a positive electrode of the first capacitor is connected to the third tap of the secondary winding and the common end of the power supply, and a negative electrode of the first capacitor is grounded.

8. The LLC synchronous rectification circuit according to claim 1, characterized in that: The third tap of the secondary winding is located between the first tap of the secondary winding and the second tap of the secondary winding.

9. The LLC synchronous rectification circuit according to claim 3, characterized in that: The first diode and the second diode are Schottky diodes.

10. The LLC synchronous rectification circuit according to claim 4, characterized in that: The third diode and the fourth diode are Schottky diodes.

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