Chip packaging structure, combined packaging chip and electronic equipment
By encapsulating the die in the carrier, forming a chip packaging structure, using the packaging frame to achieve rapid heat dissipation, and supporting chip stacking packaging, the problem that chips with high heat dissipation requirements but small area in the combined package cannot effectively dissipate heat and stacking packaging.
Patent Information
- Application Number
- CN202420437301.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-07
- Publication Date
- 2025-02-18
- Estimated Expiration
- 2034-03-07
AI Technical Summary
In combined packages, chips with high heat dissipation requirements but smaller area cannot effectively use the leadframe for heat dissipation, and chips are prone to cross-wires and insufficient heat dissipation when stacking.
By encapsulating the die in the carrier, a chip packaging structure is formed, a package frame is used to achieve rapid heat dissipation, and chip stack packaging is supported to avoid lead crossing.
The chip with high heat dissipation requirements can effectively utilize the packaging frame for heat dissipation in the combined package and support chip stacking packaging, solving the problem that small-sized chip stacking packaging cannot meet its heat dissipation needs.
Smart Images
Figure CN222507617U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a chip packaging structure, a combined packaged chip and an electronic device. Background Art
[0002] The existing PD chip combination packaging is mainly based on QFN packaging (quad flat non-leaded package), and most of them adopt QFN square flat non-leaded packaging, which is a surface mount packaging. The package size and specifications are relatively fixed. The multi-chip combination packaging is realized by the combination chip packaging wire bonding method. Some chips have high requirements for heat dissipation, and the heat sink of the chip and the leadframe (package frame) need to be directly connected through silver glue to achieve heat dissipation. However, due to the limitations of chip size and netlist relationship, after the package is selected, there is insufficient space for parallel placement of multiple chips on the plane, and they need to be stacked; chip stacking will encounter wire crossing, and chips with high heat dissipation requirements cannot be placed at the bottom due to their small area, resulting in their inability to dissipate heat through the leadframe (the heat sink of the chip and the leadframe is directly connected through silver glue to achieve rapid heat dissipation).
[0003] How to solve the problem of using leadframe to dissipate heat in a combined package with a chip that has a high heat dissipation requirement and a relatively small area has become a technical problem that needs to be solved urgently by those skilled in the art. Utility Model Content
[0004] In view of the above problems, the embodiments of the present application provide a chip packaging structure, a combined packaged chip and an electronic device to solve the above technical problems.
[0005] In a first aspect, an embodiment of the present application provides a chip packaging structure, including:
[0006] a first bare chip, a plurality of first pins being formed on a first surface of the first bare chip;
[0007] A carrier, wherein a mounting through hole is formed on the carrier, and the first bare chip is embedded in the mounting through hole;
[0008] An insulating layer is arranged on the first surface of the carrier, the insulating layer covers the carrier and the first bare chip, and chip pins are arranged on the insulating layer, and the chip pins correspond to and are connected with the first pins one by one.
[0009] Optionally, the chip pins are distributed along the edge of the insulating layer.
[0010] The chip pins are connected to the first pins via wires, and the wires are distributed on the first surface of the carrier.
[0011] Optionally, the second surface of the first die and the second surface of the carrier are located in the same plane.
[0012] In a second aspect, an embodiment of the present application provides a combined packaged chip, including the above-mentioned chip packaging structure.
[0013] Optionally, the combined packaged chip includes a packaging frame, and the chip packaging structure is arranged on the packaging frame.
[0014] A second bare chip is arranged on the chip packaging structure, and the second bare chip is connected to the insulating layer.
[0015] Optionally, the chip pins are located outside an overlapping area between the second bare die and the insulating layer.
[0016] Optionally, the package frame includes a base island and frame pins,
[0017] The chip packaging structure is bonded to the base island by adhesive material, the second bare chip is bonded to the insulating layer by adhesive material, a plurality of second pins are formed on the second bare chip, and the chip pins and the second pins are respectively connected to the frame pins by packaging leads.
[0018] Optionally, some of the second pins are connected to the chip pins.
[0019] Optionally, the combined packaged chip further includes a plastic package, and the package frame, the chip packaging structure and the second bare chip are packaged in the plastic package.
[0020] In a third aspect, an embodiment of the present application provides an electronic device, comprising the above-mentioned combined packaged chip.
[0021] The chip packaging structure provided in the embodiment of the present application, by packaging the bare chip in the carrier, allows the chip with high heat dissipation requirements and small size to be placed at the bottom during combined packaging to directly achieve rapid heat dissipation through the packaging frame, and can also support stacking packaging of chips on the upper layer. This solves the technical problem that the stacking packaging of small-sized chips cannot meet their heat dissipation requirements.
[0022] These and other aspects of the present application will become more apparent from the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0024] Figure 1 A side view schematic diagram of a chip packaging structure provided in an embodiment of the present application is shown.
[0025] Figure 2 A schematic top view of a chip packaging structure provided in an embodiment of the present application is shown.
[0026] Figure 3 A bottom view schematically shows a chip packaging structure provided in an embodiment of the present application.
[0027] Figure 4 A side view schematic diagram of a combined packaged chip provided in an embodiment of the present application is shown.
[0028] Figure 5 A schematic top view of a combined packaged chip provided in an embodiment of the present application is shown.
[0029] Figure 6 A bottom view schematically shows a combined packaged chip provided in an embodiment of the present application.
[0030] In the figure,
[0031] 1. Chip packaging structure; 11. First bare die; 111. First pin; 12. Carrier; 13. Insulation layer; 14. Chip pin; 15. Wire; 2. Package frame; 21. Base island; 22. Frame pin; 3. Second bare die; 31. Second pin; 4. Chip adhesive; 5. Package lead; 6. Plastic package. DETAILED DESCRIPTION
[0032] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.
[0033] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.
[0034] In the embodiments of the present application, it should be noted that, in this article, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.
[0035] Moreover, the terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.
[0036] In the description of the embodiments of the present application, words such as "example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "example" or "for example" in the embodiments of the present application is not to be interpreted as being more preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.
[0037] In addition, the "plurality" in the embodiments of the present application refers to two or more than two. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two or more. For example, including at least one means including one, two or more, and there is no limit on which ones are included. For example, including at least one of A, B and C, then A, B, C, A and B, A and C, B and C, or A, B and C can be included.
[0038] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.
[0039] The combined PD chip is a USB Type-C and USB PD controller suitable for PC applications, integrating all the functions of Type-CCC and USB PD. It also integrates a variety of mobile phone fast charging protocols to enhance the charging compatibility of terminal devices. The combined chip can integrate 2 independent PD modules or 1 PD module.
[0040] Traditional packaged integrated chips generally use QFN packaging, and the package size specifications are relatively fixed. Generally, chips with large areas are placed on the bottom layer, and chips with small areas are placed on the upper layer. When the chip area is small and the heat dissipation requirements are relatively high, the chip often cannot be placed at the bottom, and rapid heat dissipation cannot be achieved through the packaging frame. The present application forms a chip packaging structure with a bare die and a carrier to increase its actual area, so that chips with higher heat dissipation requirements can meet the requirements of being placed on the bottom layer and directly in contact with the packaging frame, thereby improving heat dissipation efficiency. At the same time, the pins of the chip can also be rearranged through the carrier setting to meet the needs of combined stacking packaging and avoid the situation of lead crossing.
[0041] The present application will be described in detail below in conjunction with specific embodiments:
[0042] like Figure 1 As shown, Figure 1 The chip packaging structure 1 provided by the embodiment of the utility model is schematically shown. The chip packaging structure 1 includes a first bare chip 11, a carrier 12 and an insulating layer 13. Optionally, the carrier 12 is a silicon-based carrier 12, a plastic encapsulation material carrier 12 or other insulating carrier 12. A mounting through hole is formed on the carrier 12, and the first bare chip 11 is embedded in the mounting through hole. The insulating layer 13 is arranged on the first surface of the carrier 12 and covers the first surface of the carrier 12 and the first surface of the first bare chip 11. Optionally, the insulating layer 13 is an insulating material coating, and materials such as PI (polyimide) and PBO (Polyp-phenylenebenzoxazole) can be selected. In this embodiment, the first bare chip 11 is packaged inside the carrier 12 in a packaging form such as FO (Fan out), eWLB (embedded wafer level Ball Grid Array) or PLP (Panel level package).
[0043] The insulating layer 13 is provided with chip pins 14, such as Figure 2 As shown, the chip pins 14 are embedded in the insulator and at least one surface is exposed, a plurality of first pins 111 are arranged on the first surface of the first bare chip 11, the number of the chip pins 14 is the same as the number of the first pins 111, and the chip pins 14 and the first pins 111 correspond to and are connected one by one. Optionally, the chip pins 14 are made of electroplated nickel.
[0044] In one embodiment of the present application, the chip pins 14 are distributed along the edge of the insulating layer 13 and connected to the first pins 111 through the wires 15. Optionally, the wires 15 are electroplated copper wiring. In this embodiment, the wires 15 and the chip pins 14 are arranged on the first surface of the carrier 12 and fixed to the first surface of the carrier 12 by the insulating layer 13. The insulating layer 13 has windows corresponding to the positions of the chip pins 14, so that the upper surfaces of the chip pins 14 are exposed on the surface of the insulating layer 13.
[0045] In one embodiment, Figure 1 , Figure 3 As shown, the second surface of the first die 11 and the second surface of the carrier 12 are located in the same plane, wherein the second surface of the first die 11 is parallel to the first surface of the first die 11, and the second surface of the carrier 12 is parallel to the first surface of the carrier 12. Optionally, the second surface of the first die 11 can be exposed by grinding the carrier 12 and the second surface of the first die 11, that is, the second surface of the first die 11 and the second surface of the carrier 12 are located in the same plane. The second surface of the first die 11 and the second surface of the carrier 12 being located in the same plane can prevent the arrangement of the carrier 12 from affecting the heat dissipation of the first die 11 through the packaging frame.
[0046] The chip packaging structure 1 provided in the embodiment of the present application meets the size requirements by packaging the first bare chip 11 in the carrier 12, ensuring that it can be placed at the bottom layer during stacking packaging, and achieves rapid heat dissipation through the packaging frame. At the same time, the chip pins 14 can be rearranged as needed to better match the pin positions of the upper chip, avoiding the problem of lead crossing.
[0047] The embodiment of the present application further provides a combined package chip, the combined package chip comprising the above-mentioned chip packaging structure 1, Figure 3 The combined package chip provided by the embodiment of the utility model is schematically shown. In one embodiment, as Figure 3 , Figure 4 , Figure 5 As shown, the combined packaged chip includes a package frame 2, a chip package structure 1 is arranged on the package frame 2, a second die 3 is also arranged on the chip package structure 1, and the second die 3 is arranged above the insulating layer 13, wherein the heat dissipation of the first die 11 is greater than the heat dissipation of the second die 3, and the combined packaged chip is arranged on the package frame 2 so that the first die 11 can directly dissipate heat through the package frame 2, thereby achieving rapid heat dissipation. The chip pin 14 is located outside the overlapping area of the second die 3 and the insulating layer 13, that is, the chip pin 14 is not covered by the second die 3, ensuring that the chip pin 14 can be normally connected to other components.
[0048] In one embodiment, Figure 4As shown, the packaging frame 2 includes a base island 21 and a frame pin 22, and the chip packaging structure 1 is bonded to the base island 21 by an adhesive material. Optionally, the adhesive material includes a chip adhesive 4, wherein the second side of the first bare chip 11 and the second side of the carrier 12 are bonded to the base island 21 by the chip adhesive 4. During operation, the high heat of the first bare chip 11 can be directly dissipated to the outside (air and PCB board) through the base island 21 of the packaging frame 2, thereby achieving a rapid heat dissipation effect.
[0049] The second bare chip 3 is bonded to the insulating layer 13 by the chip adhesive 4, and the bonding position is located outside the area where the chip pins 14 are located, so as to avoid the second bare chip 3 or the chip adhesive 4 from blocking the chip pins 14. A plurality of second pins 31 are formed on the second bare chip 3, and the chip pins 14 and the second pins 31 are respectively connected to the frame pins 22 through the package leads 5. Optionally, the package leads 5 can be made of gold wire, copper wire, palladium copper wire or alloy wire. In one embodiment, a part of the second pins 31 is connected to the chip pins 14, and the other part is connected to the frame pins 22. Optionally, one second pin 31 can be connected to one chip pin 14, or multiple second pins 31 can be connected to one chip pin 14, and the chip pins 14 not connected to the second pins 31 are connected to the frame pins 22.
[0050] In one embodiment, the combined packaged chip further includes a plastic package 6 , in which the package frame 2 , the chip package structure 1 and the second die 3 are packaged.
[0051] In one embodiment, the combined package chip of the present application can be a PD chip, which is suitable for USB Type-C and USB PD controllers for PC applications, and can integrate multiple fast charging protocols to enhance the charging compatibility of terminal devices. It can also solve the high-voltage resistance problem of PD products based on the combined package architecture, and is also suitable for application scenarios where general MCUs require high-voltage protection and high-voltage power supply.
[0052] The combined packaged chip of the embodiment of the present application adopts the above chip packaging structure 1 to ensure that the first bare die 11 with high heat dissipation requirements will not be limited by size, so that the first bare die 11 with a small size can be directly set on the packaging frame 2, and the heat dissipation through the packaging frame 2 can achieve rapid heat dissipation, and can also support the stacking packaging of the upper second bare die 3. At the same time, the first pin 111 on the first bare die 11 is led out to the chip pin 14, and the layout can be re-arranged so that the layout of the chip pin 14 is better matched with the second pin 31 on the second bare die 3 and the frame pin 22 on the packaging frame 2, avoiding the problem of lead crossing.
[0053] The present application also provides an electronic device, which includes a device body and a combined package chip as described above, which is provided in the device body. The electronic device can be, but is not limited to, a mobile terminal, such as a smart phone, a laptop, a tablet computer, a POS (point of sales terminal), etc.
[0054] The above are only preferred embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any technical personnel in the field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.
Claims
1. A chip packaging structure, characterized in that: include: a first bare chip, a plurality of first pins being formed on a first surface of the first bare chip; A carrier, wherein a mounting through hole is formed on the carrier, and the first bare chip is embedded in the mounting through hole; An insulating layer is arranged on the first surface of the carrier, the insulating layer covers the carrier and the first bare chip, and chip pins are arranged on the insulating layer, and the chip pins correspond to and are connected with the first pins one by one.
2. The chip packaging structure according to claim 1, characterized in that: The chip pins are distributed along the edge of the insulating layer, The chip pins are connected to the first pins via wires, and the wires are distributed on the first surface of the carrier.
3. The chip packaging structure according to claim 1 or 2, characterized in that: The second surface of the first die and the second surface of the carrier are located in the same plane.
4. A combined package chip, characterized in that: A chip packaging structure comprising any one of claims 1 to 3.
5. The combined package chip according to claim 4, characterized in that: The combined packaged chip comprises a packaging frame, and the chip packaging structure is arranged on the packaging frame. A second bare chip is arranged on the chip packaging structure, and the second bare chip is arranged on the insulating layer.
6. The combined package chip according to claim 5, characterized in that: The chip pins are located outside an overlapping area between the second bare die and the insulating layer.
7. The combined package chip according to claim 5, characterized in that: The package frame includes a base island and frame pins. The chip packaging structure is bonded to the base island by an adhesive material, the second bare chip is bonded to the insulating layer by an adhesive material, a plurality of second pins are formed on the second bare chip, and the chip pins and the second pins are respectively connected to the frame pins by packaging leads.
8. The combined package chip according to claim 7, characterized in that: Some of the second pins are connected to the chip pins.
9. The combined package chip according to any one of claims 5 to 8, characterized in that: The combined packaged chip further comprises a plastic package, in which the package frame, the chip package structure and the second bare chip are packaged.
10. An electronic device, characterized in that: Comprising the combined packaged chip as described in any one of claims 4 to 9.