Display device

Abstract

The present disclosure relates to a display device, and more particularly, to a display device capable of improving resolution. According to an embodiment of the present disclosure, a display device includes: a substrate; a first gate electrode disposed on the substrate; a lower capacitor electrode disposed on the first gate electrode to overlap the first gate electrode in a plan view; and a repair line disposed on the lower capacitor electrode. The display device may have improved resolution.

Description

[0001] This application claims priority and all rights arising from Korean Patent Application No. 10-2023-0057914 filed in the Korean Intellectual Property Office on May 3, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a display device, and more particularly, to a display device capable of increasing resolution. Background Art

[0003] An organic light emitting display device includes a light emitting element whose brightness changes by current flowing through an organic light emitting diode. Utility Model Content

[0004] An object of the present disclosure is to provide a display device capable of increasing resolution.

[0005] The objects of the present disclosure are not limited to the above objects, and additional objects of the present disclosure not mentioned herein will be clearly understood by those skilled in the art through the following description of the present disclosure.

[0006] According to an embodiment of the present disclosure, a display device includes: a substrate; a first gate electrode disposed on the substrate; a lower capacitor electrode disposed on the first gate electrode to overlap the first gate electrode in a plan view; and a repair line disposed on the lower capacitor electrode.

[0007] In an embodiment, the display device may further include an upper capacitor electrode disposed on the lower capacitor electrode to overlap the lower capacitor electrode in a plan view.

[0008] In an embodiment, the first gate electrode overlaps the upper capacitor electrode in a plan view.

[0009] In an embodiment, an area of ​​the lower capacitor electrode is greater than an area of ​​the first gate electrode in a plan view.

[0010] In an embodiment, an area of ​​the upper capacitor electrode is greater than an area of ​​the lower capacitor electrode in a plan view.

[0011] In an embodiment, the display device may further include a driving voltage line connected to the upper capacitor electrode.

[0012] In an embodiment, the first capacitor is formed by the first gate electrode and the lower capacitor electrode.

[0013] In an embodiment, the second capacitor is formed by a lower capacitor electrode and an upper capacitor electrode.

[0014] In an embodiment, the upper capacitor electrode has a greater number of holes than the lower capacitor electrode.

[0015] In an embodiment, one of the holes in the upper capacitor electrode overlaps the hole in the lower capacitor electrode.

[0016] In an embodiment, the repair line and the upper capacitor electrode are disposed at the same layer.

[0017] In an embodiment, the display device may further include a second gate electrode and a third gate electrode disposed at the same layer as the first gate electrode.

[0018] In an embodiment, the display device may further include a second gate electrode disposed adjacent to the first gate electrode, and the repair line is disposed between the first gate electrode and the second gate electrode.

[0019] In an embodiment, the display device further includes a pixel connection electrode overlapping the repair line.

[0020] In an embodiment, the repair line includes a repair short portion overlapping the pixel connection electrode.

[0021] According to an embodiment of the present disclosure, a display device includes: a substrate; a first transistor, including a first gate electrode arranged on the substrate; a lower capacitor electrode, arranged on the first gate electrode to overlap with the first gate electrode in a plan view; an upper capacitor electrode, arranged on the lower capacitor electrode to overlap with the lower capacitor electrode in a plan view; a repair line, arranged in the same plane as the upper capacitor electrode; and a pixel electrode; arranged on the repair line to overlap with the repair line.

[0022] In an embodiment, the first gate electrode and the lower capacitor electrode may constitute a first capacitor, and the lower capacitor electrode and the upper capacitor electrode may constitute a second capacitor.

[0023] In an embodiment, the first capacitor and the second capacitor may be connected in series between the first gate electrode and the driving voltage line.

[0024] In an embodiment, the pixel electrode may include a pixel connection electrode connected to the first transistor, and the repair line may overlap the pixel connection electrode.

[0025] In an embodiment, the display device may further include a second transistor including a second gate electrode disposed adjacent to the first gate electrode, and the repair line may be disposed between the first gate electrode and the second gate electrode so as not to overlap the first gate electrode and the second gate electrode in a plan view.

[0026] According to the display device disclosed in the present invention, since the gate electrode and the repair line are arranged in different layers, the distance between the repair line and the gate electrode can be reduced, thereby reducing the size of the pixel. Therefore, the resolution of the display device can be improved.

[0027] It should be noted that the effects of the present disclosure are not limited to the above-mentioned effects, and other effects that are not mentioned will be clearly understood by those skilled in the art through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0029] Figure 1 is a perspective view showing a display device according to an embodiment;

[0030] Figure 2 is a cross-sectional view showing a display device according to an embodiment;

[0031] Figure 3 is a plan view showing a display unit of a display device according to an embodiment;

[0032] Figure 4 is a block diagram showing a display panel and a display driver according to one embodiment;

[0033] Figure 5 is a circuit diagram of one pixel of a display device according to one embodiment;

[0034] Figure 6 is a plan view of a unit pixel array according to one embodiment;

[0035] Figure 7 is selectively shown only Figure 6 A plan view of a first pattern layer and a second pattern layer of a component;

[0036] Figure 8 is selectively shown only Figure 6 A plan view of a third pattern layer of the component;

[0037] Fig. 9 is selectively shown only Figure 6 A plan view of a first pattern layer to a third pattern layer of a component;

[0038] Fig.10 is selectively shown only Figure 6 A plan view of a fourth pattern layer of the component;

[0039] Fig.11 is selectively shown only Figure 6 A plan view of the first pattern layer to the fourth pattern layer of the component;

[0040] Fig.12 is selectively shown only Figure 6 A plan view of a fifth pattern layer of the component;

[0041] Fig.13 is selectively shown only Figure 6 A plan view of a sixth pattern layer of the component;

[0042] Fig.14 is selectively shown only Figure 6 A plan view of the first pattern layer to the fifth pattern layer of the component;

[0043] Fig.15 is selectively shown only Figure 6 A plan view of a fifth pattern layer and a sixth pattern layer of a component;

[0044] Fig.16 is selectively shown only Figure 6 A plan view of a sixth pattern layer and a seventh pattern layer of a component;

[0045] Fig.17 It is along Figure 6 A cross-sectional view taken along line II';

[0046] Fig.18 It is along Figure 6 A cross-sectional view taken along line II-II';

[0047] Fig.19 is a circuit diagram of one pixel of a display device according to one embodiment;

[0048] Fig. 20 is a plan view of a unit pixel array according to one embodiment;

[0049] Fig.21 is selectively shown only Fig. 20 A plan view of a first pattern layer and a second pattern layer of a component;

[0050] Fig. 22 is selectively shown only Fig. 20 A plan view of a third pattern layer of the component;

[0051] Fig.23 is selectively shown only Fig. 20 A plan view of the first pattern layer to the fourth pattern layer of the component;

[0052] Fig.24 is selectively shown only Fig. 20 A plan view of a fifth pattern layer of the component;

[0053] Fig.25 is selectively shown only Fig. 20 A plan view of a sixth pattern layer of the component;

[0054] Fig.26 is selectively shown only Fig. 20A plan view of the first pattern layer to the fifth pattern layer of the component;

[0055] Fig. 27 is selectively shown only Fig. 20 A plan view of a fifth pattern layer and a sixth pattern layer of a component;

[0056] Fig.28 is selectively shown only Fig. 20 A plan view of a sixth pattern layer and a seventh pattern layer of a component;

[0057] Fig.29 It is along Fig. 20 A cross-sectional view taken along line III-III';

[0058] Fig.30 is a cross-sectional view showing the structure of a light emitting element according to one embodiment;

[0059] Fig.31 , Fig.32 , Fig.33 and Fig.34 is a cross-sectional view showing the structure of a light emitting element according to one embodiment;

[0060] Fig.35 It is shown Fig.33 A cross-sectional view of an example of an organic light emitting diode;

[0061] Fig.36 It is shown Fig.34 A cross-sectional view of an example of an organic light emitting diode; and

[0062] Fig.37 is a cross-sectional view showing a structure of a pixel of a display device according to an embodiment. DETAILED DESCRIPTION

[0063] The advantages and features of the present disclosure and methods for implementing the same will become apparent with reference to the exemplary embodiments described in detail below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments to be described below, but can be implemented in various different forms, and the exemplary embodiments are provided only to complete the present disclosure and allow those of ordinary skill in the art to which the present disclosure belongs to fully recognize the scope of the present disclosure, and the present disclosure will be limited by the scope of the claims.

[0064] When an element or layer is referred to as being "on" another element or layer, it includes both the case where the element or layer is directly on the other element or layer, and the case where the element or layer is on the other element or layer with another element or layer placed between them. Throughout the specification, the same reference numerals indicate the same components. The shapes, sizes, proportions, angles, quantities, etc. disclosed in the drawings for describing exemplary embodiments are examples, and therefore, the present disclosure is not limited to the shapes, sizes, proportions, angles, quantities, etc. shown in the drawings.

[0065] It will be understood that although the terms "first", "second", etc. can be used to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another component. Therefore, without departing from the teachings of the present disclosure, the first component discussed below can be referred to as the second component.

[0066] Each feature of the various exemplary embodiments of the present disclosure may be partially or completely combined or coupled with each other, and may be technically capable of various interlocking and driving, and each exemplary embodiment may be implemented independently of each other, or may be implemented together in an associated relationship.

[0067] In the specification, "A and / or B" means A, B, or A and B. In addition, in the specification, "at least one of A and B" means A, B, or A and B.

[0068] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0069] Figure 1 is a perspective view showing a display device according to an embodiment.

[0070] Reference Figure 1 The display device 10 may be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic organizers, electronic books, portable multimedia players (PMPs), navigation systems, ultra mobile PCs (UMPCs), etc. For example, the display device 10 may be applied as a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) device. For another example, the display device 10 may be applied to wearable devices such as smart watches, watch phones, glasses-type displays, or head-mounted displays (HMDs).

[0071] The display device 10 may have a planar shape similar to a quadrilateral shape. For example, the display device 10 may have a planar shape similar to a quadrilateral shape having short sides in the first direction DR1 and long sides in the second direction DR2. The corner where the short side in the first direction DR1 and the long side in the second direction DR2 meet may be a right angle or a rounded corner (rounded) having a predetermined curvature. The planar shape of the display device 10 is not limited to a quadrilateral shape, and may be formed in a shape similar to other polygonal shapes, a circular shape, or an elliptical shape.

[0072] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , a touch driver 400 , and a power supply unit 500 .

[0073] The display panel 100 may include a main area MA and a sub area SBA.

[0074] The main area MA may include a display area DA including pixels displaying an image and a non-display area NDA disposed around the display area DA. The display area DA may emit light from a plurality of emission areas or a plurality of opening areas. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining an emission area or an opening area, and a self-luminous element.

[0075] For example, the self-luminous element may include at least one of an organic light emitting diode (LED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but is not limited thereto.

[0076] The non-display area NDA may be an area surrounding the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a gate driver (not shown) supplying a gate signal to a gate line and a fan-out line (not shown) connecting the display driver 200 to the display area DA.

[0077] The sub-region SBA may extend from one side of the main region MA. The sub-region SBA may include a flexible material that may be bent, folded, or curled. For example, when the sub-region SBA is bent, the sub-region SBA may overlap with the main region MA in the thickness direction (e.g., the third direction DR3). The sub-region SBA may include a display driver 200 and a pad (or referred to as a "pad") portion connected to the circuit board 300. Alternatively, the sub-region SBA may be omitted, and the display driver 200 and the pad portion may be arranged in the non-display area NDA.

[0078] The display driver 200 may output a signal and a voltage for driving the display panel 100. The display driver 200 may supply a data voltage to a data line. The display driver 200 may supply a power voltage to a power line, and may supply a gate control signal to a gate driver. The display driver 200 may be formed as an integrated circuit (IC) and may be mounted on the display panel 100 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 may be disposed in a sub-region SBA, and may overlap with the main region MA in a thickness direction (third direction DR3) by bending of the sub-region SBA. For another example, the display driver 200 may be mounted on a circuit board 300.

[0079] The circuit board 300 may be attached to the pad portion of the display panel 100 by using an anisotropic conductive film (ACF). Leads of the circuit board 300 may be electrically connected to the pad portion of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0080] The touch driver 400 may be mounted on the circuit board 300. The touch driver 400 may be electrically connected to the touch sensing unit of the display panel 100. The touch driver 400 may supply a touch drive signal to a plurality of touch electrodes of the touch sensing unit, and may sense the amount of change in capacitance between the plurality of touch electrodes. For example, the touch drive signal may be a pulse signal having a predetermined frequency. The touch driver 400 may calculate whether an input and input coordinates are made based on the amount of change in capacitance between the plurality of touch electrodes. The touch driver 400 may be formed by an integrated circuit (IC).

[0081] The power supply unit 500 may be provided on the circuit board 300 to supply power voltage to the display driver 200 and the display panel 100. The power supply unit 500 may generate a driving voltage to supply it to the driving voltage line VDL, generate an initialization voltage (e.g., a first initialization voltage and a second initialization voltage) to supply it to the initialization voltage lines (e.g., a first initialization voltage line VIL1 and a second initialization voltage line VIL2), and generate a common voltage to supply it to a common electrode common to the light emitting elements of a plurality of pixels. For example, the driving voltage may be a high potential voltage for driving the light emitting element, and the common voltage may be a low potential voltage for driving the light emitting element.

[0082] Figure 2 is a cross-sectional view showing a display device according to an embodiment.

[0083] Reference Figure 2The display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EMTL, and an encapsulation layer ENC.

[0084] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded or curled. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. For another example, the substrate SUB may include a glass material or a metal material.

[0085] The thin film transistor layer TFTL may be disposed on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors constituting a pixel circuit of a pixel. The thin film transistor layer TFTL may also include a gate line, a data line, a power line, a gate control line, a fan-out line connecting the display driver 200 to the data line, and a lead connecting the display driver 200 to the pad portion. Each of the thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when a gate driver is formed on one side of the non-display area NDA of the display panel 100, the gate driver may include a thin film transistor.

[0086] The thin film transistor layer TFTL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistor, gate line, data line, and power line of each of the pixels of the thin film transistor layer TFTL may be disposed in the display area DA. The gate control line and fan-out line of the thin film transistor layer TFTL may be disposed in the non-display area NDA. The lead line of the thin film transistor layer TFTL may be disposed in the sub-area SBA.

[0087] The light emitting element layer EMTL may be disposed on the thin film transistor layer TFTL. The light emitting element layer EMTL may include a plurality of light emitting elements and a pixel defining layer defining pixels, and a pixel electrode, a light emitting layer, and a common electrode of each of the light emitting elements are sequentially stacked to emit light. The plurality of light emitting elements of the light emitting element layer EMTL may be disposed in the display area DA.

[0088] For example, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the pixel electrode receives a predetermined voltage through the thin film transistor of the thin film transistor layer TFTL and the common electrode receives a cathode voltage, holes and electrons may be respectively transmitted to the organic light-emitting layer through the hole transport layer and the electron transport layer, and may be combined with each other to emit light in the organic light-emitting layer. For example, the pixel electrode may be an anode electrode, and the common electrode may be a cathode electrode, but the present disclosure is not limited thereto.

[0089] For another example, the plurality of light emitting elements may include a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, or a micro light emitting diode.

[0090] The encapsulation layer ENC may cover the top surface and the side surface of the light emitting element layer EMTL and may protect the light emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic layer and at least one organic layer for encapsulating the light emitting element layer EMTL.

[0091] The touch sensing unit TSU may be disposed on the encapsulation layer ENC. The touch sensing unit TSU may include a plurality of touch electrodes for capacitively sensing a user's touch and a touch line connecting the plurality of touch electrodes to the touch driver 400. For example, the touch sensing unit TSU may sense a user's touch by using a mutual capacitance method or a self capacitance method.

[0092] For another example, the touch sensing unit TSU may be disposed on a separate substrate disposed on the display unit DU. In this case, the substrate supporting the touch sensing unit TSU may be a base member encapsulating the display unit DU.

[0093] A plurality of touch electrodes of the touch sensing unit TSU may be disposed in a touch sensor region overlapping the display area DA. A touch line of the touch sensing unit TSU may be disposed in a touch peripheral region overlapping the non-display area NDA.

[0094] The color filter layer CFL may be disposed on the touch sensing unit TSU. The color filter layer CFL may include a plurality of color filters corresponding to the plurality of emission regions, respectively. Each of the color filters may selectively transmit light of a specific wavelength, and may block or absorb light of a different wavelength. The color filter layer CFL may absorb a portion of light from outside the display device 10 to reduce reflected light caused by external light. Therefore, the color filter layer CFL may prevent color distortion caused by reflection of external light.

[0095] Since the color filter layer CFL is directly disposed on the touch sensing unit TSU, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 may be relatively reduced.

[0096] The sub-region SBA of the display panel 100 may extend from one side of the main region MA. The sub-region SBA may include a flexible material that may be bent, folded, or curled. For example, when the sub-region SBA is bent, the sub-region SBA may overlap the main region MA in the thickness direction (third direction DR3). The sub-region SBA may include a display driver 200 and a pad portion electrically connected to the circuit board 300.

[0097] Figure 3 is a plan view showing a display unit of a display device according to an embodiment. Figure 4 is a block diagram showing a display panel and a display driver according to one embodiment.

[0098] Reference Figure 3 and Figure 4 , the display panel 100 may include a display area DA and a non-display area NDA.

[0099] The display area DA may include a plurality of pixels PX and a plurality of driving voltage lines VDL, a plurality of common voltage lines VSL (see FIG. Figure 5 ), a plurality of gate lines GL, a plurality of emission control lines EML and a plurality of data lines DL.

[0100] Each of the plurality of pixels PX may be connected to a gate line GL, a data line DL, an emission control line EML, a driving voltage line VDL, and a common voltage line VSL. Each of the pixels PX may include at least one transistor, a light emitting element, and a capacitor.

[0101] Each of the plurality of gate lines GL may extend in a first direction DR1 and may be spaced apart from each other in a second direction DR2 crossing the first direction DR1. The gate lines GL may be arranged along the second direction DR2. The gate lines GL may sequentially supply gate signals to the plurality of pixels PX.

[0102] The emission control lines EML may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2. The emission control lines EML may be arranged along the second direction DR2. The emission control lines EML may sequentially supply emission control signals to the plurality of pixels PX.

[0103] The data lines DL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The data lines DL may be arranged along the first direction DR1. The data lines DL may supply data voltages to the plurality of pixels PX. The data voltages may determine the brightness of each of the pixels PX.

[0104] The driving voltage lines VDL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The driving voltage lines VDL may be arranged along the first direction DR1. The driving voltage lines VDL may supply a first driving voltage to the plurality of pixels PX. The first driving voltage may be a high potential voltage for driving the light emitting elements of the pixels PX.

[0105] The non-display area NDA may surround the display area DA. The non-display area NDA may include a gate driver 610, an emission control driver 620, a fan-out line FL, a first gate control line GSL1, and a second gate control line GSL2.

[0106] The fan-out line FL may extend from the display driver 200 to the display area DA. The fan-out line FL may supply a data voltage received from the display driver 200 to the plurality of data lines DL.

[0107] The first gate control line GSL1 may extend from the display driver 200 to the gate driver 610. The first gate control line GSL1 may supply the gate driver 610 with a gate control signal GCS received from the display driver 200.

[0108] The second gate control line GSL2 may extend from the display driver 200 to the emission control driver 620. The second gate control line GSL2 may supply the emission control driver 620 with the emission control signal ECS received from the display driver 200.

[0109] The sub-area SBA may extend from one side of the non-display area NDA. The sub-area SBA may include a display driver 200 and a pad portion DP. The pad portion DP may be disposed closer to one edge of the sub-area SBA than the display driver 200. The pad portion DP may be electrically connected to the circuit board 300 through an anisotropic conductive film ACF.

[0110] The display driver 200 may include a timing controller 210 and a data driver 220 .

[0111] The timing controller 210 may receive digital video data DATA and a timing signal from the circuit board 300. The timing controller 210 may generate a data control signal DCS for controlling the operation timing of the data driver 220, a gate control signal GCS for controlling the operation timing of the gate driver 610, and an emission control signal ECS for controlling the operation timing of the emission control driver 620 based on the timing signal. The timing controller 210 may supply the gate control signal GCS to the gate driver 610 through the first gate control line GSL1. The timing controller 210 may supply the emission control signal ECS to the emission control driver 620 through the second gate control line GSL2. The timing controller 210 may supply the digital video data DATA and the data control signal DCS to the data driver 220.

[0112] The data driver 220 may convert the digital video data DATA into an analog data voltage and supply the analog data voltage to the data line DL through the fan-out line FL. The gate signal of the gate driver 610 may select the pixel PX supplied with the data voltage, and the selected pixel PX may receive the data voltage through the data line DL.

[0113] The power supply unit 500 may be provided on the circuit board 300 to supply power voltage to the display driver 200 and the display panel 100. The power supply unit 500 may generate a driving voltage and supply the driving voltage to the driving voltage line VDL, generate an initialization voltage and supply the initialization voltage to the initialization voltage line, and generate a common voltage and supply the common voltage to a common electrode common to light emitting elements of a plurality of pixels.

[0114] The gate driver 610 may be disposed on one outer side of the display area DA or one side of the non-display area NDA. The emission control driver 620 may be disposed on the other outer side of the display area DA or the other side of the non-display area NDA. However, the present disclosure is not limited thereto. As another example, the gate driver 610 and the emission control driver 620 may be disposed at any one side of one side and the other side of the non-display area NDA.

[0115] The gate driver 610 may include a plurality of transistors for generating gate signals based on the gate control signal GCS. The emission control driver 620 may include a plurality of transistors for generating emission control signals based on the emission control signal ECS. For example, the transistors of the gate driver 610 and the transistors of the emission control driver 620 may be formed in the same layer as the transistors of each of the pixels PX. The gate driver 610 may supply the gate signal to the gate line GL, and the emission control driver 620 may supply the emission control signal to the emission control line EML.

[0116] Figure 5 is a circuit diagram of one pixel of a display device according to an embodiment.

[0117] The pixel (e.g., PX) can be connected to the first gate line GWL, the second gate line GCL, the third gate line GIL, the fourth gate line EBL, the emission control line EML, the data line DL, the driving voltage line VDL, the common voltage line VSL, the first initialization voltage line VIL1, the second initialization voltage line VIL2 and the bias voltage line VBL.

[0118] A pixel (e.g., PX) may include a pixel circuit PC and a light emitting element LEL. The pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a first capacitor Cst, and a second capacitor Chold.

[0119] The first transistor T1 may include a gate electrode, a source electrode, and a drain electrode. The first transistor T1 may control a source-drain current (hereinafter, a driving current) according to a data voltage applied to the gate electrode. A driving current (Isd) flowing through a channel region of the first transistor T1 may be proportional to the square of a difference between a threshold voltage (Vth) and a voltage (Vsg) between a source electrode and a gate electrode of the first transistor T1 (Isd=k×(Vsg-Vth) 2 ). Here, k is a proportionality coefficient determined by the structure and physical characteristics of the first transistor T1, Vsg is the source-gate voltage of the first transistor ST1, and Vth is the threshold voltage of the first transistor T1.

[0120] The light emitting element LEL may emit light by receiving a driving current (Isd). The emission amount or brightness of the light emitting element LEL may be proportional to the magnitude of the driving current (Isd).

[0121] The light emitting element LEL may be an organic light emitting diode, which includes a first electrode, a second electrode, and an organic light emitting layer disposed between the first electrode and the second electrode. For another example, the light emitting element LEL may be an inorganic light emitting element, which includes a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. For another example, the light emitting element LEL may be a quantum dot light emitting element, which includes a first electrode, a second electrode, and a quantum dot light emitting layer disposed between the first electrode and the second electrode. For another example, the light emitting element LEL may be a micro light emitting diode.

[0122] A first electrode of the light emitting element LEL may be electrically connected to a fourth node N4. The first electrode of the light emitting element LEL may be connected to a drain electrode of the sixth transistor T6 and a source electrode of the seventh transistor T7 through the fourth node N4. A second electrode of the light emitting element LEL may be connected to a common voltage line VSL. The second electrode of the light emitting element LEL may receive a common voltage ELVSS (e.g., a low potential voltage) from the common voltage line VSL.

[0123] The second transistor T2 may be turned on by the first gate signal GW of the first gate line GWL so that the data line DL is electrically connected to the fifth node N5. The drain electrode of the second transistor T2, the first electrode of the first capacitor Cst, the first electrode of the second capacitor Chold, and the drain electrode of the fifth transistor T5 may be connected to the fifth node N5. The second transistor T2 may be turned on in response to the first gate signal GW to supply a data voltage to the fifth node N5. The gate electrode of the second transistor T2 may be electrically connected to the first gate line GWL, its source electrode may be electrically connected to the data line DL, and its drain electrode may be electrically connected to the fifth node N5. At the same time, the second transistor T2 may be configured as a dual-gate transistor. For example, the second transistor T2 may include a second-first transistor and a second-second transistor connected in series between the data line DL and the fifth node N5. The gate electrode of the second-first transistor may be electrically connected to the first gate line GWL, its source electrode may be electrically connected to the data line DL, and its drain electrode may be electrically connected to the source electrode of the second-second transistor. A gate electrode of the second-second transistor may be electrically connected to the first gate line GWL, a source electrode thereof may be electrically connected to the drain electrode of the second-first transistor, and a drain electrode thereof may be electrically connected to the fifth node N5.

[0124] The third transistor T3 may be turned on by the second gate signal GC of the second gate line GCL so that the third node N3 is electrically connected to the second node N2. For example, the gate electrode of the third transistor T3 may be electrically connected to the second gate line GCL, the source electrode thereof may be electrically connected to the third node N3, and the drain electrode thereof may be electrically connected to the second node N2. The source electrode of the third transistor T3, the second electrode of the first capacitor Cst, and the gate electrode of the first transistor T1 may be connected to the third node N3. The drain electrode of the third transistor T3, the drain electrode of the first transistor T1, and the source electrode of the sixth transistor T6 may be connected to the second node N2. The third transistor T3 may be turned on by the second gate signal GC of the second gate line GCL so that the second node N2 is electrically connected to the third node N3.

[0125] The fourth transistor T4 may be turned on by the third gate signal GI of the third gate line GIL so that the third node N3 is electrically connected to the first initialization voltage line VIL1. The fourth transistor T4 may be connected between the third node N3 and the first initialization voltage line VIL1. For example, the gate electrode of the fourth transistor T4 may be electrically connected to the third gate line GIL, its source electrode may be electrically connected to the third node N3, and its drain electrode may be electrically connected to the first initialization voltage line VIL1. At the same time, the fourth transistor T4 may be configured as a dual-gate transistor. For example, the fourth transistor T4 may include a fourth-first transistor and a fourth-second transistor connected in series. The gate electrode of the fourth-first transistor may be electrically connected to the third gate line GIL, its drain electrode may be electrically connected to the first initialization voltage line VIL1, and its source electrode may be electrically connected to the drain electrode of the fourth-second transistor. The gate electrode of the fourth-second transistor may be electrically connected to the third gate line GIL, its drain electrode may be electrically connected to the source electrode of the fourth-first transistor, and its source electrode may be electrically connected to the third node N3. The first initialization voltage line VIL1 may transmit the first initialization voltage VIT1. The third node N3 may be discharged to the first initialization voltage VIT1 .

[0126] The fifth transistor T5 can be turned on by the second gate signal GC of the second gate line GCL so that the driving voltage line VDL is electrically connected to the fifth node N5. For example, the gate electrode of the fifth transistor T5 can be electrically connected to the second gate line GCL, its source electrode can be electrically connected to the driving voltage line VDL, and its drain electrode can be electrically connected to the fifth node N5. At the same time, the fifth transistor T5 can be configured as a dual-gate transistor. For example, the fifth transistor T5 can include a fifth-first transistor and a fifth-second transistor connected in series. The gate electrode of the fifth-first transistor can be electrically connected to the second gate line GCL, its source electrode can be electrically connected to the driving voltage line VDL, and its drain electrode can be electrically connected to the source electrode of the fifth-second transistor. The gate electrode of the fifth-second transistor can be electrically connected to the second gate line GCL, its source electrode can be electrically connected to the drain electrode of the fifth-first transistor, and its drain electrode can be electrically connected to the fifth node N5. The source electrode of the fifth transistor T5 can receive the driving voltage ELVDD.

[0127] The sixth transistor T6 may be turned on by the emission control signal EM of the emission control line EML to electrically connect the second node N2 to the fourth node N4 as the first electrode of the light emitting element LEL. The gate electrode of the sixth transistor T6 may be electrically connected to the emission control line EML, the source electrode thereof may be electrically connected to the second node N2, and the drain electrode thereof may be electrically connected to the fourth node N4.

[0128] The seventh transistor T7 may be turned on by the fourth gate signal EB of the fourth gate line EBL so that the fourth node N4 as the first electrode of the light emitting element LEL is electrically connected to the second initialization voltage line VIL2. By turning on the seventh transistor T7 in response to the fourth gate signal EB, the first electrode of the light emitting element LEL may be discharged to the second initialization voltage VIT2. The gate electrode of the seventh transistor T7 may be electrically connected to the fourth gate line EBL, the source electrode thereof may be electrically connected to the fourth node N4, and the drain electrode thereof may be electrically connected to the second initialization voltage line VIL2. The second initialization voltage line VIL2 may transmit the second initialization voltage VIT2.

[0129] The eighth transistor T8 may be turned on by the emission control signal EM of the emission control line EML to electrically connect the driving voltage line VDL to the first node N1. The gate electrode of the eighth transistor T8 may be electrically connected to the emission control line EML, the source electrode thereof may be electrically connected to the driving voltage line VDL, and the drain electrode thereof may be electrically connected to the first node N1. The drain electrode of the eighth transistor T8, the source electrode of the first transistor T1, the drain electrode of the ninth transistor T9, and the drain electrode of the tenth transistor T10 may be connected to the first node N1.

[0130] The ninth transistor T9 may be turned on by the fourth gate signal EB of the fourth gate line EBL so that the bias voltage line VBL is electrically connected to the first node N1. The ninth transistor T9 may be turned on according to the fourth gate signal EB to supply the bias voltage VB to the first node N1. The ninth transistor T9 may improve the hysteresis of the first transistor T1 by supplying the bias voltage VB to the source electrode of the first transistor T1 connected to the first node N1. The gate electrode of the ninth transistor T9 may be electrically connected to the fourth gate line EBL, the source electrode thereof may be electrically connected to the bias voltage line VBL, and the drain electrode thereof may be electrically connected to the first node N1.

[0131] The tenth transistor T10 may be turned on by the second gate signal GC of the second gate line GCL so that the driving voltage line VDL is electrically connected to the first node N1. For example, a gate electrode of the tenth transistor T10 may be electrically connected to the second gate line GCL, a source electrode thereof may be electrically connected to the driving voltage line VDL, and a drain electrode thereof may be electrically connected to the first node N1.

[0132] When the eighth transistor T8 , the first transistor T1 , and the sixth transistor T6 are all turned on, a driving current may be supplied to the light emitting element LEL.

[0133] Each of the first transistor T1 to the tenth transistor T10 may include a silicon-based active layer. For example, each of the first transistor T1 to the tenth transistor T10 may be a p-type transistor including an active layer made of low temperature polysilicon (LTPS). The active layer made of low temperature polysilicon may have high electron mobility and excellent conduction characteristics. Therefore, in the display device 10, since a transistor having excellent conduction characteristics is included, a plurality of pixels PX can be driven stably and efficiently. Each of the first transistor T1 to the tenth transistor T10 may output a current flowing from a source electrode to a drain electrode in response to a gate low voltage applied to a gate electrode of the corresponding transistor.

[0134] Alternatively, some of the first to tenth transistors T1 to T10 may be p-type transistors including an active layer made of the above-mentioned low temperature polycrystalline silicon (LTPS), and other transistors of the first to tenth transistors T1 to T10 may be n-type transistors including an oxide-based active layer. The transistor including the oxide-based active layer may have a coplanar structure on which the gate electrode is disposed. The transistor including the oxide-based active layer may output a current flowing from the drain electrode to the source electrode in response to a gate high voltage applied to the gate electrode.

[0135] The first capacitor Cst may be electrically connected between the fifth node N5 and the third node N3. For example, a first electrode of the first capacitor Cst may be electrically connected to the fifth node N5, and a second electrode of the first capacitor Cst may be electrically connected to the third node N3. The first capacitor Cst may maintain a data voltage supplied from the data line DL through the second transistor T2 for one frame period.

[0136] The second capacitor Chold may be electrically connected between the driving voltage line VDL and the fifth node N5. For example, a first electrode of the second capacitor Chold may be electrically connected to the fifth node N5, and a second electrode of the second capacitor Chold may be electrically connected to the driving voltage line VDL. The second capacitor Chold may maintain a potential difference between the driving voltage line VDL and the gate electrode of the first transistor T1.

[0137] Figure 6 is a plan view of a unit pixel array according to an embodiment. Figure 7 is selectively shown only Figure 6 A plan view of a first pattern layer and a second pattern layer of an assembly. Figure 8 is selectively shown only Figure 6 A plan view of the third patterned layer of the assembly. Fig. 9 is selectively shown only Figure 6 A plan view of the first pattern layer to the third pattern layer of a component. Fig.10 is selectively shown only Figure 6A plan view of the fourth patterned layer of the assembly. Fig.11 is selectively shown only Figure 6 A plan view of the first to fourth pattern layers of a component. Fig.12 is selectively shown only Figure 6 A plan view of the fifth patterned layer of the assembly. Fig.13 is selectively shown only Figure 6 A plan view of the sixth pattern layer of the assembly. Fig.14 is selectively shown only Figure 6 A plan view of the first to fifth pattern layers of a component. Fig.15 is selectively shown only Figure 6 A plan view of the fifth pattern layer and the sixth pattern layer of the component. Fig.16 is selectively shown only Figure 6 A plan view of the sixth pattern layer and the seventh pattern layer of the component.

[0138] At the same time, if Figure 6 As shown in , the contact holes can be classified into first type contact holes CTa, second type contact holes CTb and third type contact holes CTc. The first type contact hole CTa can be a contact hole for connecting the fifth pattern layer to the pattern layer disposed thereunder (e.g., at least one of the second pattern layer to the fourth pattern layer). The second type contact hole CTb can be a contact hole for connecting the sixth pattern layer to the pattern layer disposed thereunder (e.g., the fifth pattern layer). The third type contact hole CTc can be a contact hole for connecting the seventh pattern layer to the pattern layer disposed thereunder (e.g., the sixth pattern layer).

[0139] The first pattern layer may be disposed on the substrate SUB along the third direction DR3. The first pattern layer may include Figure 6 and Figure 7 The active layer in the example shown in .

[0140] The active layer ACT may provide channel regions CH1 to CH10 of the first to tenth transistors T1 to T10, first electrodes E11, E211, E221, E31, E411, E421, E511, E521, E61, E71, E81, E91, and E101, and second electrodes E12, E212, E222, E32, E412, E422, E512, E522, E62, E72, E82, E92, and E102. Here, the first electrode of each of the first to tenth transistors T1 to T10 may be one of the source electrode and the drain electrode, and the second electrode of each of the first to tenth transistors T1 to T10 may be the other of the source electrode and the drain electrode.

[0141] The active layer ACT may be a semiconductor layer made of low temperature polysilicon (LTPS).

[0142] The second pattern layer may be arranged on the first pattern layer along the third direction DR3. The insulating layer may be arranged between the first pattern layer and the second pattern layer. Figure 6 and Figure 7 In the example shown in , the second pattern layer may include first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, and tenth gate electrodes GE1, GE2, GE3, GE4, GE5, GE6, GE7, GE8, GE9, and GE10.

[0143] The first to tenth gate electrodes GE1 to GE10 may overlap the corresponding active layers ACT, respectively. Channel regions CH1 to CH10 of the first to tenth transistors T1 to T10 may be formed in overlapping regions between the active layers ACT and the first to tenth gate electrodes GE1 to GE10, respectively.

[0144] The first transistor T1 may include a first gate electrode GE1, a first electrode E11, a second electrode E12, and a first channel region CH1.

[0145] The second transistor T2 may be formed as a dual-gate transistor including a second-first transistor T2-1 and a second-second transistor T2-2. The second-first transistor T2-1 may include a second-first gate electrode GE2-1, a first electrode E211, a second electrode E212, and a second-first channel region CH2-1. The second-second transistor T2-2 may include a second-second gate electrode GE2-2, a first electrode E221, a second electrode E222, and a second-second channel region CH2-2. Here, the second-first gate electrode GE2-1 and the second-second gate electrode GE2-2 may be formed integrally.

[0146] The third transistor T3 may include a third gate electrode GE3 , a first electrode E31 , a second electrode E32 , and a third channel region CH3 .

[0147] The fourth transistor T4 may be formed as a dual-gate transistor including a fourth-first transistor T4-1 and a fourth-second transistor T4-2. The fourth-first transistor T4-1 may include a fourth-first gate electrode GE4-1, a first electrode E411, a second electrode E412, and a fourth-first channel region CH4-1. The fourth-second transistor T4-2 may include a fourth-second gate electrode GE4-2, a first electrode E421, a second electrode E422, and a fourth-second channel region CH4-2. Here, the fourth-first gate electrode GE4-1 and the fourth-second gate electrode GE4-2 may be integrally formed.

[0148] The fifth transistor T5 may be formed as a dual-gate transistor including a fifth-first transistor T5-1 and a fifth-second transistor T5-2. The fifth-first transistor T5-1 may include a fifth-first gate electrode GE5-1, a first electrode E511, a second electrode E512, and a fifth-first channel region CH5-1. The fifth-second transistor T5-2 may include a fifth-second gate electrode GE5-2, a first electrode E521, a second electrode E522, and a fifth-second channel region CH5-2.

[0149] The sixth transistor T6 may include a sixth gate electrode GE6 , a first electrode E61 , a second electrode E62 , and a sixth channel region CH6 .

[0150] The seventh transistor T7 may include a seventh gate electrode GE7 , a first electrode E71 , a second electrode E72 , and a seventh channel region CH7 .

[0151] The eighth transistor T8 may include an eighth gate electrode GE8, a first electrode E81, a second electrode E82, and an eighth channel region CH8. Here, the eighth gate electrode GE8 and the sixth gate electrode GE6 may be integrally formed.

[0152] The ninth transistor T9 may include a ninth gate electrode GE9, a first electrode E91, a second electrode E92, and a ninth channel region CH9. Here, the ninth gate electrode GE9 and the seventh gate electrode GE7 may be integrally formed.

[0153] The tenth transistor T10 may include a tenth gate electrode GE10, a first electrode E101, a second electrode E102, and a tenth channel region CH10. Fig.14 As shown in FIG. 1 , the tenth gate electrode GE10 , the fifth-first gate electrode GE5 - 1 , and the third gate electrode GE3 may be integrally formed.

[0154] The third pattern layer may be arranged on the second pattern layer along the third direction DR3. The insulating layer may be arranged between the second pattern layer and the third pattern layer. Figure 6 , Figure 8 and Fig. 9 In the example shown in , the third pattern layer may include the parasitic capacitor electrode PCPE, the first initialization voltage line VIL1, and the lower capacitor electrode CPEa.

[0155] The parasitic capacitor electrode PCPE may be stacked with the active layer ACT, as in Figure 6 and Fig. 9In the example shown in . For example, the parasitic capacitor electrode PCPE may be stacked with the active layer ACT corresponding to the connection portion between the second-first transistor T2-1 and the second-second transistor T2-2. Here, the second-first transistor T2-1 and the second-second transistor T2-2 are sub-transistors of the second transistor T2 as a dual-gate transistor. In addition, the parasitic capacitor electrode PCPE may be stacked with the active layer ACT corresponding to the connection portion between the fourth-first transistor T4-1 and the fourth-second transistor T4-2. Here, the fourth-first transistor T4-1 and the fourth-second transistor T4-2 are sub-transistors of the fourth transistor T4 as a dual-gate transistor.

[0156] The first initialization voltage line VIL1 may overlap the active layer ACT, such as Figure 6 , Figure 8 and Fig. 9 As shown in . For example, the first initialization voltage line VIL1 may overlap with the active layer ACT corresponding to the connection portion between the fifth-first transistor T5-1 and the fifth-second transistor T5-2. Here, the fifth-first transistor T5-1 and the fifth-second transistor T5-2 are sub-transistors of the fifth transistor T5 as a dual-gate transistor. In addition, the first initialization voltage line VIL1 may overlap with the active layer ACT corresponding to the connection portion between the fourth-first transistor T4-1 and the third transistor T3. In addition, the first initialization voltage line VIL1 may overlap with the first electrode E31 of the third transistor T3. A parasitic capacitor may be formed in the overlapping region between the first initialization voltage line VIL1 and the active layer ACT. The first initialization voltage line VIL1 may transmit the first initialization voltage VIT1.

[0157] The lower capacitor electrode CPEa may be disposed to overlap the first gate electrode GE1, such as Figure 6 and Fig. 9As shown in . The first capacitor Cst may be formed in a region where the lower capacitor electrode CPEa overlaps the first gate electrode GE1. For example, the lower capacitor electrode CPEa and the first gate electrode GE1 may correspond to the first electrode and the second electrode of the first capacitor Cst, respectively. In addition, the lower capacitor electrode CPEa may have a hole 40 passing through it in the third direction. The first gate electrode GE1 may be connected to the first electrode E31 of the third transistor T3 through the hole 40 of the first capacitor Cst, the second hole 52 of the upper capacitor electrode CPEb, and the gate connection electrode GCE described later. In addition, the lower capacitor electrode CPEa may be connected to the second electrode E222 of the second-second transistor T2-2 and the first electrode E521 of the fifth-second transistor T5-2 through the first hole 51 of the upper capacitor electrode CPEb and the capacitor connection electrode CCE described later. In addition, the area of ​​the lower capacitor electrode CPEa may be greater than the area of ​​the first gate electrode GE1. In this case, the area of ​​the lower capacitor electrode CPEa may mean, for example, an area including the area (or size) of the hole 40.

[0158] The fourth pattern layer may be arranged on the third pattern layer along the third direction DR3. The insulating layer may be arranged between the third pattern layer and the fourth pattern layer. Figure 6 , Fig.10 and Fig.11 In the example shown in , the fourth pattern layer may include the upper capacitor electrode CPEb and the repair line RPL.

[0159] like Figure 6 and Fig.11 As shown in , the upper capacitor electrode CPEb may be disposed to overlap the lower capacitor electrode CPEa and the first gate electrode GE1 .

[0160] The second capacitor Chold may be formed in an area where the upper capacitor electrode CPEb and the lower capacitor electrode CPEa overlap. For example, the lower capacitor electrode CPEa and the upper capacitor electrode CPEb may correspond to the first electrode and the second electrode of the second capacitor Chold, respectively. In addition, the upper capacitor electrode CPEb may have more holes than the lower capacitor electrode CPEa. For example, the upper capacitor electrode CPEb may have a first hole 51 and a second hole 52 passing through it in the third direction. The first gate electrode GE1 may be connected to the first electrode E31 of the third transistor T3 through the hole 40 of the first capacitor Cst, the second hole 52 of the upper capacitor electrode CPEb, and the gate connection electrode GCE. In addition, the upper capacitor electrode CPEb may be connected to the drive voltage line VDL, the second electrode E512 of the fifth-first transistor T5-1, the second electrode E102 of the tenth transistor T10, and the first electrode E81 of the eighth transistor T8 through the drive connection electrode VCE. In addition, the area of ​​the upper capacitor electrode CPEb may be larger than the area of ​​the lower capacitor electrode CPEa. In this case, the area of ​​the lower capacitor electrode CPEa may mean an area including the area (or size) of the hole 40 , and the area of ​​the upper capacitor electrode CPEb may mean an area including the areas (or sizes) of the first and second holes 51 and 52 .

[0161] like Figure 6As shown in , the repair line RPL may overlap with the ends of the extensions EX of the upper pixel connection electrode PCEb and the lower pixel connection electrode PCEa, which will be described later. For example, the repair line RPL may include a repair short circuit portion RSP, which is a portion of the repair line RPL that protrudes in the second direction DR2 and overlaps with the connection portion between the lower pixel connection electrode PCEa and the pixel electrode PE. For example, the repair line RPL may be used to repair a defective pixel. The repair short circuit portion RSP of the repair line RPL is a portion to which a laser or the like is irradiated during the repair process of a defective pixel (e.g., an unlit pixel), and the pixel connection electrodes PCEa and PCEb of the defective pixel and the repair line RPL may be connected by laser irradiation. At the same time, in the repair process, before or after the above-mentioned laser irradiation, for example, a step of separating the connection between one side of the lower pixel connection electrode PCEa of the defective pixel and the corresponding pixel circuit PC may be first performed. For example, a portion of the extension EX of the lower pixel connection electrode PCEa may be laser cut before or after laser irradiation. Therefore, the end of the lower pixel connection electrode PCEa connected to the upper pixel connection electrode PCEb may be disconnected from the fourth node N4 (e.g., the connection portion between the sixth transistor T6 and the seventh transistor T7). After the repair process, a driving voltage may be applied to the pixel electrode PE of the defective pixel through the repair line RPL instead of the pixel circuit PC. The repair line RPL may be connected to a separate dummy pixel so that the dummy pixel may apply the above-mentioned driving voltage to the repair line RPL.

[0162] According to the present disclosure, the second electrode (e.g., the upper capacitor electrode CPEb) of the second capacitor Chold and the repair line RPL may be formed by the fourth pattern layer. In other words, according to the present disclosure, the upper capacitor electrode CPEb and the repair line RPL may be formed together in a pattern layer (e.g., the fourth pattern layer) other than the second pattern layer and the third pattern layer used to form the first capacitor Cst. In this case, as Fig.11 As shown in , since the repair line RPL included in the fourth pattern layer and the sixth gate electrode GE6 and the eighth gate electrode GE8 included in the third pattern layer are arranged in different layers, the minimum distance d1 between the repair line RPL (e.g., the repair short circuit portion RSP of the repair line RPL) and the sixth gate electrode GE6 and the eighth gate electrode GE8 in the second direction in the plan view can be further reduced. Similarly, as Fig.11As shown, since the repair line RPL included in the fourth pattern layer and the seventh gate electrode GE7 and the ninth gate electrode GE9 included in the third pattern layer are arranged in different layers, the minimum distance d2 between the repair line RPL and the seventh gate electrode GE7 and the ninth gate electrode GE9 in the second direction in the plan view can be further reduced. In addition, the insulating layer (for example, the repair line RPL) arranged between the fourth pattern layer (for example, the repair line RPL) and the second pattern layer including the sixth gate electrode GE6, the seventh gate electrode GE7, the eighth gate electrode GE8, and the ninth gate electrode GE9 is Fig.17 The thickness of the first interlayer insulating layer ITL1 and the second interlayer insulating layer ITL2 (eg, ) thick, so that the minimum distance between the gate electrode and the repair line (eg, d1 and d2) can be further reduced without being affected by the laser during the repair process. As a result, the pixel size can be reduced, which can increase the resolution.

[0163] The fifth pattern layer may be disposed on the fourth pattern layer along the third direction DR3. The insulating layer may be disposed between the fourth pattern layer and the fifth pattern layer. Figure 6 , Fig.12 and Fig.14 In the example shown in , the fifth pattern layer may include a third gate line GIL, a first gate line GWL, a data connection electrode DCE, an active connection electrode ACE, a second gate line GCL, a drive connection electrode VCE, a capacitor connection electrode CCE, a gate connection electrode GCE, an emission control line EML, a lower pixel connection electrode PCEa, a second initialization voltage line VIL2 and a bias voltage line VBL.

[0164] The third gate line GIL can be Fig.14 The fourth-first gate electrode GE4-1 and the fourth-second gate electrode GE4-2 are connected to each other through the first type contact hole CTa of the insulating layer as shown in FIG.

[0165] The first gate line GWL may be Fig.14 The gate electrodes GE2 - 1 and GE2 - 2 are connected to each other through the first type contact hole CTa of the insulating layer as shown in FIG.

[0166] The data connection electrode DCE can be Fig.14 1 is connected to the first electrode E211 of the active layer ACT (eg, the first electrode E211 of the second-first transistor T2 - 1 ) through the first type contact hole CTa of the insulating layer as shown in FIG.

[0167] The active connection electrode ACE can be Fig.14As shown in FIG. 1 , the transistor is connected to the second electrode E422 of the active layer ACT (eg, the second electrode E422 of the fourth-second transistor T4-2) and the second electrode E32 of the active layer ACT (eg, the second electrode E32 of the third transistor T3) through the first type contact hole CTa of the insulating layer.

[0168] The second gate line GCL may be Fig.14 The gate electrodes GE5 - 1 and GE5 - 2 are connected to the tenth gate electrode GE10 , the fifth-first gate electrode GE5 - 1 , the fifth-second gate electrode GE5 - 2 , and the third gate electrode GE3 through the first type contact hole CTa of the insulating layer as shown in FIG.

[0169] The driving connection electrode VCE can be Fig.14 As shown in the figure, it is connected to the second electrode E512 of the active layer ACT (e.g., the second electrode E512 of the fifth-first transistor T5-1), the upper capacitor electrode CPEb and the first electrode E81 of the active layer ACT (e.g., the first electrode E81 of the eighth transistor T8) through the first type contact hole CTa of the insulating layer.

[0170] The capacitor connection electrode CCE can be Fig.14 As shown in FIG. 1 , the capacitor connection electrode CCE is connected to the second electrode E222 of the active layer ACT (e.g., the second electrode E222 of the second-second transistor T2-2) through the first type contact hole CTa of the insulating layer. In addition, the capacitor connection electrode CCE can be connected to the lower capacitor electrode CPEa through the first type contact hole CTa of the insulating layer and the first hole 51 of the upper capacitor electrode CPEb.

[0171] like Fig.14 As shown in , the gate connection electrode GCE can be connected to the first electrode E31 of the active layer ACT (for example, the first electrode E31 of the third transistor T3) through the first type contact hole CTa of the insulating layer. In addition, the gate connection electrode GCE can be connected to the first gate electrode GE1 through the first type contact hole CTa of the insulating layer, the second hole 52 of the upper capacitor electrode CPEb, and the hole 40 of the lower capacitor electrode CPEa.

[0172] like Fig.14 As shown in , the emission control line EML may be connected to the sixth gate electrode GE6 and the eighth gate electrode GE8 through the first type contact hole CTa of the insulating layer.

[0173] like Fig.14 As shown in , the lower pixel connection electrode PCEa may be connected to the second electrode E62 of the active layer ACT (eg, the second electrode E62 of the sixth transistor T6 ) through the first type contact hole CTa of the insulating layer.

[0174] The second initialization voltage line VIL2 may include a second-first initialization voltage line VIL2-1 and a second-second initialization voltage line VIL2-2 that are separated from each other. The second-first initialization voltage line VIL2-1 and the second-second initialization voltage line VIL2-2 may transmit initialization voltages of different magnitudes.

[0175] The second-first initialization voltage line VIL2-1 may be connected to any one of the three pixels displaying different colors. For example, the second-first initialization voltage line VIL2-1 may be connected to the seventh transistor T7 of the green pixel providing light corresponding to the green wavelength. For example, the second-first initialization voltage line VIL2-1 may be connected to the second electrode E72 of the active layer ACT disposed in the red pixel (e.g., the second electrode E72 of the seventh transistor T7) through the first type contact hole CTa of the insulating layer.

[0176] The second-second initialization voltage line VIL2-2 may be connected to the remaining two pixels having different colors among the above three pixels. For example, the second-second initialization voltage line VIL2-2 may be connected to the seventh transistor T7 of the red pixel providing light corresponding to the red wavelength and the seventh transistor T7 of the blue pixel providing light corresponding to the blue wavelength. For example, the second-second initialization voltage line VIL2-2 may be connected to the second electrode E72 (e.g., the second electrode E72 of the seventh transistor T7) of the active layer ACT disposed in the red pixel through the first type contact hole CTa of the insulating layer. In addition, the second-second initialization voltage line VIL2-2 may be connected to the second electrode E72 (e.g., the second electrode E72 of the seventh transistor T7) of the active layer ACT disposed in the blue pixel through the first type contact hole CTa of the insulating layer.

[0177] The bias voltage line VBL can transmit the bias voltage VB. Fig.14 As shown in , the bias voltage line VBL may be connected to the second electrode E92 of the active layer ACT (eg, the second electrode E92 of the ninth transistor T9 ) and the parasitic capacitor electrode PCPE through the first type contact hole CTa of the insulating layer.

[0178] The sixth pattern layer may be disposed on the fifth pattern layer along the third direction DR3. The insulating layer may be disposed between the fifth pattern layer and the sixth pattern layer. Figure 6 , Fig.13 and Fig.15 In the example shown in , the sixth pattern layer may include the data line DL, the driving voltage line VDL, and the upper pixel connection electrode PCEb.

[0179] like Fig.15As shown in FIG. 1 , the data line DL may be connected to the data link electrode DCE through the second type contact hole CTb of the insulating layer.

[0180] like Fig.15 As shown in , the driving voltage line VDL may be connected to the driving connection electrode VCE through the second type contact hole CTb of the insulating layer.

[0181] like Fig.15 As shown in FIG. 1 , the upper pixel connection electrode PCEb may be connected to the lower pixel connection electrode PCEa through the second type contact hole CTb of the insulating layer.

[0182] The seventh pattern layer may be disposed on the sixth pattern layer along the third direction DR3. The insulating layer may be disposed between the sixth pattern layer and the seventh pattern layer. Figure 6 and Fig.16 In the example shown in , the seventh pattern layer may include a pixel electrode PE.

[0183] A portion of the pixel electrode PE may be exposed by a bank to be described later. For example, the bank may have a portion of an opening (hereinafter, an emission region) exposing the pixel electrode PE. A light emitting layer may be provided on the pixel electrode PE corresponding to the emission region.

[0184] The pixel electrode PE may be connected to the upper pixel connection electrode PCEb through the third type contact hole CTc of the insulating layer.

[0185] Fig.17 It is along Figure 6 A cross-sectional view taken along line II' of Fig.18 It is along Figure 6 A cross-sectional view taken along line II-II'.

[0186] like Fig.17 and Fig.18 As shown in FIG, the display device 10 may include a substrate SUB, a barrier layer BR, a thin film transistor layer TFTL, a light emitting element layer EMTL, and an encapsulation layer ENC. The barrier layer BR, the thin film transistor layer TFTL, the light emitting element layer EMTL, and the encapsulation layer ENC may be sequentially disposed on the substrate SUB along a third direction DR3.

[0187] The substrate SUB may be a rigid substrate or a flexible substrate that can be bent, folded or curled. The substrate SUB may be formed of an insulating material such as glass, quartz or a polymer resin. Examples of polymer materials may include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (TAC), cellulose acetate propionate (CAP) or a combination thereof. Alternatively, the substrate SUB may include a metal material.

[0188] like Fig.17 and Fig.18 As shown in , a barrier layer BR may be disposed on a substrate SUB. The barrier layer BR may be disposed on the entire surface of the substrate SUB. The barrier layer BR may be a layer for protecting the transistors T1 to T8 of the thin film transistor layer TFTL and the light emitting layer EL of the light emitting element layer EMTL from moisture penetrating through the substrate SUB that is easily permeated by moisture.

[0189] The barrier layer BR may be formed of a plurality of inorganic layers alternately stacked. For example, the barrier layer BR may be formed of a plurality of layers in which one or more inorganic layers of silicon nitride layer, silicon oxynitride layer, silicon oxide layer, titanium oxide layer and aluminum oxide layer are alternately stacked.

[0190] like Fig.17 and Fig.18 As shown in , the buffer layer BF may be disposed on the barrier layer BR. The buffer layer BF may be disposed on the entire surface of the substrate SUB including the barrier layer BR. The buffer layer BF may be a layer for protecting the transistors T1 to T8 of the thin film transistor layer TFTL and the light emitting layer EL of the light emitting element layer EMTL from moisture penetrating through the substrate SUB that is easily permeated by moisture.

[0191] The buffer layer BF may be formed of a plurality of inorganic layers alternately stacked. For example, the buffer layer BF may be formed of a plurality of layers in which one or more inorganic layers of silicon nitride layer, silicon oxynitride layer, silicon oxide layer, titanium oxide layer and aluminum oxide layer are alternately stacked.

[0192] The first pattern layer may be disposed on the buffer layer BF. For example, the active layer ACT may be disposed on the buffer layer BF. Fig.17 and Fig.18 As shown in , the active layer ACT may include a first electrode E11 of the first transistor T1, a second electrode E12 of the first transistor T1, a first channel region CH1 of the first transistor T1, a first electrode E61 of the sixth transistor T6, a second electrode E62 of the sixth transistor T6, and a sixth channel region CH6 of the sixth transistor T6.

[0193] The active layer ACT may be an active layer made of low temperature polysilicon (LTPS).

[0194] The gate insulating layer GTI may be disposed on the first pattern layer. Fig.17 and Fig.18 As shown in , the gate insulating layer GTI may be disposed on the active layer ACT. In this case, the gate insulating layer GTI may be disposed on the entire surface of the substrate SUB including the first active layer ACT1.

[0195] The gate insulating layer GTI may include tetraethyl orthosilicate (TEOS), silicon nitride (SiN x ) and silicon oxide (SiO 2 For example, the gate insulating layer GTI may have a double-layer structure in which a silicon nitride layer having a thickness of 40 nm and a tetraethyl orthosilicate layer having a thickness of 80 nm are sequentially stacked.

[0196] The second pattern layer may be disposed on the gate insulating layer GTI. For example, a first gate electrode GE1, a second gate electrode GE2, a third gate electrode GE3, a fourth gate electrode GE4, a fifth gate electrode GE5, a sixth gate electrode GE6, a seventh gate electrode GE7, an eighth gate electrode GE8, a ninth gate electrode GE9, and a tenth gate electrode GE10 may be disposed on the gate insulating layer GTI.

[0197] Fig.17 and Fig.18 An example is shown in which the first gate electrode GE1, the sixth gate electrode GE6, the seventh gate electrode GE7, and the ninth gate electrode GE9 are disposed on the gate insulating layer GTI. The first gate electrode GE1 may be disposed on the gate insulating layer GTI to overlap with the first channel region CH1 of the active layer ACT. The sixth gate electrode GE6 may be disposed on the gate insulating layer GTI to overlap with the sixth channel region CH6 of the active layer ACT.

[0198] The second pattern layer may include at least one of molybdenum (Mo), copper (Cu), aluminum and titanium (Ti), and may be formed of a single layer or multiple layers. For example, the first gate electrode GE1 may be formed of three layers including a titanium layer, an aluminum layer and a titanium layer sequentially disposed on the gate insulating layer GTI along the third direction DR3.

[0199] The first interlayer insulating layer ITL1 may be disposed on the second pattern layer. Fig.17 and Fig.18As shown in FIG, the first interlayer insulating layer ITL1 may be disposed on the first gate electrode GE1, the sixth gate electrode GE6, the seventh gate electrode GE7, and the ninth gate electrode GE9. In this case, the first interlayer insulating layer ITL1 may be disposed on the entire surface of the substrate SUB including the first gate electrode GE1, the sixth gate electrode GE6, the seventh gate electrode GE7, and the ninth gate electrode GE9.

[0200] The first interlayer insulating layer ITL1 may include an inorganic layer, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. Meanwhile, the first interlayer insulating layer ITL1 may include a plurality of inorganic layers.

[0201] The third pattern layer may be disposed on the first interlayer insulating layer ITL1. For example, the parasitic capacitor electrode PCPE, the first initialization voltage line VIL1, and the lower capacitor electrode CPEa may be disposed on the first interlayer insulating layer ITL1. Fig.17 An example is shown in which the lower capacitor electrode CPEa is disposed on the first interlayer insulating layer ITL1. The lower capacitor electrode CPEa may be disposed on the first interlayer insulating layer ITL1 to overlap the first gate electrode GE1. The first capacitor Cst may be formed by the lower capacitor electrode CPEa and the first gate electrode GE1.

[0202] The third pattern layer may have the same material and structure as the second pattern layer.

[0203] The second interlayer insulating layer ITL2 may be disposed on the third pattern layer. Fig.17 and Fig.18 As shown in , the second interlayer insulating layer ITL2 may be disposed on the lower capacitor electrode CPEa. In this case, the second interlayer insulating layer ITL2 may be disposed on the entire surface of the substrate SUB including the lower capacitor electrode CPEa.

[0204] The second interlayer insulating layer ITL2 may have the same material and structure as those of the above-described first interlayer insulating layer ITL1 .

[0205] The fourth pattern layer may be disposed on the second interlayer insulating layer ITL2. For example, the upper capacitor electrode CPEb and the repair line RPL may be disposed on the second interlayer insulating layer ITL2. Fig.17 As shown in FIG. 1 , the upper capacitor electrode CPEb may be disposed on the second interlayer insulating layer ITL2 to overlap with the lower capacitor electrode CPEa. The second capacitor Chold may be formed by the upper capacitor electrode CPEb and the lower capacitor electrode CPEa.

[0206] The third interlayer insulating layer ITL3 may be disposed on the fourth pattern layer. Fig.17 and Fig.18As shown in FIG. 1 , a third interlayer insulating layer ITL3 may be disposed on the upper capacitor electrode CPEb and the repair line RPL. The third interlayer insulating layer ITL3 may be disposed on the entire surface of the substrate SUB including the upper capacitor electrode CPEb and the repair line RPL.

[0207] The third interlayer insulating layer ITL3 may have the same material and structure as those of the above-described first interlayer insulating layer ITL1 .

[0208] The fifth pattern layer may be disposed on the third interlayer insulating layer ITL3. For example, the third gate line GIL, the first gate line GWL, the data connection electrode DCE, the active connection electrode ACE, the second gate line GCL, the driving connection electrode VCE, the capacitor connection electrode CCE, the gate connection electrode GCE, the emission control line EML, the lower pixel connection electrode PCEa, the second initialization voltage line VIL2, and the bias voltage line VBL may be disposed on the third interlayer insulating layer ITL3. Fig.17 and Fig.18 An example is shown in which the driving connection electrode VCE, the capacitor connection electrode CCE, the gate connection electrode GCE, the lower pixel connection electrode PCEa, and the emission control line EML are disposed on the third interlayer insulating layer ITL3.

[0209] The driving connection electrode VCE may be connected to the upper capacitor electrode CPEb through a first contact hole CT1 penetrating the third interlayer insulating layer ITL3 .

[0210] The capacitor connection electrode CCE may be connected to the lower capacitor electrode CPEa through the first hole 51 penetrating the third interlayer insulating layer ITL3 , the upper capacitor electrode CPEb, and the second contact hole CT2 of the second interlayer insulating layer ITL2 .

[0211] The gate connection electrode GCE may be connected to the first gate electrode GE1 through the second hole 52 penetrating the third interlayer insulating layer ITL3 , the upper capacitor electrode CPEb, the second interlayer insulating layer ITL2 , the hole 40 of the lower capacitor electrode CPEa, and the third contact hole CT3 of the first interlayer insulating layer ITL1 .

[0212] The lower pixel connection electrode PCEa may be connected to the second electrode E62 of the sixth transistor T6 through a fifth contact hole CT5 penetrating the third interlayer insulating layer ITL3 , the second interlayer insulating layer ITL2 , the first interlayer insulating layer ITL1 , and the gate insulating layer GTI.

[0213] The first contact hole CT1 , the second contact hole CT2 , the third contact hole CT3 , and the fifth contact hole CT5 may belong to the first type contact hole CTa.

[0214] The fifth pattern layer may have the same material or structure as the second pattern layer.

[0215] The first planarization layer VA1 may be disposed on the fifth pattern layer. For example, the first planarization layer VA1 may be disposed on the drive connection electrode VCE, the capacitor connection electrode CCE, the gate connection electrode GCE, the lower pixel connection electrode PCEa, and the emission control line EML. The first planarization layer VA1 may be disposed on the entire surface of the substrate SUB including the drive connection electrode VCE, the capacitor connection electrode CCE, the gate connection electrode GCE, the lower pixel connection electrode PCEa, and the emission control line EML.

[0216] The first planarization layer VA1 may include an organic layer such as acryl resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like.

[0217] The sixth pattern layer may be disposed on the first planarization layer VA1. Fig.17 As shown in FIG. 1 , the data line DL, the driving voltage line VDL, and the upper pixel connection electrode PCEb may be disposed on the first planarization layer VA1 .

[0218] The driving voltage line VDL may be connected to the driving connection electrode VCE through a fourth contact hole CT4 penetrating the first planarization layer VA1 .

[0219] The upper pixel link electrode PCEb may be connected to the lower pixel link electrode PCEa through a sixth contact hole CT6 penetrating the first planarization layer VA1 .

[0220] The fourth contact hole CT4 and the sixth contact hole CT6 may belong to the second type contact hole CTb.

[0221] The sixth pattern layer may have the same material or structure as the second pattern layer.

[0222] The second planarization layer VA2 may be disposed on the sixth pattern layer. For example, the second planarization layer VA2 may be disposed on the data line DL, the driving voltage line VDL, and the upper pixel connection electrode PCEb. The second planarization layer VA2 may be disposed on the entire surface of the substrate SUB including the data line DL, the driving voltage line VDL, and the upper pixel connection electrode PCEb.

[0223] The second planarization layer VA2 may have the same material and structure as those of the first planarization layer VA1 described above.

[0224] The seventh pattern layer may be disposed on the second planarization layer VA2. Fig.17 and Fig.18 As shown in FIG. 1 , the light emitting element layer EMTL including the seventh pattern layer may be disposed on the second planarization layer VA2 . For example, the pixel electrode PE as the seventh pattern layer may be disposed on the second planarization layer VA2 .

[0225] The pixel electrode PE may be connected to the upper pixel connection electrode PCEb through a seventh contact hole CT7 penetrating the second planarization layer VA2 .

[0226] The seventh contact hole CT7 may belong to the third type contact hole CTc.

[0227] In addition to the seventh pattern layer, the light emitting element layer EMTL may further include a light emitting element LEL and a bank PDL (or a pixel defining layer).

[0228] The light emitting element LEL may include a pixel electrode PE, a light emitting layer EL, and a common electrode CM. An emission region EA in which the pixel electrode PE, the light emitting layer EL, and the common electrode CM are sequentially stacked indicates a region in which holes from the pixel electrode PE and electrons from the common electrode CM recombine with each other in the light emitting layer EL to emit light. In this case, the pixel electrode PE may be an anode electrode of the light emitting element LEL, and the common electrode CM may be a cathode electrode of the light emitting element LEL.

[0229] In a top emission structure that emits light toward the common electrode CM relative to the light emitting layer EL, the pixel electrode PE may be formed of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may be formed to have a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, or a stacked structure of an APC alloy and ITO (ITO / APC / ITO) to increase reflectivity. The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0230] The embankment PDL (or pixel defining layer) may be used to define the emission area EA of the pixel. To this end, the embankment PDL may be configured to expose a portion of the pixel electrode PE on the second planarization layer VA2. The embankment PDL may cover the edge of the pixel electrode PE. At the same time, the embankment PDL may fill a recessed portion disposed on the seventh contact hole CT7 penetrating the second planarization layer VA2. Therefore, the recessed portion disposed on the seventh contact hole CT7 penetrating the second planarization layer VA2 may be filled with the embankment PDL. The embankment PDL may be formed of an organic layer such as an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0231] like Fig.17 and Fig.18As shown in , the spacer SPC may be disposed on the bank PDL. The spacer SPC may be used to support a mask during a process of manufacturing the light emitting layer EL. The spacer SPC may be formed of an organic layer such as an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc. The spacer SPC may have the same material as the bank PDL and may be formed simultaneously with the bank PDL by using, for example, a halftone mask.

[0232] The light emitting layer EL may be formed on the pixel electrode PE. The light emitting layer EL may include an organic material to emit light of a predetermined color. For example, the light emitting layer EL may include a hole transport layer, an organic material layer, and an electron transport layer. The organic material layer may include a host and a dopant. The organic material layer may include a material that emits a predetermined light, and may be formed using a phosphorescent material or a fluorescent material.

[0233] The light emitting element LEL may be provided for each pixel. For example, the first pixel may include a first light emitting element, the second pixel may include a second light emitting element, and the third pixel may include a third light emitting element. The first light emitting element, the second light emitting element, and the third light emitting element may provide light of different colors. For example, the first light emitting element may emit light of a first color, the second light emitting element may emit light of a second color, and the third light emitting element may emit light of a third color.

[0234] For example, the organic material layer of the first light-emitting layer of the first emission region emitting light of the first color may be a phosphorescent material, the phosphorescent material including a host material and a dopant, the host material including carbazole biphenyl (CBP) or mCP (1,3-bis(carbazole-9-yl)), the dopant including at least one selected from the group consisting of PIQIr(acac) (bis(1-phenylisoquinoline) iridium acetylacetonate), PQIr(acac) (bis(1-phenylquinoline) iridium acetylacetonate), PQIr(tris(1-phenylquinoline) iridium) and PtOEP (octaethylporphyrin platinum). Optionally, the organic material layer of the first light-emitting layer of the first emission region may include PBD:Eu(DBM) 3 The present invention may include fluorescent materials of phenanthracene or perylene, but the present disclosure is not limited thereto.

[0235] The organic material layer of the second light-emitting layer of the second emission region emitting light of the second color may be a phosphorescent material, the phosphorescent material including a host material including CBP or mCP and a host material including Ir(ppy). 3 (tri-(2-phenylpyridine)iridium) dopant material. Optionally, the organic material layer of the second light-emitting layer of the second emission region emitting light of the second color may include tris(8-hydroxyquinoline)aluminum (Alq 3 ) of the fluorescent material, but the present disclosure is not limited thereto.

[0236] The organic material layer of the light-emitting layer of the third emission region emitting light of the third color may be a phosphorescent material, the phosphorescent material including a host material including CBP or mCP and a 2 ppy) 2 Irpic or L 2 BD 111 but the present disclosure is not limited thereto.

[0237] The common electrode CM may be disposed on the first light emitting layer, the second light emitting layer, and the third light emitting layer (e.g., EL). The common electrode CM may be disposed to cover the first light emitting layer, the second light emitting layer, and the third light emitting layer. The common electrode CM may be a common layer commonly disposed on the first to third light emitting layers. A covering layer may be formed on the common electrode CM.

[0238] In the top emission structure, the common electrode CM may be formed of a transparent conductive material (TCO) capable of transmitting light, such as ITO or IZO, or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the common electrode CM is formed of a semi-transmissive conductive material, light emission efficiency may be increased due to a microcavity effect.

[0239] The encapsulation layer ENC may be formed on the light emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic layer to prevent oxygen or moisture from penetrating into the light emitting element layer EMTL. In addition, the encapsulation layer ENC may include at least one organic layer to protect the light emitting element layer EMTL from foreign matter such as dust. For example, the encapsulation layer ENC may include a first inorganic encapsulation layer TFE1, an organic encapsulation layer TFE2, and a second inorganic encapsulation layer TFE3.

[0240] The first inorganic encapsulation layer TFE1 may be disposed on the common electrode CM, the organic encapsulation layer TFE2 may be disposed on the first inorganic encapsulation layer TFE1, and the second inorganic encapsulation layer TFE3 may be disposed on the organic encapsulation layer TFE2. The first inorganic encapsulation layer TFE1 and the second inorganic encapsulation layer TFE3 may be formed by a multilayer in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. The organic encapsulation layer TFE2 may be an organic layer such as an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc.

[0241] Fig.19 is a circuit diagram of one pixel of a display device according to an embodiment.

[0242] The pixel PX can be connected to the first gate line GWL, the second gate line GCL, the third gate line GIL, the fourth gate line EBL, the first emission control line EML1, the second emission control line EML2, the data line DL, the driving voltage line VDL, the common voltage line VSL, the reference voltage line VRL, the first initialization voltage line VIL1, the second initialization voltage line VIL2 and the bias voltage line VBL.

[0243] A pixel (eg, PX) may include a pixel circuit PC and a light emitting element LEL. The pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a first capacitor Cst, and a second capacitor Chold.

[0244] The first transistor T1 may include a gate electrode, a source electrode, and a drain electrode. The first transistor T1 may control a source-drain current (hereinafter, a driving current) according to a data voltage applied to the gate electrode. A driving current (Isd) flowing through a channel region of the first transistor T1 may be proportional to the square of a difference between a threshold voltage (Vth) and a voltage (Vsg) between a source electrode and a gate electrode of the first transistor T1 (Isd=k×(Vsg-Vth) 2 ). Here, k is a proportionality coefficient determined by the structure and physical characteristics of the first transistor T1, Vsg is the source-gate voltage of the first transistor ST1, and Vth is the threshold voltage of the first transistor T1.

[0245] The light emitting element LEL may emit light by receiving a driving current (Isd). The emission amount or brightness of the light emitting element LEL may be proportional to the magnitude of the driving current (Isd).

[0246] The light emitting element LEL may be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer disposed between the first electrode and the second electrode. For another example, the light emitting element LEL may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. For another example, the light emitting element LEL may be a quantum dot light emitting element including a first electrode, a second electrode, and a quantum dot light emitting layer disposed between the first electrode and the second electrode. For another example, the light emitting element LEL may be a micro light emitting diode.

[0247] A first electrode of the light emitting element LEL may be electrically connected to a fourth node N4. The first electrode of the light emitting element LEL may be connected to a drain electrode of the sixth transistor T6 and a source electrode of the seventh transistor T7 through the fourth node N4. A second electrode of the light emitting element LEL may be connected to a common voltage line VSL. The second electrode of the light emitting element LEL may receive a common voltage VS (e.g., a low potential voltage) from the common voltage line VSL.

[0248] The second transistor T2 may be turned on by the first gate signal GW of the first gate line GWL so that the data line DL is electrically connected to the fifth node N5. The drain electrode of the second transistor T2, the first electrode of the first capacitor Cst, the first electrode of the second capacitor Chold, and the source electrode of the fifth transistor T5 may be connected to the fifth node N5. The second transistor T2 may be turned on in response to the first gate signal GW to supply a data voltage to the fifth node N5. The gate electrode of the second transistor T2 may be electrically connected to the first gate line GWL, its source electrode may be electrically connected to the data line DL, and its drain electrode may be electrically connected to the fifth node N5. At the same time, the second transistor T2 may be configured as a dual-gate transistor. For example, the second transistor T2 may include a second-first transistor and a second-second transistor connected in series between the data line DL and the fifth node N5. The gate electrode of the second-first transistor may be electrically connected to the first gate line GWL, its source electrode may be electrically connected to the data line DL, and its drain electrode may be electrically connected to the source electrode of the second-second transistor. A gate electrode of the second-second transistor may be electrically connected to the first gate line GWL, a source electrode thereof may be electrically connected to the drain electrode of the second-first transistor, and a drain electrode thereof may be electrically connected to the fifth node N5.

[0249] The third transistor T3 may be turned on by the second gate signal GC of the second gate line GCL so that the third node N3 is electrically connected to the second node N2. For example, the gate electrode of the third transistor T3 may be electrically connected to the second gate line GCL, its source electrode may be electrically connected to the third node N3, and its drain electrode may be electrically connected to the second node N2. The source electrode of the third transistor T3, the second electrode of the first capacitor Cst, and the gate electrode of the first transistor T1 may be connected to the third node N3. The drain electrode of the third transistor T3, the drain electrode of the first transistor T1, and the source electrode of the sixth transistor T6 may be connected to the second node N2. The third transistor T3 may be turned on by the second gate signal GC of the second gate line GCL so that the second node N2 is electrically connected to the third node N3. At the same time, the third transistor T3 may be configured as a dual-gate transistor. For example, the third transistor T3 may include a third-first transistor and a third-second transistor connected in series between the third node N3 and the second node N2. The gate electrode of the third-first transistor may be electrically connected to the second gate line GCL, its source electrode may be electrically connected to the third node N3, and its drain electrode may be electrically connected to the source electrode of the third-second transistor. A gate electrode of the third-second transistor may be electrically connected to the second gate line GCL, a source electrode thereof may be electrically connected to the drain electrode of the third-first transistor, and a drain electrode thereof may be electrically connected to the second node N2.

[0250] The fourth transistor T4 may be turned on by the third gate signal GI of the third gate line GIL so that the third node N3 is electrically connected to the first initialization voltage line VIL1. The fourth transistor T4 may be connected in series between the third node N3 and the first initialization voltage line VIL1. For example, the gate electrode of the fourth transistor T4 may be electrically connected to the third gate line GIL, its source electrode may be electrically connected to the third node N3, and its drain electrode may be electrically connected to the first initialization voltage line VIL1. At the same time, the fourth transistor T4 may be configured as a dual-gate transistor. For example, the fourth transistor T4 may include a fourth-first transistor and a fourth-second transistor connected in series. The gate electrode of the fourth-first transistor may be electrically connected to the third gate line GIL, its drain electrode may be electrically connected to the first initialization voltage line VIL1, and its source electrode may be connected to the drain electrode of the fourth-second transistor. The gate electrode of the fourth-second transistor may be electrically connected to the third gate line GIL, its drain electrode may be electrically connected to the source electrode of the fourth-first transistor, and its source electrode may be electrically connected to the third node N3.

[0251] The fifth transistor T5 may be turned on by the second gate signal GC of the second gate line GCL so that the reference voltage line VRL is electrically connected to the fifth node N5. For example, the gate electrode of the fifth transistor T5 may be electrically connected to the second gate line GCL, its source electrode may be electrically connected to the fifth node N5, and its drain electrode may be electrically connected to the reference voltage line VRL. The fifth transistor T5 may be turned on by the second gate signal GC of the second gate line GCL so that the reference voltage line VRL is electrically connected to the fifth node N5. At the same time, the fifth transistor T5 may be configured as a dual-gate transistor. For example, the fifth transistor T5 may include a fifth-first transistor and a fifth-second transistor connected in series. The gate electrode of the fifth-first transistor may be electrically connected to the second gate line GCL, its source electrode may be connected to the fifth node N5, and its drain electrode may be electrically connected to the source electrode of the fifth-second transistor. The gate electrode of the fifth-second transistor may be electrically connected to the second gate line GCL, its source electrode may be electrically connected to the drain electrode of the fifth-first transistor, and its drain electrode may be electrically connected to the reference voltage line VRL. The drain electrode of the fifth transistor T5 may receive the reference voltage VRF.

[0252] The sixth transistor T6 may be turned on by the second emission control signal EM2 of the second emission control line EML2 to electrically connect the second node N2 to the fourth node N4 as the first electrode of the light emitting element LEL. A gate electrode of the sixth transistor T6 may be electrically connected to the emission control line EML, a source electrode thereof may be electrically connected to the second node N2, and a drain electrode thereof may be electrically connected to the fourth node N4.

[0253] The seventh transistor T7 may be turned on by the fourth gate signal EB of the fourth gate line EBL so that the fourth node N4 as the first electrode of the light emitting element LEL is electrically connected to the second initialization voltage line VIL2. By turning on the seventh transistor T7 in response to the fourth gate signal, the first electrode of the light emitting element LEL may be discharged to the second initialization voltage VIT2. The gate electrode of the seventh transistor T7 may be electrically connected to the fourth gate line EBL, the source electrode thereof may be electrically connected to the fourth node N4, and the drain electrode thereof may be electrically connected to the second initialization voltage line VIL2. The second initialization voltage line VIL2 may transmit the second initialization voltage VI2 to the fourth node N4 connected to the anode of the light emitting element LEL.

[0254] The eighth transistor T8 may be turned on by the fourth gate signal EB of the fourth gate line EBL so that the bias voltage line VBL is electrically connected to the first node N1. The eighth transistor T8 may be turned on according to the fourth gate signal EB to supply the bias voltage VB to the first node N1. The eighth transistor T8 may improve the hysteresis of the first transistor T1 by supplying the bias voltage VB to the source electrode of the first transistor T1 connected to the first node N1. The gate electrode of the eighth transistor T8 may be electrically connected to the fourth gate line EBL, the source electrode thereof may be electrically connected to the bias voltage line VBL, and the drain electrode thereof may be electrically connected to the first node N1.

[0255] The ninth transistor T9 may be turned on by the first emission control signal EM1 of the first emission control line EML1 to electrically connect the driving voltage line VDL to the first node N1. The gate electrode of the ninth transistor T9 may be electrically connected to the first emission control line EML1, the source electrode thereof may be electrically connected to the driving voltage line VDL, and the drain electrode thereof may be electrically connected to the first node N1. The drain electrode of the eighth transistor T8, the source electrode of the first transistor T1, and the drain electrode of the ninth transistor T9 may be connected to the first node N1.

[0256] When the ninth transistor T9 , the first transistor T1 , and the sixth transistor T6 are all turned on, a driving current may be supplied to the light emitting element LEL.

[0257] Each of the first transistor T1 to the ninth transistor T9 may include a silicon-based active layer. For example, each of the first transistor T1 to the ninth transistor T9 may be a p-type transistor including an active layer made of low temperature polysilicon (LTPS). The active layer made of low temperature polysilicon may have high electron mobility and excellent conduction characteristics. Therefore, in the display device 10, since a transistor having excellent conduction characteristics is included, a plurality of pixels PX can be driven stably and efficiently. Each of the first transistor T1 to the ninth transistor T9 may output a current flowing into the source electrode to the drain electrode in response to a gate low voltage applied to the gate electrode of the corresponding transistor.

[0258] Alternatively, some of the first transistor T1 to the ninth transistor T9 may be p-type transistors including an active layer made of the above-mentioned low temperature polycrystalline silicon (LTPS), and other transistors of the first transistor T1 to the ninth transistor T9 may be n-type transistors including an oxide-based active layer. The transistor including the oxide-based active layer may have a coplanar structure on which the gate electrode is disposed. The transistor including the oxide-based active layer may output a current flowing from the drain electrode to the source electrode in response to a gate high voltage applied to the gate electrode.

[0259] The first capacitor Cst may be electrically connected between the fifth node N5 and the third node N3. For example, a first electrode of the first capacitor Cst may be electrically connected to the fifth node N5, and a second electrode of the first capacitor Cst may be electrically connected to the third node N3. The first capacitor Cst may maintain a data voltage supplied from the data line DL through the second transistor T2 for one frame period.

[0260] The second capacitor Chold may be electrically connected between the driving voltage line VDL and the fifth node N5. For example, a first electrode of the second capacitor Chold may be electrically connected to the fifth node N5, and a second electrode of the second capacitor Chold may be electrically connected to the driving voltage line VDL. The second capacitor Chold may maintain a potential difference between the driving voltage line VDL and the gate electrode of the first transistor T1.

[0261] Fig. 20 is a plan view of a unit pixel array according to an embodiment. Fig.21 is selectively shown only Fig. 20 A plan view of a first pattern layer and a second pattern layer of an assembly. Fig. 22 is selectively shown only Fig. 20 A plan view of the third patterned layer of the assembly. Fig.23 is selectively shown only Fig. 20 A plan view of the first to fourth pattern layers of a component. Fig.24 is selectively shown only Fig. 20 A plan view of the fifth patterned layer of the assembly. Fig.25 is selectively shown only Fig. 20 A plan view of the sixth pattern layer of the assembly. Fig.26 is selectively shown only Fig. 20 A plan view of the first to fifth pattern layers of a component. Fig. 27 is selectively shown only Fig. 20 A plan view of the fifth pattern layer and the sixth pattern layer of the component. Fig.28 is selectively shown only Fig. 20 A plan view of the sixth pattern layer and the seventh pattern layer of the component.

[0262] At the same time, if Fig. 20As shown in , the contact holes can be classified into first type contact holes CTa, second type contact holes CTb and third type contact holes CTc. The first type contact hole CTa can be a contact hole for connecting the fifth pattern layer to the pattern layer disposed thereunder (e.g., at least one of the second pattern layer to the fourth pattern layer). The second type contact hole CTb can be a contact hole for connecting the sixth pattern layer to the pattern layer disposed thereunder (e.g., the fifth pattern layer). The third type contact hole CTc can be a contact hole for connecting the seventh pattern layer to the pattern layer disposed thereunder (e.g., the sixth pattern layer).

[0263] The first pattern layer can be disposed on the substrate SUB along the third direction DR3. Fig. 20 and Fig.21 In the example shown in , the first pattern layer may include a first active layer ACT1 and a second active layer ACT2.

[0264] The first active layer ACT1 may provide channel regions CH1, CH3, CH4, CH6, CH7, CH8 and CH9 of the first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9, the first electrodes E11, E31, E411, E421, E61, E71, E81 and E91 and the second electrodes E12, E32, E412, E422, E62, E72, E82 and E92.

[0265] The second active layer ACT2 may provide channel regions CH2 and CH5 of the second and fifth transistors T2 and T5 , first electrodes E211 , E221 , E511 , and E521 , and second electrodes E212 , E222 , E512 , and E522 .

[0266] Here, the first electrode of each of the first to ninth transistors T1 to T9 may be one of the source electrode and the drain electrode, and the second electrode of each of the first to ninth transistors T1 to T9 may be the other of the source electrode and the drain electrode.

[0267] Each of the first and second active layers ACT1 and ACT2 may be a semiconductor layer made of low temperature polycrystalline silicon (LTPS).

[0268] The second pattern layer may be arranged on the first pattern layer along the third direction DR3. The insulating layer may be arranged between the first pattern layer and the second pattern layer. Fig. 20 and Fig.21In the example shown in, the second pattern layer may include a first gate electrode GE1, a second-first gate electrode GE2-1, a second-second gate electrode GE2-2, a third-first gate electrode GE3-1, a third-second gate electrode GE3-2, a fourth-first gate electrode GE4-1, a fourth-second gate electrode GE4-2, a fifth-first gate electrode GE5-1, a fifth-second gate electrode GE5-2, a sixth gate electrode GE6, a seventh gate electrode GE7, an eighth gate electrode GE8, a ninth gate electrode GE9 and a lower capacitor electrode CPEa.

[0269] The first gate electrode GE1, the third-first gate electrode GE3-1, the third-second gate electrode GE3-2, the fourth-first gate electrode GE4-1, the fourth-second gate electrode GE4-2, the sixth gate electrode GE6, the seventh gate electrode GE7, the eighth gate electrode GE8, and the ninth gate electrode GE9 may overlap the first active layer ACT1. Channel regions CH1, CH3-1, CH3-2, CH4-1, CH4-2, CH6, CH7, CH8 and CH9 of the first transistor T1, the third-first transistor T3-1, the third-second transistor T3-2, the fourth-first transistor T4-1, the fourth-second transistor T4-2, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 can be respectively formed in the overlapping area between the first active layer ACT1 and the first gate electrode GE1, the third-first gate electrode GE3-1, the third-second gate electrode GE3-2, the fourth-first gate electrode GE4-1, the fourth-second gate electrode GE4-2, the sixth gate electrode GE6, the seventh gate electrode GE7, the eighth gate electrode GE8 and the ninth gate electrode GE9.

[0270] The second-first gate electrode GE2-1, the second-second gate electrode GE2-2, the fifth-first gate electrode GE5-1, and the fifth-second gate electrode GE5-2 may overlap the second active layer ACT2. Channel regions CH2-1, CH2-2, CH5-1, and CH5-2 of the second-first transistor T2-1, the second-second transistor T2-2, the fifth-first transistor T5-1, and the fifth-second transistor T5-2 may be formed in the overlapping region between the second active layer ACT2 and the second-first gate electrode GE2-1, the second-second gate electrode GE2-2, the fifth-first gate electrode GE5-1, and the fifth-second gate electrode GE5-2, respectively.

[0271] The first transistor T1 may include a first gate electrode GE1, a first electrode E11, a second electrode E12, and a first channel region CH1.

[0272] The second transistor T2 may be formed as a dual-gate transistor including a second-first transistor T2-1 and a second-second transistor T2-2. The second-first transistor T2-1 may include a second-first gate electrode GE2-1, a first electrode E211, a second electrode E212, and a second-first channel region CH2-1. The second-second transistor T2-2 may include a second-second gate electrode GE2-2, a first electrode E221, a second electrode E222, and a second-second channel region CH2-2. Here, the second-first gate electrode GE2-1 and the second-second gate electrode GE2-2 may be formed integrally.

[0273] The third transistor T3 may include a third gate electrode GE3, a first electrode E31, a second electrode E32, and a third channel region CH3. The third transistor T3 may be formed as a dual-gate transistor including a third-first transistor T3-1 and a third-second transistor T3-2. The third-first transistor T3-1 may include a third-first gate electrode GE3-1, a first electrode E311, a second electrode E312, and a third-first channel region CH3-1. The third-second transistor T3-2 may include a third-second gate electrode GE3-2, a first electrode E321, a second electrode E322, and a third-second channel region CH3-2. Here, the third-first gate electrode GE3-1 and the third-second gate electrode GE3-2 may be formed integrally.

[0274] The fourth transistor T4 may be formed as a dual-gate transistor including a fourth-first transistor T4-1 and a fourth-second transistor T4-2. The fourth-first transistor T4-1 may include a fourth-first gate electrode GE4-1, a first electrode E411, a second electrode E412, and a fourth-first channel region CH4-1. The fourth-second transistor T4-2 may include a fourth-second gate electrode GE4-2, a first electrode E421, a second electrode E422, and a fourth-second channel region CH4-2. Here, the fourth-first gate electrode GE4-1 and the fourth-second gate electrode GE4-2 may be integrally formed.

[0275] The fifth transistor T5 may be formed as a dual-gate transistor including a fifth-first transistor T5-1 and a fifth-second transistor T5-2. The fifth-first transistor T5-1 may include a fifth-first gate electrode GE5-1, a first electrode E511, a second electrode E512, and a fifth-first channel region CH5-1. The fifth-second transistor T5-2 may include a fifth-second gate electrode GE5-2, a first electrode E521, a second electrode E522, and a fifth-second channel region CH5-2.

[0276] The sixth transistor T6 may include a sixth gate electrode GE6 , a first electrode E61 , a second electrode E62 , and a sixth channel region CH6 .

[0277] The seventh transistor T7 may include a seventh gate electrode GE7 , a first electrode E71 , a second electrode E72 , and a seventh channel region CH7 .

[0278] The eighth transistor T8 may include an eighth gate electrode GE8, a first electrode E81, a second electrode E82, and an eighth channel region CH8. Here, the eighth gate electrode GE8 and the seventh gate electrode GE7 may be integrally formed.

[0279] The ninth transistor T9 may include a ninth gate electrode GE9, a first electrode E91, a second electrode E92, and a ninth channel region CH9.

[0280] The third pattern layer may be arranged on the second pattern layer along the third direction DR3. The insulating layer may be arranged between the second pattern layer and the third pattern layer. Fig. 20 , Fig. 22 and Fig.23 In the example shown in , the third pattern layer may include a first parasitic capacitor electrode PCPE1, a second parasitic capacitor electrode PCPE2, a third parasitic capacitor electrode PCPE3, a lower driving voltage line VDLa, and an upper capacitor electrode CPEb.

[0281] The first parasitic capacitor electrode PCPE1 is as shown in Fig. 20 and Fig.23 In the example shown in , the first parasitic capacitor electrode PCPE1 may be overlapped with the active layer ACT. For example, the first parasitic capacitor electrode PCPE1 may be overlapped with the second active layer ACT2 corresponding to the connection portion between the second-first transistor T2-1 and the second-second transistor T2-2. Here, the second-first transistor T2-1 and the second-second transistor T2-2 are sub-transistors of the second transistor T2 as a dual-gate transistor.

[0282] The second parasitic capacitor electrode PCPE2 may overlap the second active layer ACT2 corresponding to the connection portion between the fifth-first transistor T5-1 and the fifth-second transistor T5-2. Here, the fifth-first transistor T5-1 and the fifth-second transistor T5-2 are sub-transistors of the fifth transistor T5 as a double-gate transistor.

[0283] The third parasitic capacitor electrode PCPE3 may be overlapped with the first active layer ACT1 corresponding to the connection portion between the third-first transistor T3-1 and the fourth-first transistor T4-1. In addition, the third parasitic capacitor electrode PCPE3 may be overlapped with the first active layer ACT1 corresponding to the connection portion between the third-first transistor T3-1 and the third-second transistor T3-2. Here, the third-first transistor T3-1 and the third-second transistor T3-2 are sub-transistors of the third transistor T3 as a dual-gate transistor. In addition, the third parasitic capacitor electrode PCPE3 may be overlapped with the first active layer ACT1 corresponding to the connection portion between the fourth-first transistor T4-1 and the fourth-second transistor T4-2. Here, the fourth-first transistor T4-1 and the fourth-second transistor T4-2 are sub-transistors of the fourth transistor T4 as a dual-gate transistor.

[0284] The lower driving voltage line VDLa may overlap the lower capacitor electrode CPEa. The second capacitor Chold may be formed in a region where the lower driving voltage line VDLa overlaps the lower capacitor electrode CPEa. For example, the lower capacitor electrode CPEa and the lower driving voltage line VDLa may correspond to a first electrode and a second electrode of the second capacitor Chold, respectively. In addition, the lower driving voltage line VDLa may have a hole 50 passing through it in the third direction DR3.

[0285] The upper capacitor electrode CPEb may overlap with the first gate electrode GE1. The first capacitor Cst may be formed in a region where the upper capacitor electrode CPEb overlaps with the first gate electrode GE1. For example, the upper capacitor electrode CPEb and the first gate electrode GE1 may correspond to the first electrode and the second electrode of the first capacitor Cst, respectively. In addition, the upper capacitor electrode CPEb may have a hole 40 passing through it in the third direction DR3. In addition, the area of ​​the upper capacitor electrode CPEb may be greater than the area of ​​the first gate electrode GE1. In this case, the area of ​​the upper capacitor electrode CPEb may mean, for example, an area including the area (or size) of the hole 40.

[0286] The fourth pattern layer may be arranged on the third pattern layer along the third direction DR3. The insulating layer may be arranged between the third pattern layer and the fourth pattern layer. Fig. 20 and Fig.23 In the example shown in , the fourth pattern layer may include a repair line RPL.

[0287] like Fig. 20As shown in , the repair line RPL may overlap with the extension EX of the lower pixel connection electrode PCEa to be described later. For example, the repair line RPL may include a repair short circuit portion RSP, which is a portion of the repair line RPL protruding in the second direction DR2 and overlapping the lower pixel connection electrode PCEa. For example, the repair line RPL may be used to repair a defective pixel. For the description of the repair line RPL, reference may be made to the above Figure 6 Description of the repair line RPL.

[0288] According to the present disclosure, the repair line RPL can be formed by the fourth pattern layer. In other words, according to the present disclosure, the repair line RPL can be formed in a pattern layer (for example, the fourth pattern layer) other than the second pattern layer and the third pattern layer for forming the first capacitor Cst. In this case, since the repair line RPL included in the fourth pattern layer and the sixth gate electrode GE6 and the fourth-second gate electrode GE4-2 included in the third pattern layer are arranged in different layers, the minimum distance between the repair short circuit portion RSP of the repair line RPL and the sixth gate electrode GE6 and the fourth-second gate electrode GE4-2 in the plan view in the second direction can be further reduced. Similarly, since the repair line RPL included in the fourth pattern layer and the seventh gate electrode GE7 and the eighth gate electrode GE8 included in the third pattern layer are arranged in different layers, the distance between the repair short circuit portion RSP of the repair line RPL and the seventh gate electrode GE7 and the eighth gate electrode GE8 in the plan view in the second direction can be further reduced. In addition, the insulating layer (for example, the repair line RPL) provided between the fourth pattern layer (for example, the repair line RPL) and the second pattern layer (the sixth gate electrode GE6 and the fourth-second gate electrode GE4-2) is provided. Fig.29 The thickness of the first interlayer insulating layer ITL1 and the second interlayer insulating layer ITL2 (eg, ) is thick, so that the minimum distance can be further reduced without being affected by the laser during the repair process. As a result, the pixel size can be reduced, which can increase the resolution.

[0289] The fifth pattern layer may be disposed on the fourth pattern layer along the third direction DR3. The insulating layer may be disposed between the fourth pattern layer and the fifth pattern layer. Fig. 20 , Fig.24 and Fig.26 In the example shown in, the fifth pattern layer may include a second gate line GCL, a first gate line GWL, a lower reference voltage line VRLa, a data connection electrode DCE, a capacitor connection electrode CCE, a drive connection electrode VCE, a gate connection electrode GCE, a first emission control line EML1, a third gate line GIL, a second emission control line EML2, a lower pixel connection electrode PCEa, a first initialization voltage line VIL1, a fourth gate line EBL, a bias voltage line VBL and a second initialization voltage line VIL2.

[0290] The second gate line GCL may be Fig.26 The gate electrodes GE5-1, GE5-2, GE3-1 and GE3-2 are connected to the fifth-first gate electrode GE5-1, the fifth-second gate electrode GE5-2, the third-first gate electrode GE3-1 and the third-second gate electrode GE3-2 through the first type contact hole CTa of the insulating layer as shown in FIG.

[0291] The first gate line GWL may be Fig.26 The gate electrodes GE2 - 1 and GE2 - 2 are connected to each other through the first type contact hole CTa of the insulating layer as shown in FIG.

[0292] The lower reference voltage line VRLa can be Fig.26 The transistor 500 is connected to the second electrode E522 of the second active layer ACT2 (eg, the second electrode E522 of the fifth-second transistor T5-2) through the first type contact hole CTa of the insulating layer as shown in FIG.

[0293] The data connection electrode DCE can be Fig.26 The first electrode E211 of the second active layer ACT2 (eg, the first electrode E211 of the second-first transistor T2 - 1 ) is connected to the first electrode E211 of the second active layer ACT2 through the first type contact hole CTa of the insulating layer as shown in FIG.

[0294] The capacitor connection electrode CCE can be Fig.26 As shown in FIG. 1 , the capacitor connection electrode CCE is connected to the second electrode E222 and the first electrode E511 of the second active layer ACT2 (for example, the second electrode E212 of the second-second transistor T2-2 and the first electrode E511 of the fifth-first transistor T5-1) through the first type contact hole CTa of the insulating layer. In addition, the capacitor connection electrode CCE can be connected to the lower capacitor electrode CPEa through the first type contact hole CTa of the insulating layer and the hole 50 of the lower driving voltage line VDLa. In addition, the capacitor connection electrode CCE can be connected to the upper capacitor electrode CPEb through the first type contact hole CTa of the insulating layer.

[0295] The driving connection electrode VCE can be Fig.26 As shown in FIG. 1 , the driving connection electrode VCE may be connected to the lower driving voltage line VDLa through the first type contact hole CTa of the insulating layer. In addition, the driving connection electrode VCE may be connected to the first electrode E91 of the first active layer ACT1 (e.g., the first electrode E91 of the ninth transistor T9) through the first type contact hole CTa of the insulating layer. In addition, the driving connection electrode VCE may be connected to the third parasitic capacitor electrode PCPE3 through the first type contact hole CTa of the insulating layer.

[0296] The gate connection electrode GCE may be Fig.26As shown in FIG. 1 , the gate connection electrode GCE is connected to the first electrode E311 of the first active layer ACT1 (e.g., the first electrode E311 of the third-first transistor T3-1) through the first type contact hole CTa of the insulating layer. In addition, the gate connection electrode GCE can be connected to the first gate electrode GE1 through the first type contact hole CTa of the insulating layer and the hole 40 of the upper capacitor electrode CPEb.

[0297] The first emission control line EML1 may be Fig.26 As shown in FIG. 8 , the gate electrode GE9 is connected to the ninth gate electrode GE9 through the first type contact hole CTa of the insulating layer.

[0298] The third gate line GIL can be Fig.26 The fourth-first gate electrode GE4-1 and the fourth-second gate electrode GE4-2 are connected to each other through the first type contact hole CTa of the insulating layer as shown in FIG.

[0299] The second emission control line EML2 may be Fig.26 As shown in FIG. 8 , the gate electrode GE6 is connected to the sixth gate electrode GE6 through the first type contact hole CTa of the insulating layer.

[0300] The lower pixel connection electrode PCEa can be Fig.26 As shown in FIG. 8 , the transistor 1 is connected to the second electrode E62 of the first active layer ACT1 (eg, the second electrode E62 of the sixth transistor T6 ) through the first type contact hole CTa of the insulating layer.

[0301] The first initialization voltage line VIL1 can be Fig.26 As shown in FIG. 4 , the transistor 40 is connected to the second electrode E422 of the first active layer ACT1 (eg, the second electrode E422 of the fourth-second transistor T4 - 2 ) through the first type contact hole CTa of the insulating layer.

[0302] The fourth gate line EBL may be Fig.26 The gate electrodes GE7 and GE8 are connected to the seventh gate electrode GE7 and the eighth gate electrode GE8 through the first type contact hole CTa of the insulating layer as shown in FIG.

[0303] The bias voltage line VBL can transmit the bias voltage VB. Fig.26 As shown in , the bias voltage line VBL may be connected to the first electrode E81 of the first active layer ACT1 (eg, the first electrode E81 of the eighth transistor T8 ) through the first type contact hole CTa of the insulating layer.

[0304] The second initialization voltage line VIL2 can be Fig.26 The first parasitic capacitor electrode PCPE1 and the second parasitic capacitor electrode PCPE2 are connected to the second electrode E72 of the first active layer ACT1 (eg, the second electrode E72 of the seventh transistor T7) through the first type contact hole CTa of the insulating layer as shown in FIG.

[0305] The sixth pattern layer may be disposed on the fifth pattern layer along the third direction DR3. The insulating layer may be disposed between the fifth pattern layer and the sixth pattern layer. Fig. 20 , Fig.25 and Fig. 27 In the example shown in , the sixth pattern layer may include the data line DL, the upper driving voltage line VDLb, the upper pixel connection electrode PCEb, and the upper reference voltage line VRLb.

[0306] like Fig. 27 As shown in FIG. 1 , the data line DL may be connected to the data link electrode DCE through the second type contact hole CTb of the insulating layer.

[0307] like Fig. 27 As shown in , the upper driving voltage line VDLb may be connected to the driving connection electrode VCE through the second type contact hole CTb of the insulating layer.

[0308] like Fig. 27 As shown in FIG. 1 , the upper pixel connection electrode PCEb may be connected to the lower pixel connection electrode PCEa through the second type contact hole CTb of the insulating layer.

[0309] like Fig. 27 As shown in , the upper reference voltage line VRLb may be connected to the lower reference voltage line VRLa through the second type contact hole CTb of the insulating layer.

[0310] The seventh pattern layer may be disposed on the sixth pattern layer along the third direction DR3. The insulating layer may be disposed between the sixth pattern layer and the seventh pattern layer. Fig. 20 and Fig. 27 In the example shown in , the seventh pattern layer may include a pixel electrode PE.

[0311] A portion of the pixel electrode PE may be exposed by a bank to be described later. For example, the bank may have an opening (hereinafter, an emission region) exposing a portion of the pixel electrode PE. A light emitting layer may be provided on the pixel electrode PE corresponding to the emission region.

[0312] The pixel electrode PE may be connected to the upper pixel connection electrode PCEb through the third type contact hole CTc of the insulating layer.

[0313] Fig.29 It is along Fig. 20 A cross-sectional view taken along line III-III'.

[0314] like Fig.29As shown in FIG, the display device 10 may include a substrate SUB, a barrier layer BR, a thin film transistor layer TFTL, a light emitting element layer EMTL, and an encapsulation layer ENC. The barrier layer BR, the thin film transistor layer TFTL, the light emitting element layer EMTL, and the encapsulation layer ENC may be sequentially disposed on the substrate SUB along a third direction DR3.

[0315] Fig.29 The substrate SUB can be connected with the above Fig.17 and Fig.18 The same as the substrate SUB.

[0316] like Fig.29 As shown in FIG. 8 , the barrier layer BR may be disposed on the substrate SUB. Fig.29 The barrier layer BR may have Fig.17 and Fig.18 The barrier layer BR has the same material and structure.

[0317] like Fig.29 As shown in FIG. 8 , the buffer layer BF may be disposed on the barrier layer BR. Fig.29 The buffer layer BF may have Fig.17 and Fig.18 The buffer layer BF has the same material and structure.

[0318] The first pattern layer may be disposed on the buffer layer BF. For example, the first active layer ACT1 and the second active layer ACT2 may be disposed on the buffer layer BF. Fig.29 An example is shown in which the first active layer ACT1 is disposed on the buffer layer BF. The first active layer ACT1 may include a fourth-second channel region CH4-2 of the fourth-second transistor T4-2, a second electrode E422 of the fourth-second transistor T4-2, a second electrode E62 of the sixth transistor T6, a sixth channel region CH6 of the sixth transistor T6, a first electrode E61 of the sixth transistor T6, and a second electrode E12 of the first transistor T1.

[0319] The first pattern layer may have Fig.17 and Fig.18 The same material and structure as the first patterned layer.

[0320] The gate insulating layer GTI may be disposed on the first pattern layer. Fig.29 As shown in , the gate insulating layer GTI may be disposed on the first active layer ACT1. In this case, the gate insulating layer GTI may be disposed on the entire surface of the substrate SUB including the first active layer ACT1.

[0321] Fig.29 The gate insulating layer GTI may have Fig.17 and Fig.18The gate insulating layer GTI has the same material and structure.

[0322] The second pattern layer may be disposed on the gate insulating layer GTI. For example, the first gate electrode GE1, the second-first gate electrode GE2-1, the second-second gate electrode GE2-2, the third-first gate electrode GE3-1, the third-second gate electrode GE3-2, the fourth-first gate electrode GE4-1, the fourth-second gate electrode GE4-2, the fifth-first gate electrode GE5-1, the fifth-second gate electrode GE5-2, the sixth gate electrode GE6, the seventh gate electrode GE7, the eighth gate electrode GE8, the ninth gate electrode GE9 and the lower capacitor electrode CPEa may be disposed on the gate insulating layer GTI.

[0323] Fig.29 An example is shown in which the fourth-second gate electrode GE4 - 2 , the sixth gate electrode GE6 , and the first gate electrode GE1 are disposed on the gate insulating layer GTI.

[0324] The fourth-second gate electrode GE4-2 may be disposed on the gate insulating layer GTI to overlap the fourth-second channel region CH4-2 of the first active layer ACT1. The sixth gate electrode GE6 may be disposed on the gate insulating layer GTI to overlap the sixth channel region CH6 of the first active layer ACT1. The first gate electrode GE1 may be disposed on the gate insulating layer GTI to overlap the first channel region CH1 of the first active layer ACT1.

[0325] Fig.29 The second pattern layer may have Fig.17 and Fig.18 The second pattern layer has the same material and structure as above.

[0326] The first interlayer insulating layer ITL1 may be disposed on the second pattern layer. Fig.29 As shown in FIG, the first interlayer insulating layer ITL1 may be disposed on the fourth-second gate electrode GE4-2, the sixth gate electrode GE6 and the first gate electrode GE1. In this case, the first interlayer insulating layer ITL1 may be disposed on the entire surface of the substrate SUB including the fourth-second gate electrode GE4-2, the sixth gate electrode GE6 and the first gate electrode GE1.

[0327] Fig.29 The first interlayer insulating layer ITL1 may have Fig.17 and Fig.18 The first interlayer insulating layer ITL1 has the same material and structure.

[0328] The third pattern layer may be disposed on the first interlayer insulating layer ITL1. For example, the first parasitic capacitor electrode PCPE1, the second parasitic capacitor electrode PCPE2, the third parasitic capacitor electrode PCPE3, the lower driving voltage line VDLa, and the upper capacitor electrode CPEb may be disposed on the first interlayer insulating layer ITL1. Fig.29 An example is shown in which the upper capacitor electrode CPEb is disposed on the first interlayer insulating layer ITL1. The upper capacitor electrode CPEb may be disposed on the first interlayer insulating layer ITL1 to overlap the first gate electrode GE1. The first capacitor Cst may be formed by the upper capacitor electrode CPEb and the first gate electrode GE1.

[0329] Fig.29 The third pattern layer may have Fig.17 and Fig.18 The third pattern layer has the same material and structure.

[0330] The second interlayer insulating layer ITL2 may be disposed on the third pattern layer. Fig.29 As shown in FIG. 1 , the second interlayer insulating layer ITL2 may be disposed on the upper capacitor electrode CPEb. In this case, the second interlayer insulating layer ITL2 may be disposed on the entire surface of the substrate SUB including the upper capacitor electrode CPEb.

[0331] Fig.29 The second interlayer insulating layer ITL2 may have Fig.17 and Fig.18 The second interlayer insulating layer ITL2 has the same material and structure.

[0332] The fourth pattern layer may be disposed on the second interlayer insulating layer ITL2. For example, the repair line RPL may be disposed on the second interlayer insulating layer ITL2.

[0333] Fig.29 The fourth pattern layer may have Fig.17 and Fig.18 The fourth pattern layer has the same material and structure.

[0334] The third interlayer insulating layer ITL3 may be disposed on the fourth pattern layer. Fig.29 As shown in FIG, a third interlayer insulating layer ITL3 may be disposed on the repair line RPL. The third interlayer insulating layer ITL3 may be disposed on the entire surface of the substrate SUB including the repair line RPL.

[0335] Fig.29 The third interlayer insulating layer ITL3 may have Fig.17 and Fig.18 The third interlayer insulating layer ITL3 has the same material and structure.

[0336] The fifth pattern layer may be disposed on the third interlayer insulating layer ITL3. For example, the second gate line GCL, the first gate line GWL, the lower reference voltage line VRLa, the data connection electrode DCE, the capacitor connection electrode CCE, the drive connection electrode VCE, the gate connection electrode GCE, the first emission control line EML1, the third gate line GIL, the second emission control line EML2, the lower pixel connection electrode PCEa, the first initialization voltage line VIL1, the fourth gate line EBL, the bias voltage line VBL, and the second initialization voltage line VIL2 may be disposed on the third interlayer insulating layer ITL3. Fig.29 An example is shown in which the second emission control line EML2 , the lower pixel link electrode PCEa, the third gate line GIL, the second gate line GCL, and the first emission control line EML1 are disposed on the third interlayer insulating layer ITL3 .

[0337] The lower pixel connection electrode PCEa may be connected to the second electrode E62 of the sixth transistor T6 through a first contact hole CT1 penetrating the third interlayer insulating layer ITL3 , the second interlayer insulating layer ITL2 , the first interlayer insulating layer ITL1 , and the gate insulating layer GTI.

[0338] The first contact hole CT1 may belong to the first type contact hole CTa.

[0339] Fig.29 The fifth pattern layer may have Fig.17 and Fig.18 The fifth pattern layer has the same material and structure.

[0340] The first planarization layer VA1 may be disposed on the fifth pattern layer. For example, the first planarization layer VA1 may be disposed on the second emission control line EML2, the lower pixel connection electrode PCEa, the third gate line GIL, the second gate line GCL, and the first emission control line EML1. The first planarization layer VA1 may be disposed on the entire surface of the substrate SUB including the second emission control line EML2, the lower pixel connection electrode PCEa, the third gate line GIL, the second gate line GCL, and the first emission control line EML1.

[0341] Fig.29 The first planarization layer VA1 may have Fig.17 and Fig.18 The first planarization layer VA1 has the same material and structure as the first planarization layer VA1.

[0342] The sixth pattern layer may be disposed on the first planarization layer VA1. Fig.29 As shown in FIG. 1 , the upper driving voltage line VDLb, the upper pixel connection electrode PCEb, and the upper reference voltage line VRLb may be disposed on the first planarization layer VA1 .

[0343] The upper pixel connection electrode PCEb may be connected to the lower pixel connection electrode PCEa through a second contact hole CT2 penetrating the first planarization layer VA1 .

[0344] The second contact hole CT2 may belong to the second type contact hole CTb.

[0345] Fig.29 The sixth pattern layer may have Fig.17 and Fig.18 The sixth pattern layer has the same material and structure.

[0346] The second planarization layer VA2 may be disposed on the sixth pattern layer. For example, the second planarization layer VA2 may be disposed on the upper driving voltage line VDLb, the upper pixel connection electrode PCEb, and the upper reference voltage line VRLb. The second planarization layer VA2 may be disposed on the entire surface of the substrate SUB including the upper driving voltage line VDLb, the upper pixel connection electrode PCEb, and the upper reference voltage line VRLb.

[0347] Fig.29 The second planarization layer VA2 may have Fig.17 and Fig.18 The second planarization layer VA2 has the same material and structure.

[0348] The seventh pattern layer may be disposed on the second planarization layer VA2. Fig.29 As shown in FIG. 1 , the light emitting element layer EMTL including the seventh pattern layer may be disposed on the second planarization layer VA2 . For example, the pixel electrode PE as the seventh pattern layer may be disposed on the second planarization layer VA2 .

[0349] The pixel electrode PE may be connected to the upper pixel connection electrode PCEb through a third contact hole CT3 penetrating the second planarization layer VA2 .

[0350] The third contact hole CT3 may belong to the third type contact hole CTc.

[0351] In addition to the seventh pattern layer, the light emitting element layer EMTL may further include a light emitting element LEL and a bank PDL (or a pixel defining layer).

[0352] The light emitting element LEL may include a pixel electrode PE, a light emitting layer EL, and a common electrode CM. An emission region EA in which the pixel electrode PE, the light emitting layer EL, and the common electrode CM are sequentially stacked indicates a region in which holes from the pixel electrode PE and electrons from the common electrode CM recombine with each other in the light emitting layer EL to emit light. In this case, the pixel electrode PE may be an anode electrode of the light emitting element LEL, and the common electrode CM may be a cathode electrode of the light emitting element LEL.

[0353] because Fig.29 The light emitting element LEL, the spacer SPC and the encapsulation layer ENC are respectively Fig.17 and Fig.18 The light emitting element LEL, the spacer SPC and the encapsulation layer ENC are the same, so Fig.29 The description of the light emitting element LEL, the spacer SPC and the encapsulation layer ENC is as follows Fig.17 and Fig.18 Description.

[0354] At the same time, reference will be made to Figures 30 to 37 Describe the light emitting element LEL (e.g. Fig.17 and Fig.29 Another structure of LEL).

[0355] Fig.30 is a cross-sectional view showing the structure of a light emitting element according to an embodiment, Figure 31 to Figure 34 is a cross-sectional view showing the structure of a light emitting element according to an embodiment.

[0356] Reference Fig.30 According to one embodiment, a light emitting element LEL (eg, an organic light emitting diode) may include a pixel electrode PE, a common electrode CM, and an intermediate layer 203 disposed between the pixel electrode PE and the common electrode CM.

[0357] The pixel electrode PE may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). The pixel electrode 201 may include a reflective layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a compound or mixture thereof. For example, the pixel electrode PE may have a three-layer structure of ITO / Ag / ITO.

[0358] The common electrode CM may be disposed on the intermediate layer 203. The common electrode CM may include a low work function metal, an alloy, a conductive compound, or any combination thereof. For example, the common electrode CM may include lithium (Li), silver (Ag), magnesium (Mg), aluminum (Al), aluminum-lithium (Al-Li), calcium (Ca), magnesium-indium (Mg-In), magnesium-silver (Mg-Ag), ytterbium (Yb), silver-ytterbium (Ag-Yb), ITO, IZO, or any combination thereof. The common electrode CM may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode.

[0359] The intermediate layer 203 may include a high molecular material or a low molecular material that emits light of a predetermined color. In addition to various organic materials, the intermediate layer 203 may also include a metal-containing compound such as an organic metal compound, an inorganic material such as a quantum dot, and the like.

[0360] In an embodiment, the intermediate layer 203 may include a light-emitting layer and a first functional layer and a second functional layer respectively disposed below and above the light-emitting layer. The first functional layer may include, for example, a hole transport layer HTL or may include a hole transport layer and a hole injection layer HIL. The second functional layer is a component disposed on the light-emitting layer and is optional. For example, the intermediate layer 203 may include or may not include a second functional layer. The second functional layer may include an electron transport layer ETL and / or an electron injection layer EIL.

[0361] In an embodiment, the intermediate layer 203 may include two or more light emitting units sequentially stacked between the pixel electrode PE and the common electrode CM and a charge generation layer CGL disposed between the two light emitting units. When the intermediate layer 203 includes the light emitting unit and the charge generation layer, the light emitting element LEL (e.g., an organic light emitting diode) may be a series light emitting element. The light emitting element LEL (e.g., an organic light emitting diode) may improve color purity and light emitting efficiency by having a stacked structure of a plurality of light emitting units.

[0362] One light-emitting unit may include a light-emitting layer and a first functional layer and a second functional layer disposed below and above the light-emitting layer, respectively. The charge generation layer CGL may include a negative charge generation layer and a positive charge generation layer. The light-emitting efficiency of an organic light-emitting diode as a tandem light-emitting element having a plurality of light-emitting layers may be further improved by the negative charge generation layer and the positive charge generation layer.

[0363] The negative charge generation layer may be an n-type charge generation layer. The negative charge generation layer may supply electrons. The negative charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material. The positive charge generation layer may be a p-type charge generation layer. The positive charge generation layer may supply holes. The positive charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material.

[0364] In one embodiment, Fig.31As shown in , the light emitting element LEL (e.g., an organic light emitting diode) may include a first emission unit EU1 including a first light emitting layer EL1 and a second emission unit EU2 including a second light emitting layer EL2, which are sequentially stacked. The charge generation layer CGL may be disposed between the first emission unit EU1 and the second emission unit EU2. For example, the light emitting element LEL (e.g., an organic light emitting diode) may include a pixel electrode PE, a first light emitting layer EL1, a charge generation layer CGL, a second light emitting layer EL2, and a common electrode CM, which are sequentially stacked. The first functional layer and the second functional layer may be disposed on and below the first light emitting layer EL1, respectively. The first functional layer and the second functional layer may be included below and above the second light emitting layer EL2, respectively. The first light emitting layer EL1 may be a blue light emitting layer, and the second light emitting layer EL2 may be a yellow light emitting layer.

[0365] In one embodiment, Fig.32 As shown in , the light emitting element LEL (e.g., an organic light emitting diode) may include a first emission unit EU1 and a third emission unit EU3 and a second emission unit EU2, the first emission unit EU1 and the third emission unit EU3 include a first light emitting layer EL1, and the second emission unit EU2 includes a second light emitting layer EL2. The first charge generation layer CGL1 may be disposed between the first emission unit EU1 and the second emission unit EU2, and the second charge generation layer CGL2 may be disposed between the second emission unit EU2 and the third emission unit EU3. For example, the light emitting element LEL (e.g., an organic light emitting diode) may include a pixel electrode PE, a first light emitting layer EL1, a first charge generation layer CGL1, a second light emitting layer EL2, a second charge generation layer CGL2, a first light emitting layer EL1, and a common electrode CM stacked sequentially. The first functional layer and the second functional layer may be disposed on and below the first light emitting layer EL1, respectively. The first functional layer and the second functional layer may be disposed on and below the second light emitting layer EL2, respectively. The first light emitting layer EL1 may be a blue light emitting layer, and the second light emitting layer EL2 may be a yellow light emitting layer.

[0366] In one embodiment, in the light emitting element LEL (e.g., an organic light emitting diode), in addition to the second light emitting layer EL2, the second emission unit EU2 may further include a third light emitting layer EL3 and / or a fourth light emitting layer EL4 directly contacting the second light emitting layer EL2 below and / or above the second light emitting layer EL2. Here, direct contact may mean that no other layer is provided between the second light emitting layer EL2 and the third light emitting layer EL3 and / or between the second light emitting layer EL2 and the fourth light emitting layer EL4. The third light emitting layer EL3 may be a red light emitting layer, and the fourth light emitting layer EL4 may be a green light emitting layer.

[0367] For example, Fig.33As shown in , the light emitting element LEL (e.g., an organic light emitting diode) may include a pixel electrode PE, a first light emitting layer EL1, a first charge generating layer CGL1, a third light emitting layer EL3, a second light emitting layer EL2, a second charge generating layer CGL2, a first light emitting layer EL1, and a common electrode CM stacked sequentially. Optionally, as Fig.31 As shown in the figure, the light-emitting element LEL (e.g., an organic light-emitting diode) may include a pixel electrode PE, a first light-emitting layer EL1, a first charge generation layer CGL1, a third light-emitting layer EL3, a second light-emitting layer EL2, a fourth light-emitting layer EL4, a second charge generation layer CGL2, a first light-emitting layer EL1 and a common electrode CM stacked sequentially.

[0368] Fig.35 It is shown Fig.33 A cross-sectional view of an example of an organic light emitting diode, and Fig.36 It is shown Fig.34 A cross-sectional view of an example of an organic light emitting diode.

[0369] Reference Fig.35 , the light emitting element LEL (e.g., an organic light emitting diode) may include a first emission unit EU1, a second emission unit EU2, and a third emission unit EU3 stacked in sequence. The first charge generation layer CGL1 may be disposed between the first emission unit EU1 and the second emission unit EU2, and the second charge generation layer CGL2 may be disposed between the second emission unit EU2 and the third emission unit EU3. The first charge generation layer CGL1 and the second charge generation layer CGL2 may include a negative charge generation layer nCGL and a positive charge generation layer pCGL, respectively.

[0370] The first emission unit EU1 may include a blue light emitting layer BEML. The first emission unit EU1 may further include a hole injection layer HIL and a hole transport layer HTL between the pixel electrode PE and the blue light emitting layer BEML. In one embodiment, a p-doped layer may be further included between the hole injection layer HIL and the hole transport layer HTL. The p-doped layer may be formed by doping the hole injection layer HIL with a p-type doping material. In one embodiment, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may be further included between the blue light emitting layer BEML and the hole transport layer HTL. The blue light auxiliary layer may improve the luminous efficiency of the blue light emitting layer BEML. The blue light auxiliary layer may improve the light emission efficiency of the blue light emitting layer BEML by adjusting the hole charge balance. The electron blocking layer may prevent electrons from being injected into the hole transport layer HTL. The buffer layer may compensate for the resonance distance according to the wavelength of light emitted from the light emitting layer.

[0371] The second emission unit EU2 may include a yellow light emitting layer YEML and a red light emitting layer REML directly contacting the yellow light emitting layer YEML below the yellow light emitting layer YEML. The second emission unit EU2 may further include a hole transport layer HTL between the positive charge generation layer pCGL of the first charge generation layer CGL1 and the red light emitting layer REML, and may further include an electron transport layer ETL between the yellow light emitting layer YEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0372] The third emission unit EU3 may include a blue light emitting layer BEML. The third emission unit EU3 may also include a hole transport layer HTL between the positive charge generation layer pCGL of the second charge generation layer CGL2 and the blue light emitting layer BEML. The third emission unit EU3 may also include an electron transport layer ETL and an electron injection layer EIL between the blue light emitting layer BEML and the common electrode CM. The electron transport layer ETL may have a single layer or multiple layers. In one embodiment, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may be further included between the blue light emitting layer BEML and the hole transport layer HTL. At least one of a hole blocking layer and a buffer layer may also be included between the blue light emitting layer BEML and the electron transport layer ETL. The hole blocking layer may prevent holes from being injected into the electron transport layer ETL.

[0373] Fig.36 The light emitting element LEL (e.g., organic light emitting diode) shown in FIG. Fig.35 The light emitting element LEL (eg, organic light emitting diode) shown in FIG. 1 is different in the stacking structure of the second emission unit EU2, and the other configurations are the same. Fig.36 , the second emission unit EU2 may include a yellow light emitting layer YEML, a green light emitting layer GEML directly contacting the yellow light emitting layer YEML below the yellow light emitting layer YEML, and an electron transport layer ETL directly contacting the yellow light emitting layer YEML above the yellow light emitting layer YEML. The second emission unit EU2 may further include a hole transport layer HTL between the positive charge generation layer pCGL of the first charge generation layer CGL1 and the red light emitting layer REML, and may further include an electron transport layer ETL between the green light emitting layer GEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0374] Fig.37 is a cross-sectional view showing a structure of a pixel of a display device according to an embodiment.

[0375] Reference Fig.37, the display panel 100 of the display device 10 may include a plurality of pixels (e.g., the above-mentioned sub-pixels). The plurality of pixels may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a pixel electrode PE, a common electrode CM, and an intermediate layer 203. In one embodiment, the first pixel PX1 may be a red pixel, the second pixel PX2 may be a green pixel, and the third pixel PX3 may be a blue pixel.

[0376] The pixel electrode PE may be independently disposed in each of the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 .

[0377] The intermediate layer 203 of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a first emission unit EU1 and a second emission unit EU2 stacked sequentially, and a charge generation layer CGL between the first emission unit EU1 and the second emission unit EU2. The charge generation layer CGL may include a negative charge generation layer nCGL and a positive charge generation layer pCGL. The charge generation layer CGL may be a common layer continuously formed in the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0378] The first emission unit EU1 of the first pixel PX1 may include a hole injection layer HIL, a hole transport layer HTL, a red light emitting layer REML, and an electron transport layer ETL sequentially stacked on the pixel electrode PE. The first emission unit EU1 of the second pixel PX2 may include a hole injection layer HIL, a hole transport layer HTL, a green light emitting layer GEML, and an electron transport layer ETL sequentially stacked on the pixel electrode PE. The first emission unit EU1 of the third pixel PX3 may include a hole injection layer HIL, a hole transport layer HTL, a blue light emitting layer BEML, and an electron transport layer ETL sequentially stacked on the pixel electrode PE. Each of the hole injection layer HIL, the hole transport layer HTL, and the electron transport layer ETL of the first emission unit EU1 may be a common layer continuously formed in the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0379] The second emission unit EU2 of the first pixel PX1 may include a hole transport layer HTL, an auxiliary layer AXL, a red light emitting layer REML, and an electron transport layer ETL sequentially stacked on the charge generation layer CGL. The second emission unit EU2 of the second pixel PX2 may include a hole transport layer HTL, a green light emitting layer GEML, and an electron transport layer ETL sequentially stacked on the charge generation layer CGL. The second emission unit EU2 of the third pixel PX3 may include a hole transport layer HTL, a blue light emitting layer BEML, and an electron transport layer ETL sequentially stacked on the charge generation layer CGL. Each of the hole transport layer HTL and the electron transport layer ETL of the second emission unit EU2 may be a common layer continuously formed in the first pixel PX1, the second pixel PX2, and the third pixel PX3. In one embodiment, at least one of a hole blocking layer and a buffer layer may also be included between the light emitting layer and the electron transport layer ETL in the second emission unit EU2 of the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0380] The thickness H1 of the red light emitting layer REML, the thickness H2 of the green light emitting layer GEML, and the thickness H3 of the blue light emitting layer BEML may be determined according to the resonance distance. The auxiliary layer AXL may be a layer added to adjust the resonance distance and may include a resonance auxiliary material. For example, the auxiliary layer AXL may include the same material as the hole transport layer HTL.

[0381] exist Fig.37 In the embodiment, the auxiliary layer AXL may be disposed only in the first pixel PX1, but the embodiments of the present disclosure are not limited thereto. For example, the auxiliary layer AXL may be disposed in at least one of the first pixel PX1, the second pixel PX2, and the third pixel PX3 to adjust the resonance distance of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0382] The display panel of the display device 10 may further include a cover layer 207 disposed outside the common electrode CM. The cover layer 207 may be used to improve the luminous efficiency through the principle of constructive interference. Therefore, the light extraction efficiency of the light emitting element LEL (e.g., organic light emitting diode) may be improved, thereby improving the luminous efficiency of the light emitting element LEL (e.g., organic light emitting diode).

[0383] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the preferred embodiments without departing substantially from the principles of the present invention. Therefore, the disclosed preferred embodiments of the present invention are used only in a general and descriptive sense, and not for the purpose of limitation.

Claims

1. A display device, characterized in that: The display device comprises: substrate; A first gate electrode is disposed on the substrate; a lower capacitor electrode disposed on the first gate electrode to overlap with the first gate electrode in a plane; and A repair line is disposed on the lower capacitor electrode.

2. The display device according to claim 1, characterized in that The display device further includes an upper capacitor electrode disposed on the lower capacitor electrode to overlap the lower capacitor electrode in a plane.

3. The display device according to claim 2, characterized in that: The first gate electrode overlaps the upper capacitor electrode in a plane.

4. The display device according to claim 2, characterized in that: An area of ​​the lower capacitor electrode is larger than an area of ​​the first gate electrode in a plane.

5. The display device according to claim 2, characterized in that: An area of ​​the upper capacitor electrode is larger than an area of ​​the lower capacitor electrode in a plane.

6. The display device according to claim 2, characterized in that: The display device further includes a driving voltage line connected to the upper capacitor electrode.

7. The display device according to claim 2, characterized in that: The repair line and the upper capacitor electrode are disposed on the same layer.

8. The display device according to claim 2, characterized in that: A second capacitor is formed by the lower capacitor electrode and the upper capacitor electrode.

9. The display device according to claim 2, characterized in that: The upper capacitor electrode has a greater number of holes than the lower capacitor electrode.

10. The display device according to claim 9, characterized in that: One of the holes in the upper capacitor electrode overlaps the hole in the lower capacitor electrode in a plane.

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