Light-load energy-saving control circuit of DCDC boosting device

Abstract

A light-load energy-saving control circuit of a DCDC boosting device comprises a reference judgment module, a boosting system switch driving control module, an energy-saving delay control module, a P-type transistor Q1 and an N-type transistor Q2. The reference judgment module comprises a comparator unit PFMCMP, a band-gap reference unit BANDGAP, an inductive current zero-crossing comparator unit ZCDCMP, an inductive current overcurrent comparator unit OCLCMP and a bias current unit BIAS; the boost system switch driving control module comprises an oscillator unit OSC, a logic control unit PFM CTRL LOGIC and a gate driving unit GATE DRIVER, so that the energy-saving time-delay control module can be used for closing current used when the system does not work, the power consumption of the boost device system during standby is greatly reduced, the consumption of energy storage equipment is reduced, and the power consumption of the boost device system is reduced. And the standby use time of the mobile portable device is prolonged.

Description

Technical Field

[0001] The utility model belongs to the technical field of integrated circuits (ICs), and relates to a light-load energy-saving control circuit of a DCDC boost device. Background Art

[0002] At present, DCDC boost devices are often used in application scenarios where low-voltage input power supplied by only 1 to 2 dry batteries or lithium battery energy storage devices needs to be converted into high-voltage power output. They are widely used in low-power handheld electronic devices such as digital cameras, LED lighting, wireless headphones and wireless mice.

[0003] See also Figure 1 , Figure 1 The figure shows a schematic diagram of the structure of a DCDC boost device system in the prior art. Figure 1 As shown, the system mainly includes a reference judgment module, a boost system switch drive control module, an inductor L1, a feedback resistor RFB1, a feedback resistor RFB2, a capacitor CIN, a capacitor COUT, a P-type transistor Q1 and an N-type transistor Q2 and other components.

[0004] The reference judgment module includes a comparator unit PFMCMP, a bandgap reference unit BANDGAP, an inductor current zero-crossing comparator unit ZCDCMP, an inductor current overcurrent comparator unit OCLCMP and a bias current unit BIAS; the boost system switch drive control module includes an oscillator unit OSC, a logic control unit PFM CTRL LOGIC and a drive module GATEDRIVER.

[0005] At startup, the external input VIN power supply is powered on, and the current from VIN charges the capacitor COUT through the inductor L1 and the P-type transistor Q1, and the output voltage VOUT rises to a voltage value close to VIN. The power supply of the internal modules is provided by the external input VIN. When the external input VIN meets the voltage that the system can work, the bias current unit BIAS is started first to provide the bias current IB for the comparator unit PFMCMP, the inductor current zero-crossing comparator unit ZCDCMP, and the inductor current overcurrent comparator unit OCLCMP. At the same time, the bandgap reference unit BANDGAP is started, and the output VREF is used to provide a reference voltage for the comparator unit PFMCMP. The output voltage output terminal voltage VOUT is divided by the resistor RFB1 and the resistor RFB2 to the comparator unit PFMCMP for comparison with the reference voltage VREF. When the comparator unit PFMCMP detects that VREF>FB, the comparator unit PFMCMP outputs an enable control signal of a logic high level PFM. At this time, the oscillator unit OSC starts to oscillate and output a fixed-period clock signal CLK. Under the premise that the enable signals of ZCD and OCL are invalid, the driver module DRIVER receives the square wave signal CLK and outputs VPG and VNG to connect the gates of the P-type transistor Q1 and the N-type transistor Q2 to realize the opening or closing of the P-type transistor Q1 and the N-type transistor Q2.

[0006] When the P-type transistor Q1 is turned off and the N-type transistor Q2 is turned on, the external input VIN, the inductor L1, and the transistor N-type transistor Q2 form a charging loop, and the inductor L1 begins to store energy; when the P-type transistor Q1 is turned on and the N-type transistor Q2 is turned off, the current across L1 will not change suddenly immediately, and a discharge loop will be formed between VIN and the output voltage VOUT. The energy of the inductor L1 is slowly released and transmitted to the output voltage VOUT through the P-type transistor Q1, thereby increasing the output voltage VOUT.

[0007] When FB>VREF, it means that the output voltage VOUT is greater than the target voltage. At this time, the comparator unit PFMCMP outputs a logic low signal to control the oscillator unit OSC to stop working. At this time, the clock signal CLK is always at a low level. After passing through the driver module DRIVER, the VNG signal continues to output a low level, and the N-type transistor Q2 cannot be turned on. During the energy release process of the inductor L1, the inductor current zero-crossing comparator unit ZCDCMP compares the voltage LX with the output voltage VOUT. When the output voltage VOUT>LX, it means that the current of the inductor L1 is released to nearly 0, and the output ZCD is a logic low signal. The ZCD signal outputs the PFMCTRL signal through the logic control unit PFM CTRL LOGIC and is transmitted to the gate drive unit GATE DRIVER, and the output VPG signal turns off the P-type transistor Q1 to prevent the current of the inductor L1 from flowing back to the input end.

[0008] When FB<VREF, it means that the output voltage VOUT is less than the target voltage. At this time, the PFMCMP module outputs a logic high signal to control the oscillator unit OSC to work and continuously output a fixed-cycle clock signal CLK. The logic control unit PFMCTRL LOGIC receives the square wave signal CLK and outputs the PFM CTRL signal to the gate drive unit GATE DRIVER, and outputs the corresponding VPG and VNG signals to control the P-type transistor Q1 and the N-type transistor Q2 to turn on or off. In the process of the continuous increase of the current of the inductor L1, the inductor current overcurrent comparator unit OCLCMP compares the size of LX and GND. When LX>GND, it means that the current of the inductor L1 exceeds the set current limit value, and outputs the OCL signal to the logic control unit PFM CTRL LOGIC. The logic control unit PFM CTRLLOGIC outputs the corresponding PFM CTRL signal to the gate drive unit GATE DRIVER to control the VNG signal to become a low level, thereby turning off Q2. Q2 will not be turned on again until the next CLK cycle starts, thereby limiting the peak value of the inductor current.

[0009] In the prior art, when the load is very small or there is no load, the P-type transistor Q1 and the N-type transistor Q2 will be turned off at the same time and no switching action will be performed. At this time, the system does not need to work. However, at this time, the bias current module BIAS in the reference judgment module will continue to provide bias current IB to the inductor current overcurrent comparator unit OCLCMP, the comparator unit PFMCMP module, the inductor current zero-crossing comparator unit ZCDCMP, etc. Since the power supply of the internal modules is provided by the output voltage VOUT, this part of the consumption accounts for a large proportion under light load, which will reduce the conversion efficiency under light load, and will undoubtedly shorten the standby time of many mobile energy storage power supply devices, which is contrary to the current design concept of low power consumption and high conversion efficiency of electronic equipment. Utility Model Content

[0010] In order to solve the above technical problems, the utility model proposes a light load energy-saving control circuit of a DCDC boost device. By adding a light load energy-saving delay control circuit module, the power consumption of the system itself can be reduced when the boost device is in standby state or light load working stage, the consumption of energy storage power supply device can be saved, the conversion efficiency can be improved, and the standby time of electronic equipment can be extended.

[0011] To achieve the above purpose, the technical solution of the utility model is as follows:

[0012] A light load energy-saving control circuit device of a DCDC boost device, comprising an output terminal VOUT, an input terminal VIN, a reference judgment module, a boost system switch drive control module, an energy-saving delay control module, a P-type transistor Q1, a feedback resistor RFB1, a feedback resistor RFB2, an inductor L1 and an N-type transistor Q2; the reference judgment module comprises a comparator unit PFMCMP, a bandgap reference unit BANDGAP, an inductor current zero-crossing comparator unit ZCDCMP, an inductor current overcurrent comparator unit OCLCMP and a bias current unit BIAS; the boost system switch drive control module comprises an oscillator unit OSC, a logic control unit PFM CTRL LOGIC and a gate drive unit GATE DRIVER; the feedback resistor RFB1 and the feedback resistor RFB2 are connected in series between the output voltage VOUT and the ground terminal GND to generate the divided voltage FB; one end of the L1 is connected to the drain of the P-type transistor Q1 and the N-type transistor Q2, and the other end of the L1 receives the input voltage VIN; the source of the P-type transistor Q1 is connected to the output terminal VOUT; the source of the N-type transistor Q2 is connected to the ground terminal GND; wherein the comparator unit PFMCMP, the bandgap reference unit BANDGAP, the inductor current zero-crossing comparator unit ZCDCMP, the inductor current overcurrent comparator unit OCLCMP, the bias current unit BIAS, the oscillator unit OSC, the logic control unit PFM CTRL The power supplies of the LOGIC and gate drive unit GATEDRIVER units are both provided by the voltage of the output terminal voltage VOUT. When the output terminal voltage VOUT meets the voltage of the system operation, the bias current unit BIAS provides the bias current IB for the comparator unit PFMCMP, the inductor current zero-crossing comparator unit ZCDCMP and the inductor current overcurrent comparator unit OCLCMP; the bandgap reference unit BANDGAP provides a reference voltage for the comparator unit PFMCMP; the comparator unit PFMCMP compares the reference voltage VREF with the output terminal VOUT The voltage division FB outputs the enable control signal PFM; the inductor current overcurrent comparator unit OCLCMP is used to compare the voltage of the LX signal and the ground terminal GND to determine whether the current on the inductor L1 is in an overcurrent state, and outputs the OCL signal; the inductor current zero-crossing comparator unit ZCDCMP is used to compare the voltage of the VOUT signal and the LX signal to determine whether the current on the inductor L1 is reverse flow, and output the ZCD signal; the oscillator unit OSC receives the enable control signal PFM and generates a periodic square wave signal CLK; the logic control unit PFM CTRL LOGIC receives the square wave signal CLK, the OCL signal and the ZCD signal, and outputs the PFMCTRL control signal;The gate driving unit GATE DRIVER is used to receive the PFMCTRL signal and output the VPG signal and the VNG signal to the gates of the P-type transistor Q1 and the N-type transistor Q2 respectively, to control the opening and closing of the P-type transistor Q1 and the N-type transistor Q2; the energy-saving delay control module includes a signal delay detection unit VNGDELAY, the signal delay detection unit VNG DELAY receives the VNG signal and outputs the VNGD signal to control the reduction of the bias current IB output by the bias current unit BIAS; the power supply of the signal delay detection unit VNG DELAY is provided by the voltage of the output terminal voltage VOUT. ;

[0013] Furthermore, the energy-saving delay control module also includes an energy-saving control unit ECO CTRL and a switch SW0, the switch SW0 is connected between the other end of the feedback resistor RFB2 and the ground terminal GND; one input end of the energy-saving control unit ECO CTRL receives the VNGD signal sent by the signal delay detection unit VNG DELAY, and the other input end receives the periodic square wave signal CLK generated by the oscillator unit OSC, and its output end outputs an ECO signal to the input ends of the bias current unit BIAS and the bandgap reference unit BANDGAP, and controls the opening and closing of the switch SW0, and outputs the ECO energy-saving signal to turn off the bias current IB.

[0014] Further, the energy-saving control unit ECO CTRL includes a switch SW1, a switch SW2, a switch SW3, a first N-type transistor Q1, a second N-type transistor Q2, a capacitor C1, a capacitor C2, a resistor R1, a resistor R2, an operational amplifier OP and a logic NAND gate X1; one end of the resistor R1, the resistor R2 and the capacitor C1 is connected to the output terminal VOUT, and the other end of the resistor R1 is connected to the drain of the first N-type transistor Q1, the gate of the first N-type transistor Q1, the bias voltage terminal VB of the operational amplifier OP, the gate of the second N-type transistor Q2 and the drain of the second N-type transistor Q2; one end of the capacitor C2, the source of the first N-type transistor Q1 and the second N-type transistor Q2 are connected to the ground terminal GND; the capacitor C1 The other end of the resistor R2, the other end of the switch SW2 and one end of the switch SW3 are connected together; the other end of the resistor R2, the other end of the switch SW2 and one end of the switch SW3 are connected to the node VR1; the other end of the switch SW3 is connected to the drain of the second N-type transistor Q2; the other end of the capacitor C2 is connected to the negative input end of the operational amplifier OP and one end of the switch SW1 at the node VN; one input end of the logic NAND gate X1 is connected to the other end of the switch SW1 and the output end of the operational amplifier OP, and the other input end of the logic NAND gate X1 is connected to the VNGD signal to output the ECO signal; the square wave signal CLK controls the opening and closing of the switches SW1, SW2 and SW3.

[0015] Furthermore, the light load energy-saving control circuit of the DCDC boost device also includes a capacitor COUT and a capacitor CIN, one end of the capacitor CIN is connected to the input voltage VIN and one end of the inductor L1, the other end of the capacitor CIN is connected to the ground terminal GND, and the other end of the inductor L1 is connected to the connection point of the LX signal terminal, the P-type transistor Q1 and the drain of the N-type transistor Q2; one end of the capacitor COUT is connected to the output voltage VOUT and the source of the P-type transistor Q1, and the other end is connected to the ground terminal GND.

[0016] It can be seen from the above technical scheme that the light load energy-saving control circuit device of the DCDC boost device of the utility model can shut down the current used when the system is not working through the energy-saving delay control module, which can greatly reduce the power consumption of the boost device system during standby, reduce the consumption of the energy storage device, improve the conversion efficiency of the light load, and increase the standby use time of the mobile portable device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 The structure diagram of the DCDC boost device in the prior art is shown as follows

[0018] Figure 2 The figure shows a schematic diagram of a preferred embodiment of a light load energy-saving control circuit of a DCDC boost device of the utility model.

[0019] Figure 3 The figure is a schematic diagram of a light load energy-saving control circuit of a DCDC boost device in another preferred embodiment of the utility model.

[0020] Figure 4 for Figure 3 Schematic diagram of the ECO control module (switch closed state) in the boost device system shown

[0021] Figure 5 for Figure 3 Schematic diagram of the ECO control module (switch open) in the boost system shown

[0022] Figure 6 The figure is a schematic diagram showing the average current comparison between the boost device system in the embodiment of the utility model and the boost device system in the prior art under no-load condition. DETAILED DESCRIPTION

[0023] The following is combined with Figure 2-6 , the specific implementation methods of the utility model are further described in detail.

[0024] Example 1

[0025] See also Figure 2 , Figure 2 The figure shows a schematic diagram of a preferred embodiment of a light load energy-saving control circuit of a DCDC boost device in an embodiment of the present utility model. Figure 2 As shown, the circuit may include an output terminal VOUT, an input terminal VIN, a reference judgment module, a boost system switch drive control module, an energy-saving delay control module, a P-type transistor Q1, a feedback resistor RFB1, a feedback resistor RFB2, an inductor L1 and an N-type transistor Q2; the reference judgment module includes a comparator unit PFMCMP, a bandgap reference unit BANDGAP, an inductor current zero-crossing comparator unit ZCDCMP, an inductor current overcurrent comparator unit OCLCMP and a bias current unit BIAS; the boost system switch drive control module includes an oscillator unit OSC, a logic control unit PFM CTRLLOGIC and a gate drive unit GATE DRIVER; the feedback resistor RFB1 and the feedback resistor RFB2 are connected in series between the output voltage VOUT and the ground terminal GND to generate the divided voltage FB; one end of the L1 is connected to the drain of the P-type transistor Q1 and the N-type transistor Q2, and the other end of the L1 receives the input voltage VIN; the source of the P-type transistor Q1 is connected to the output terminal VOUT; the source of the N-type transistor Q2 is connected to the ground terminal GND.

[0026] The comparator unit PFMCMP, the bandgap reference unit BANDGAP, the inductor current zero-crossing comparator unit ZCDCMP, the inductor current overcurrent comparator unit OCLCMP, the bias current unit BIAS, the oscillator unit OSC, the logic control unit PFM CTRL LOGIC and the gate drive unit GATE The power supply of DRIVER is provided by the voltage of the output terminal voltage VOUT. When the output terminal voltage VOUT meets the voltage of the system operation, the bias current unit BIAS provides the bias current IB for the comparator unit PFMCMP, the inductor current zero-crossing comparator unit ZCDCMP and the inductor current overcurrent comparator unit OCLCMP; the bandgap reference unit BANDGAP provides a reference voltage for the comparator unit PFMCMP; the comparator unit PFMCMP compares the reference voltage VREF with the divided voltage FB of the output terminal VOUT voltage, and outputs an enable control signal PFM; the inductor current overcurrent comparator unit OCLCMP is used to compare the voltage of the LX signal and the ground terminal GND to determine whether the current on the inductor L1 is in an overcurrent state, and outputs an OCL signal; the inductor current zero-crossing comparator unit ZCDCMP is used to compare the voltage of the VOUT signal and the LX signal to determine whether the current on the inductor L1 is reverse flow, and outputs a ZCD signal.

[0027] The oscillator unit OSC receives the enable control signal PFM to generate a periodic square wave signal CLK; the logic control unit PFM CTRL LOGIC receives the square wave signal CLK, the OCL signal and the ZCD signal, and outputs the PFMCTRL control signal; the gate drive unit GATE DRIVER is used to receive the PFMCTRL signal and output the VPG signal and the VNG signal to the gates of the P-type transistor Q1 and the N-type transistor Q2 respectively, to control the opening and closing of the P-type transistor Q1 and the N-type transistor Q2.

[0028] The energy-saving delay control module includes a signal delay detection unit VNG DELAY, which receives a VNG signal and outputs a VNGD signal to control the reduction of the bias current IB output by the bias current unit BIAS; the power supply of the signal delay detection unit VNG DELAY is provided by the voltage of the output terminal voltage VOUT.

[0029] In some embodiments of the present utility model, the energy-saving control unit ECO CTRL includes a switch SW1, a switch SW2, a switch SW3, a first N-type transistor Q1, a second N-type transistor Q2, a capacitor C1, a capacitor C2, a resistor R1, a resistor R2, an operational amplifier OP and a logic NAND gate X1; one end of the resistor R1, the resistor R2 and the capacitor C1 is connected to the output terminal VOUT, and the other end of the resistor R1 is connected to the drain of the first N-type transistor Q1, the gate of the first N-type transistor Q1, the bias voltage terminal VB of the operational amplifier OP, the gate of the second N-type transistor Q2 and the drain of the second N-type transistor Q2; one end of the capacitor C2, the source of the first N-type transistor Q1 and the second N-type transistor Q2 are connected to the ground terminal GND; the capacitor C1 The other end of the resistor R2, the other end of the switch SW2 and one end of the switch SW3 are connected together; the other end of the resistor R2, the other end of the switch SW2 and one end of the switch SW3 are connected to the node VR1; the other end of the switch SW3 is connected to the drain of the second N-type transistor Q2; the other end of the capacitor C2 is connected to the negative input end of the operational amplifier OP and one end of the switch SW1 at the node VN; one input end of the logic NAND gate X1 is connected to the other end of the switch SW1 and the output end of the operational amplifier OP, and the other input end of the logic NAND gate X1 is connected to the VNGD signal to output the ECO signal; the square wave signal CLK controls the opening and closing of the switches SW1, SW2 and SW3.

[0030] In some other embodiments of the utility model, the light load energy-saving control circuit of the DCDC boost device further includes a capacitor COUT and a capacitor CIN, one end of the capacitor CIN is connected to the input voltage VIN and one end of the inductor L1, the other end of the capacitor CIN is connected to the ground terminal GND, and the other end of the inductor L1 is connected to the connection point of the LX signal terminal, the P-type transistor Q1 and the drain of the N-type transistor Q2; one end of the capacitor COUT is connected to the output voltage VOUT and the source of the P-type transistor Q1, and the other end is connected to the ground terminal GND.

[0031] Specifically, when the system starts, the external input VIN power supply is powered on, the current from VIN charges the capacitor COUT through the inductor L1 and the P-type transistor Q1, and the output voltage VOUT rises to a voltage value close to VIN. The power supply of the internal modules is provided by the voltage of the output voltage VOUT. When the output voltage VOUT meets the voltage that the system can work, the bias current unit BIAS provides the bias current IB for the comparator unit PFMCMP, the inductor current zero-crossing comparator unit ZCDCMP and the inductor current overcurrent comparator unit OCLCMP; the bandgap reference unit BANDGAP provides the reference voltage for the comparator unit PFMCMP and the inductor current overcurrent comparator unit OCLCMP.

[0032] When the comparator unit PFMCMP detects that VREF>FB, the comparator unit PFMCMP outputs an enable control signal of logic high level PFM. At this time, the oscillator unit OSC starts to oscillate and output a clock signal CLK with a fixed period. Under the premise that the ZCD and OCL enable control signals are invalid, the logic control unit PFM CTRL LOGIC receives the square wave signal CLK and outputs the PFMCTRL signal to the driving module GATE DRIVER. The driving module GATE DRIVER outputs the corresponding VPG and VNG signals according to the received PFM CTRL signal to connect the gates of the P-type transistor Q1 and the N-type transistor Q2, so as to turn on or off the P-type transistor Q1 and the N-type transistor Q2. When the P-type transistor Q1 is turned off and the N-type transistor Q2 is turned on, the external input VIN, the inductor L1 and the N-type transistor Q2 form a charging loop, and the inductor L1 begins to store energy; when the P-type transistor Q1 is turned on and the N-type transistor Q2 is turned off, the current across L1 will not change suddenly immediately, and a discharge loop is formed between VIN and the output voltage VOUT. The energy on the inductor L1 begins to be released, and the inductor energy is transmitted to the output voltage VOUT through the P-type transistor Q1, thereby increasing the output voltage VOUT.

[0033] When FB>VREF, it means that the output voltage VOUT is greater than the target voltage. At this time, PFMCMP outputs a logic low level signal to control the oscillator unit OSC to stop working. At this time, the clock signal CLK is always at a low level. The logic control unit PFM CTRL LOGIC outputs a PFM CTRL low level signal to make the subsequent drive module GATE DRIVER output a continuously low level VNG signal, and the N-type transistor Q2 cannot be turned on.

[0034] When the inductor L1 releases energy, the inductor current zero-crossing comparator unit ZCDCMP compares the voltage LX with the output voltage VOUT to determine whether the current on the inductor L1 is zero, and outputs a ZCD signal to the logic control unit PFM CTRLLOGIC. The logic control unit PFM CTRL LOGIC outputs a PFM CTRL signal to the drive module GATE DRIVER, and outputs a VPG signal to turn off the P-type transistor Q1 to prevent the current of the inductor L1 from flowing back to the input end.

[0035] When FB<VREF, it means that the output voltage VOUT is less than the target voltage. At this time, PFMCMP outputs a logic high level signal to control the oscillator unit OSC to work and continuously output a fixed-cycle clock signal CLK. The logic control unit PFM CTRLLOGIC receives the square wave signal CLK and outputs the PFM CTRL signal to the driver module GATE DRIVER, and outputs the corresponding VPG and VNG to control the P-type transistor Q1 and the N-type transistor Q2 to turn on or off. In the process of the continuous increase of the current of the inductor L1, the OCLCMP module compares the size of LX and GND. When LX>GND, it means that the current of the inductor L1 exceeds the set current limit value, and outputs the OCL signal to the logic control unit PFM CTRL LOGIC. The logic control unit PFM CTRL LOGIC outputs the corresponding PFM CTRL signal to the driver module GATE DRIVER to control the VNG signal to become a low level, thereby turning off the N-type transistor Q2 until the next CLK cycle begins, and the N-type transistor Q2 will be turned on again, thereby limiting the peak value of the inductor current.

[0036] When the output end is in the state of no-load or light-load, the boost device system will reduce the frequency of switching the P-type transistor Q1 and the N-type transistor Q2, and will intermittently turn off the P-type transistor Q1 and the N-type transistor Q2 at the same time. When the VNG DELAY module in the energy-saving delay control module detects that the VNG signal is in a long-term closed state, it will output a VNGD signal to the BIAS module. The VNGD signal will turn off certain bias current branches to reduce the system's consumption of bias current at this time, thereby reducing the consumption of the energy storage device and increasing the standby time of the mobile portable device.

[0037] Example 2

[0038] See also Figure 3 , Figure 3 FIG. 2 is a schematic diagram of a light load energy-saving control circuit of a DCDC boost device in another preferred embodiment of the present invention. Figure 3As shown, the circuit may include a reference judgment module, a boost system switch drive control module, an energy-saving delay control module, a P-type transistor Q1, an N-type transistor Q2, and some inductors, capacitors, resistors and other components.

[0039] In addition to the signal delay detection unit VNG DELAY, the energy-saving delay control module may further include an energy-saving control unit ECO CTRL and a switch SW0, wherein the switch SW0 is connected between the other end of the feedback resistor RFB2 and the ground terminal GND; one input end of the energy-saving control unit ECO CTRL receives the VNGD signal sent by the signal delay detection unit VNGDELAY, and the other input end receives the periodic square wave signal CLK generated by the oscillator unit OSC, and its output end outputs an ECO signal to the input ends of the bias current unit BIAS and the bandgap reference unit BANDGAP, and controls the opening and closing of the switch SW0, and outputs the ECO energy-saving signal to turn off the bias current IB.

[0040] When the system starts, the external input VIN power supply is powered on, and the current from VIN charges the capacitor COUT through the inductor L1 and the P-type transistor Q1, and the output voltage VOUT rises to a voltage value close to VIN. The power supply of the internal modules is provided by the output voltage VOUT. When the output voltage VOUT meets the voltage that the system can work, the BIAS module is started first to provide bias current IB for PFMCMP, ZCDCMP, and OCLCMP. At the same time, the BANDGAP module is started and outputs VREF to provide a reference voltage for the PFMCMP module. The output voltage VOUT is divided by R1 and R2 to obtain a voltage FB to the PFMCMP module for comparison with VREF. When PFMCMP detects that VREF>FB, the PFMCMP module outputs an enable control signal with PFM as a logic high level. At this time, the oscillator unit OSC starts to oscillate and output a fixed-period clock signal CLK. Under the premise that the ZCD and OCL enable control signals are invalid, the logic control unit PFM CTRL LOGIC receives the square wave signal CLK and outputs the PFM CTRL signal to the driver module GATE DRIVER. The driver module GATE DRIVER outputs the corresponding VPG and VNG signals according to the received PFM CTRL signal to connect the gates of the P-type transistor Q1 and the N-type transistor Q2 to realize the opening or closing of the P-type transistor Q1 and the N-type transistor Q2. When the P-type transistor Q1 is turned off and the N-type transistor Q2 is turned on, the external input VIN and the inductors L1 and Q2 form a charging loop, and the inductor L1 begins to store energy; when the P-type transistor Q1 is turned on and the N-type transistor Q2 is turned off, the current across L1 will not change suddenly immediately, and a discharge loop will be formed between VIN and the output voltage VOUT. The energy on the inductor L1 begins to be released, and the inductor energy is transmitted to the output voltage VOUT through the P-type transistor Q1, thereby increasing the output voltage VOUT.

[0041] When FB>VREF, it means that the output voltage VOUT is greater than the target voltage. At this time, PFMCMP outputs a logic low signal to control the oscillator unit OSC to stop working. At this time, the clock signal CLK is always at a low level. After the logic control unit PFM CTRL LOGIC outputs a PFM CTRL low signal, the subsequent driver module GATE DRIVER outputs a continuously low-level VNG signal, and the N-type transistor Q2 cannot be turned on. During the energy release process of the inductor L1, the inductor current zero-crossing comparator unit ZCDCMP compares the LX with the output voltage VOUT voltage to determine whether the current on the inductor L1 is zero, and outputs a ZCD signal to the logic control unit PFM CTRL LOGIC. The logic control unit PFM CTRL LOGIC outputs a PFM CTRL signal to the driver module GATE DRIVER, and outputs a VPG signal to turn off the P-type transistor Q1 to prevent the current of the inductor L1 from flowing back to the input end.

[0042] When FB<VREF, it means that the output voltage VOUT is less than the target voltage. At this time, PFMCMP outputs a logic high signal to control the oscillator unit OSC to work and continuously output a fixed-cycle clock signal CLK. The logic control unit PFM CTRLLOGIC receives the square wave signal CLK and outputs the PFM CTRL signal to the driver module GATE DRIVER, and outputs the corresponding VPG and VNG to control the P-type transistor Q1 and the N-type transistor Q2 to turn on or off. In the process of the continuous increase of the current of the inductor L1, the OCLCMP module compares the size of LX and GND. When LX>GND, it means that the current of the inductor L1 exceeds the set current limit value, and outputs the OCL signal to the logic control unit PFM CTRL LOGIC. The logic control unit PFM CTRL LOGIC outputs the corresponding PFMCTRL signal to the driver module GATE DRIVER to control the VNG signal to become a low level, thereby turning off the N-type transistor Q2 until the next CLK cycle begins, and the N-type transistor Q2 will be turned on again, thereby limiting the peak value of the inductor current.

[0043] See also Figure 4-5 , Figure 4 for Figure 3 Schematic diagram of the ECO control module (switch closed state) in the boost device system shown; Figure 5 for Figure 3 Schematic diagram of the ECO control module (switch open state) in the boost device system shown.

[0044] When the output end is in the state of no-load or light-load, the boost device system will reduce the frequency of switching the P-type transistor Q1 and the N-type transistor Q2, and will intermittently turn off the P-type transistor Q1 and the N-type transistor Q2 at the same time. When the signal delay detection unit VNG DELAY in the energy-saving delay control module detects that the VNG signal is in a long-term closed state, it will output the VNGD signal to the energy-saving control unit ECO CTRL; the square wave signal CLK output by the oscillator unit OSC controls the energy-saving control unit ECO CTRL. When the square wave signal CLK is at a high level, the switches SW1, SW2 and SW3 of the energy-saving control unit ECO CTRL are in a closed state. At this time, the output voltage VOUT will be sampled in real time, and a fixed voltage difference will be generated between the output voltage VOUT and VR1 and stored on the C1 capacitor, and the information of VR1 will be kept on the C2 capacitor; when the square wave signal CLK is at a low level, the energy-saving control unit ECO The switches SW1, SW2 and SW3 in CTRL are in the disconnected state. Since the fixed voltage across the capacitor C1 cannot change suddenly, the voltage change of the output voltage VOUT will cause a corresponding voltage change on VR1, generating a new VR1'. VR1' is compared with the previous VR1 on the capacitor C2. When VR1' is greater than VR1 on the capacitor C2, and VNGD is at a high level at this time, that is, the transistor Q2 is in a long-term closed state, that is, the system is in an energy-saving state, ECO outputs a low-level signal, turns off the enable signals of the bias current unit BIAS and the bandgap reference unit BANDGAP and the switch SW0 on the voltage divider resistor. At this time, only the energy-saving control unit ECO CTRL of the internal module will consume a weak current, and the current of other internal modules is cut off by the ECO signal. As VR1' continues to decrease, when VR1' is less than VR1, the ECO signal will rise to a high level, and the corresponding other internal modules will be reopened at this time to make the system work normally.

[0045] See also Figure 6 , Figure 6 The figure shows a comparison of the average current of the boost device system in the embodiment of the utility model and the boost device system in the prior art under no-load condition. Figure 6 As shown, the energy-saving delay control module of the utility model can shut down the current used when the system is not working, which can greatly reduce the power consumption of the boost device system during standby, reduce the consumption of energy storage equipment, improve the conversion efficiency of light loads, and increase the standby use time of mobile portable devices.

[0046] The above-described embodiments are only preferred embodiments of the present invention, and the embodiments are not intended to limit the patent protection scope of the present invention. Therefore, all equivalent structural changes made using the description and drawings of the present invention should also be included in the protection scope of the present invention.

Claims

1. A light load energy-saving control circuit for a DCDC boost device, characterized in that: It includes an output terminal VOUT, an input terminal VIN, a reference judgment module, a boost system switch drive control module, an energy-saving delay control module, a P-type transistor Q1, a feedback resistor RFB1, a feedback resistor RFB2, an inductor L1 and an N-type transistor Q2; the reference judgment module includes a comparator unit PFMCMP, a bandgap reference unit BANDGAP, an inductor current zero-crossing comparator unit ZCDCMP, an inductor current overcurrent comparator unit OCLCMP and a bias current unit BIAS; the boost system switch drive control module includes an oscillator unit OSC, a logic control unit PFM CTRL LOGIC and a gate drive unit GATE DRIVER; the feedback resistor RFB1 and the feedback resistor RFB2 are connected in series between the output terminal voltage VOUT and the ground terminal GND to generate a divided voltage FB; one end of the L1 is connected to the drain of the P-type transistor Q1 and the N-type transistor Q2, and the other end of the L1 receives the input voltage VIN; the source of the P-type transistor Q1 is connected to the output terminal VOUT; the source of the N-type transistor Q2 is connected to the ground terminal GND; The power supplies of the comparator unit PFMCMP, the bandgap reference unit BANDGAP, the inductor current zero-crossing comparator unit ZCDCMP, the inductor current overcurrent comparator unit OCLCMP, the bias current unit BIAS, the oscillator unit OSC, the logic control unit PFM CTRL LOGIC and the gate drive unit GATE DRIVER are all provided by the voltage of the output terminal voltage VOUT. When the output terminal voltage VOUT meets the voltage of the system operation, the bias current unit BIAS A bias current IB is provided for the comparator unit PFMCMP, the inductor current zero-crossing comparator unit ZCDCMP and the inductor current overcurrent comparator unit OCLCMP; the bandgap reference unit BANDGAP provides a reference voltage for the comparator unit PFMCMP; the comparator unit PFMCMP compares the reference voltage VREF with the divided voltage FB of the output terminal VOUT voltage, and outputs an enable control signal PFM; the inductor current overcurrent comparator unit OCLCMP is used to compare the voltage of the LX signal and the ground terminal GND to determine whether the current on the inductor L1 is in an overcurrent state, and output an OCL signal; the inductor current zero-crossing comparator unit ZCDCMP is used to compare the voltage of the VOUT signal and the LX signal to determine whether the current on the inductor L1 is reverse flow, and output a ZCD signal; The oscillator unit OSC receives the enable control signal PFM and generates a periodic square wave signal CLK; the logic control unit PFM CTRL LOGIC receives the square wave signal CLK, the OCL signal and the ZCD signal, and outputs the PFMCTRL control signal; the gate drive unit GATE DRIVER is used to receive the PFMCTRL signal and output the VPG signal and the VNG signal to the gates of the P-type transistor Q1 and the N-type transistor Q2, respectively, to control the opening and closing of the P-type transistor Q1 and the N-type transistor Q2; The energy-saving delay control module includes a signal delay detection unit VNG DELAY, which receives a VNG signal and outputs a VNGD signal to control the reduction of the bias current IB output by the bias current unit BIAS; the power supply of the signal delay detection unit VNG DELAY is provided by the voltage of the output terminal voltage VOUT.

2. The light load energy-saving control circuit of the DCDC boost device according to claim 1, characterized in that: The energy-saving delay control module also includes an energy-saving control unit ECO CTRL and a switch SW0, wherein the switch SW0 is connected between the other end of the feedback resistor RFB2 and the ground terminal GND; an input end of the energy-saving control unit ECO CTRL receives the VNGD signal sent by the signal delay detection unit VNG DELAY, and another input end receives the periodic square wave signal CLK generated by the oscillator unit OSC, and an output end thereof outputs an ECO signal to the input ends of the bias current unit BIAS and the bandgap reference unit BANDGAP, and controls the opening and closing of the switch SW0, and outputs an ECO energy-saving signal to turn off the bias current IB.

3. The light load energy-saving control circuit of the DCDC boost device according to claim 2, characterized in that: The energy-saving control unit ECO CTRL includes a switch SW1, a switch SW2, a switch SW3, a first N-type transistor Q1, a second N-type transistor Q2, a capacitor C1, a capacitor C2, a resistor R1, a resistor R2, an operational amplifier OP and a logic NAND gate X1; one end of the resistor R1, the resistor R2 and the capacitor C1 is connected to the output terminal VOUT, and the other end of the resistor R1 is connected to the drain of the first N-type transistor Q1, the gate of the first N-type transistor Q1, the bias voltage terminal VB of the operational amplifier OP, the gate of the second N-type transistor Q2 and the drain of the second N-type transistor Q2; one end of the capacitor C2, the source of the first N-type transistor Q1 and the second N-type transistor Q2 are connected to the ground terminal GND; the capacitor C1 The other end of the resistor R2, the other end of the switch SW2 and one end of the switch SW3 are connected together; the other end of the resistor R2, the other end of the switch SW2 and one end of the switch SW3 are connected to the node VR1; the other end of the switch SW3 is connected to the drain of the second N-type transistor Q2; the other end of the capacitor C2 is connected to the negative input end of the operational amplifier OP and one end of the switch SW1 at the node VN; one input end of the logic NAND gate X1 is connected to the other end of the switch SW1 and the output end of the operational amplifier OP, and the other input end of the logic NAND gate X1 is connected to the VNGD signal to output the ECO signal; the square wave signal CLK controls the opening and closing of the switches SW1, SW2 and SW3.

4. The light load energy-saving control circuit of the DCDC boost device according to claim 1, characterized in that: It also includes a capacitor COUT and a capacitor CIN, one end of the capacitor CIN is connected to the input voltage VIN and one end of the inductor L1, the other end of the capacitor CIN is connected to the ground terminal GND, and the other end of the inductor L1 is connected to the connection point of the LX signal, the P-type transistor Q1 and the drain of the N-type transistor Q2; one end of the capacitor COUT is connected to the output voltage VOUT and the source of the P-type transistor Q1, and the other end is connected to the ground terminal GND.

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