Chip lamination packaging structure

Abstract

The utility model discloses a chip lamination packaging structure, which comprises a substrate, a main chip inversely arranged on the front surface of the substrate, filling materials filled between the main chip and the substrate, first solder balls planted on a first bonding pad of the substrate around the main chip, a plastic packaging layer arranged on the front surface of the substrate, the first solder balls and the main chip are coated by the plastic packaging layer, but the tops of the main chip and the first solder balls are exposed. A high-bandwidth memory chip is arranged above the main chip in an inverted mode, the top of a first welding ball is welded to a second welding disc of the high-bandwidth memory chip, a groove is formed in the portion, located on one side of the high-bandwidth memory chip, of the plastic package layer and located on the periphery of the first welding ball, and a second welding ball is planted on the back face of the substrate. According to the utility model, the CPU / GPU and other main chips are inversely arranged on the substrate, and then the balls on the surface of the substrate and the high-bandwidth memory chip are vertically interconnected in a short distance through the lamination packaging technology, so that the packaging structure is smaller in size, the space occupied by subsequent assembly is smaller, the chip miniaturization is realized, the electric signal connection path is greatly shortened, and the low delay of signal transmission is realized.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor packaging, and more specifically to a chip stacking packaging structure for a high-bandwidth memory chip. Background Art

[0002] High Bandwidth Memory (HBM) is a memory chip designed to solve the high bandwidth requirements of high-performance CPUs / GPUs. HBM packages multiple traditional DRAM (Dynamic Random Access Memory) memory chips vertically to solve the limitation of insufficient bandwidth of traditional DRAM on the computing power of high-performance CPUs / GPUs and give full play to the computing power performance.

[0003] HBM is packaged together with main chips such as CPU / GPU to form a specific module, and then connected to the circuit board. In the prior art, main chips such as CPU / GPU are placed side by side with stacked DRAM chips and packaged on a substrate. This results in a large package structure, which occupies a lot of space, making it difficult to miniaturize the chip, and the electrical signal connection path is long, resulting in long signal delay. Utility Model Content

[0004] In order to solve the above problems, the utility model provides a low-latency, small-size storage and computing integrated chip stacking packaging structure.

[0005] According to one aspect of the utility model, a chip stacking packaging structure is provided, which includes a substrate, a main chip is flipped on the front side of the substrate, a filler is filled between the main chip and the substrate, a solder ball 1 is implanted on a solder pad 1 of the substrate around the main chip, a high-bandwidth memory chip is flipped on top of the main chip, the high-bandwidth memory chip includes a plurality of high-bandwidth memory wafers stacked in a vertical direction, and the top of the solder ball 1 is welded to a solder pad 2 of the high-bandwidth memory chip.

[0006] In some embodiments, a plastic encapsulation layer is disposed on the front side of the substrate, and the plastic encapsulation layer covers the solder ball 1 and the main chip, but exposes the top of the main chip and the solder ball 1.

[0007] In some implementations, a groove is formed on the plastic packaging layer located on one side of the high bandwidth memory chip and around the solder ball.

[0008] In some embodiments, solder balls 2 are implanted on the back side of the substrate.

[0009] In some embodiments, the high-bandwidth memory wafers in the high-bandwidth memory chip are connected via bumps, and the main chip is provided with one or more bumps.

[0010] Compared with the prior art, the beneficial effects of the present invention are as follows: the present invention plants a solder ball on the surface of a substrate, and flips the main chip such as the CPU / GPU on the substrate, and then vertically interconnects the solder ball on the surface of the substrate with the high-bandwidth memory chip (HBM / HighBandwidth Memory) through the PoP (Package on Package) stacking packaging technology. Compared with the prior art, the stacking packaging structure has a smaller packaging structure size, occupies less space for subsequent assembly, realizes chip miniaturization, and greatly shortens the electrical signal connection path, thereby achieving low latency in signal transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a schematic diagram of the structure of a chip stacking packaging structure of the utility model;

[0012] Figure 2 It is a schematic diagram of the packaging process before the plastic sealing layer is thinned;

[0013] Figure 3 It is a schematic diagram of the packaging process after the plastic layer is thinned. DETAILED DESCRIPTION

[0014] The utility model is further described below in conjunction with specific implementation methods.

[0015] like Figure 1 As shown, a chip stacking package structure of one embodiment of the utility model comprises a substrate 1, a main chip 2 is flipped on the front of the substrate 1, a filler 3 is filled between the main chip 2 and the substrate 1, the filler 3 surrounds the periphery of the main chip 2 and fills the bottom connected to the substrate 1, and a solder ball 4 is planted on the pad 11 of the substrate 1 around the main chip 2; a plastic sealing layer 5 is sealed on the front of the substrate 1, the plastic sealing layer 5 covers the solder ball 4 and the main chip 2, but the top of the main chip 2 and the solder ball 4 are exposed, and a groove 51 is opened on the plastic sealing layer 5 located on one side of the high-bandwidth memory chip 6 along the periphery of the solder ball 4; a high-bandwidth memory chip 6 is flipped on the top of the main chip 2, and the top of the solder ball 4 is welded to the pad 2 62 of the high-bandwidth memory chip 6. A solder ball 2 7 is planted on the back of the substrate 1.

[0016] The high bandwidth memory chip 6 includes a plurality of vertically stacked high bandwidth memory wafers 61. The high bandwidth memory wafers 61 in the high bandwidth memory chip 6 are connected via bumps 63. The main chip 2 in the chip stacking package structure may be one or more.

[0017] Combination Figure 2 and 3 , specifically describing the packaging process of the chip stacking packaging structure described in this application, the steps are as follows:

[0018] Step 1: If Figure 2 As shown in FIG. 2A , a substrate 1 is taken, and solder balls are planted on corresponding pads 11 around the main chip 2 to be flip-mounted on the front side of the substrate 1 to form solder balls 4 .

[0019] Step 2: If Figure 2 2B and 2C. Take the main chip 2, flip-chip solder the main chip 2 to the front of the substrate 1, and complete the bottom filling, the filling material 3 is filled between the main chip 2 and the substrate 1, and around the lower half of the main chip 2.

[0020] In each chip stacking package structure, the number of the main chips 2 can be one or more.

[0021] Step 3: If Figure 2 As shown in FIG. 2D , the substrate 1 is plastic-sealed to form a plastic-sealing layer 5 on the front side of the substrate 1 . During the plastic-sealing process, the plastic-sealing material covers the front side of the substrate 1 , the solder ball 1 4 and the main chip 2 . After the plastic-sealing material is solidified, the plastic-sealing layer 5 is formed.

[0022] Step 4: Thin the plastic layer 5 to expose the main chip 2 and the top of the solder ball 4. Figure 3 As shown in Figure 2E.

[0023] Step 5: Use laser technology to create grooves 51 around the solder ball 4, such as Figure 3 As shown in 2F.

[0024] Step 6: If Figure 3 As shown in FIG. 2G , the high-bandwidth memory chip 6 is prepared in advance, and the high-bandwidth memory chip 6 is flip-chip soldered on the surface of the solder ball 1 4 .

[0025] Step 7: Planting balls on the back of substrate 1 to form solder balls 7, such as Figure 3 As shown in 2H.

[0026] The utility model plants solder balls 4 on the surface of a substrate 1, and flips a main chip 2 such as a CPU / GPU onto the substrate 1, and then vertically interconnects the solder balls 4 on the surface of the substrate 1 with a high-bandwidth memory chip 6 (HBM / High Bandwidth Memory) through PoP (Package on Package) stacking packaging technology. Compared with the existing structure, the stacking packaging structure has a smaller packaging structure size, occupies less space for subsequent assembly, realizes chip miniaturization, and greatly shortens the electrical signal connection path, thereby achieving low latency in signal transmission.

[0027] The above are only some embodiments of the present invention. It should be pointed out that for ordinary technicians in this field, other modifications and improvements can be made without departing from the creative concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A chip stacking package structure, comprising a substrate (1), characterized in that: A main chip (2) is flip-mounted on the front side of the substrate (1), a filler (3) is filled between the main chip (2) and the substrate (1), a solder ball (4) is implanted on a solder pad (11) of the substrate (1) around the main chip (2), a high-bandwidth memory chip (6) is flip-mounted on top of the main chip (2), the high-bandwidth memory chip (6) comprises a plurality of high-bandwidth memory wafers (61) stacked in a vertical direction, and the top of the solder ball (4) is soldered to a solder pad (62) of the high-bandwidth memory chip (6).

2. The chip stacking package structure according to claim 1, characterized in that: A plastic sealing layer (5) is provided on the front side of the substrate (1), and the plastic sealing layer (5) covers the solder ball one (4) and the main chip (2), but exposes the top of the main chip (2) and the solder ball one (4).

3. The chip stacking package structure according to claim 2, characterized in that: A groove (51) is provided around the solder ball one (4) on the plastic packaging layer (5) located on one side of the high-bandwidth memory chip (6).

4. The chip stacking package structure according to claim 1 or 3, characterized in that: A second solder ball (7) is implanted on the back side of the substrate (1).

5. The chip stacking package structure according to claim 1, characterized in that: The high-bandwidth memory wafers (61) in the high-bandwidth memory chip (6) are connected to each other via bumps (63), and the main chip (2) is provided with one or more bumps.

Images