Semiconductor package
By designing the structure of substrate, rewiring layer, electronic components and conductive columns in semiconductor packages, the problem of RDL construction difficulty in embedded structures is solved, and more efficient packaging performance is achieved.
Patent Information
- Application Number
- CN202421187613.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-28
- Publication Date
- 2025-02-25
- Estimated Expiration
- 2034-05-28
AI Technical Summary
There are challenges in building fine-pitched rewiring layers (RDLs) in embedded structures, especially due to structural warping caused by the difference in thermal expansion coefficient between the fill material and the active element, which in turn increases the construction difficulty of RDLs.
The design of a semiconductor package is employed, including a substrate, a first heavy wiring layer, a first electronic component and a first conductive post. The first conductive post overlaps the first electronic component in the lateral direction, and covers the element and the conductive post through the bottom fill layer to form a fan-out embedded structure to match the thickness of the first electronic component and avoid the rewiring layer being damaged by the component collision. .
Through this design, the goal of improving performance in semiconductor packages is achieved, the problem of the rewiring layer being damaged by component collision is avoided, and the production difficulty is reduced.
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Figure CN222530436U_ABST
Abstract
Description
Technical Field
[0001] An embodiment of the utility model relates to a semiconductor package. Background Art
[0002] High-density interconnect embedding technology or packaging is used for further advanced electronic applications in high-performance computing (HPC), artificial intelligence (AI), 5th / 6th generation mobile communication technology (5G / 6G), and electric vehicle markets. Embedding active components and / or passive components can reduce the package thickness, but it is very challenging to build fine-pitch redistribution layers (RDL) on embedded components.
[0003] Embedded structures, such as Figure 1 The Advanced Embedded Active System Integration (a-EASI) 1 (fanning out signals through RDL 4), Semiconductor Embedded in SUBstrate (SESUB) 2, Figure 3 The system-level package (SIP) 3 shown in the figure embeds active components and / or passive components in the substrate, which can reduce the package thickness. The fan-out RDL is finally constructed directly on the substrate. The line width and pitch of the traces in the RDL cannot be fine, and the yield also faces huge challenges. In addition, if a fine-pitch RDL is directly constructed on the embedded structure, the difference in the coefficient of thermal expansion (CTE) between the filling material and the active components or / and passive components in the embedded structure will cause the embedded structure to warp, making it more difficult to construct the RDL. Utility Model Content
[0004] In view of the problems existing in the related art, the purpose of the present invention is to provide a semiconductor package to at least improve the performance of the semiconductor package.
[0005] To achieve the above-mentioned purpose, the utility model provides a semiconductor package, comprising: a substrate; a first redistribution layer, arranged on the substrate; a first electronic component, arranged between the substrate and the first redistribution layer; the first redistribution layer comprises a first conductive column extending toward the substrate and electrically connected to the substrate, the first conductive column overlaps with the first electronic component in the lateral direction.
[0006] In some embodiments, the semiconductor package further includes: a first bottom filling layer located between the first redistribution layer and the substrate and covering the first electronic component.
[0007] In some embodiments, the semiconductor package further includes: a first solder located between the first conductive column and the substrate, and a first bottom filling layer covering the first conductive column and the first solder.
[0008] In some embodiments, the first underfill layer covers a surface of the first electronic component facing the first redistribution layer.
[0009] In some embodiments, the first underfill layer has a curved surface.
[0010] In some embodiments, the semiconductor package further includes: a second bottom filling layer, the first electronic component is electrically connected to the substrate, and the second bottom filling layer is located between the first electronic component and the substrate and covers the connection point between the first electronic component and the substrate.
[0011] In some embodiments, the first underfill layer covers the second underfill layer.
[0012] In some embodiments, the first underfill layer covers a surface of the first electronic component that faces the substrate.
[0013] In some embodiments, the semiconductor package further includes: a passive component disposed on the substrate, wherein the passive component is located outside the first bottom filling layer.
[0014] In some embodiments, the semiconductor package further includes: a second bottom filling layer, the first electronic component is electrically connected to the first redistribution layer, the second bottom filling layer is located between the first electronic component and the first redistribution layer and covers the connection point between the first electronic component and the first redistribution layer.
[0015] In some embodiments, the first underfill layer covers the second underfill layer.
[0016] In some embodiments, the semiconductor package further includes: a second electronic component disposed above the first redistribution layer.
[0017] In some embodiments, the second electronic component is electrically connected to the first electronic component through the first conductive pillar.
[0018] In some embodiments, the semiconductor package further includes: a third electronic component disposed between the substrate and the first redistribution layer, and the first conductive pillar overlaps the third electronic component in a lateral direction.
[0019] In some embodiments, the semiconductor package also includes: a second redistribution layer, arranged on the substrate side by side with the first redistribution layer; a third electronic component, arranged between the substrate and the second redistribution layer; the second redistribution layer includes a second conductive column extending toward the substrate and electrically connected to the substrate, and the second conductive column overlaps with the third electronic component laterally.
[0020] In some embodiments, the semiconductor package further includes: a third bottom filling layer located between the second redistribution layer and the substrate and covering the third electronic component.
[0021] In some embodiments, the semiconductor package further includes: a second solder located between the second conductive pillar and the substrate, and a third bottom filling layer covers the second conductive pillar and the second solder.
[0022] An embodiment of the present application also provides a semiconductor package, comprising: a substrate; a first redistribution layer, arranged on the substrate; a first electronic component, a third electronic component and a passive component, arranged side by side between the substrate and the first redistribution layer, and the passive component is located between the first electronic component and the third electronic component; the first redistribution layer comprises a first conductive column and a second conductive column extending toward the substrate and electrically connected to the substrate, and the first conductive column and the second conductive column are respectively arranged around the first electronic component and the third electronic component.
[0023] In some embodiments, the first electronic component and the third electronic component are directly connected to the first redistribution layer.
[0024] In some embodiments, the passive element is located between the first conductive pillar and the second conductive pillar.
[0025] The beneficial technical effects of the utility model are:
[0026] An embodiment of the present application provides a fan-out embedded structure, wherein a first redistribution layer includes a first conductive column to match the thickness of a first electronic component, thereby avoiding the problem that the first redistribution layer is damaged by collision with the first electronic component. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 Shown is the state of the art advanced embedded active system integration.
[0028] Figure 2 A semiconductor built into a substrate in the prior art is shown.
[0029] Figure 3 A prior art system-in-package is shown.
[0030] Figure 4 and Figure 5 The production of the first redistribution layer and the second redistribution layer are shown respectively.
[0031] Figure 6 and Figure 7 The forming of the first solder and the second solder are shown respectively.
[0032] Figure 8 Bonding of a first electronic component to a substrate is shown.
[0033] Fig. 9The formation of a first underfill layer and a third underfill layer is shown.
[0034] Fig.10 Shows the Fig. 9 The resulting structure after carrier removal is shown.
[0035] Fig.11 It is shown that the second electronic component is bonded to the first redistribution layer, and the fourth electronic component is bonded to the second redistribution layer.
[0036] Fig.12 The formation of a fifth underfill layer and a sixth underfill layer is shown.
[0037] Fig.13 A semiconductor package according to a first embodiment of the present application is shown.
[0038] Fig.14 and Fig.15 The production of the first redistribution layer and the second redistribution layer are shown respectively.
[0039] Fig.16 and Fig.17 The forming of the first solder and the second solder are shown respectively.
[0040] Fig.18 Shows the Fig.16 , Fig.17 The structure shown, passive components are bonded to the substrate.
[0041] Fig.19 The formation of an underfill layer is shown.
[0042] Fig. 20 Shows the Fig.19 The resulting structure after carrier removal is shown.
[0043] Fig.21 It is shown that a first underfill layer and a third underfill layer are obtained.
[0044] Fig. 22 The formation of a fifth underfill layer and a sixth underfill layer is shown.
[0045] Fig.23 A semiconductor package according to a second embodiment of the present application is shown.
[0046] Fig.24 The fabrication of a first redistribution layer is shown.
[0047] Fig.25 The forming of the first solder and the second solder is shown.
[0048] Fig.26 Shows the Fig.25 The structure shown, passive components are bonded to substrate 10 .
[0049] Fig. 27 The formation of a first underfill layer is shown.
[0050] Fig.28 Shows the Fig. 27 The resulting structure after carrier removal is shown.
[0051] Fig.29 Bonding a second electronic component to the first redistribution layer is shown.
[0052] Fig.30 The formation of a fifth underfill layer is shown.
[0053] Fig.31 A semiconductor package according to a third embodiment of the present application is shown.
[0054] Fig.32 The fabrication of a first redistribution layer is shown.
[0055] Fig.33 The formation of a first solder is shown to bond a first electronic component to a first redistribution layer.
[0056] Fig.34 Shows the Fig.33 Structure shown, passive components bonded to substrate.
[0057] Fig.35 The formation of a first underfill layer is shown.
[0058] Fig.36 It is shown that the second electronic component and the fourth electronic component are bonded to the first redistribution layer.
[0059] Fig.37 The formation of a fifth underfill layer is shown.
[0060] Fig.38 A semiconductor package according to a fourth embodiment of the present application is shown.
[0061] Fig.39 The fabrication of a first redistribution layer is shown.
[0062] Fig.40 It shows forming a first solder to bond the first electronic component and the third electronic component to the first redistribution layer.
[0063] Fig.41 Shows the Fig.40 Structure shown, passive components bonded to substrate.
[0064] Fig.42 The formation of a first underfill layer is shown.
[0065] Fig.43 Shows the Fig.42 The resulting structure after carrier removal is shown.
[0066] Fig.44 It is shown that the second electronic component, the fifth electronic component, and the fourth electronic component are bonded to the first redistribution layer.
[0067] Fig.45 The formation of a fifth underfill layer is shown.
[0068] Fig.46 A semiconductor package according to a fifth embodiment of the present application is shown.
[0069] Fig.47 The fabrication of a first redistribution layer is shown.
[0070] Fig.48 It shows forming a first solder and bonding a first electronic component to a first redistribution layer.
[0071] Fig.49 Shows the Fig.48 In the structure shown, the passive components are flip-bonded to the substrate.
[0072] Fig.50 The formation of a first underfill layer is shown.
[0073] Fig.51 Will Fig.50 The resulting structure after carrier removal is shown.
[0074] Fig.52 Bonding a second electronic component to the first redistribution layer is shown.
[0075] Fig.53 The formation of a fifth underfill layer is shown.
[0076] Fig.54 A semiconductor package according to a sixth embodiment of the present application is shown. DETAILED DESCRIPTION
[0077] In order to better understand the spirit of the embodiments of the present application, some preferred embodiments of the present application are further described below.
[0078] The embodiments of the present application will be described in detail below. In the full text of the present application specification, the same or similar components and components with the same or similar functions are represented by similar reference numerals. The embodiments of the accompanying drawings described herein are illustrative, graphical, and are used to provide a basic understanding of the present application. The embodiments of the present application should not be interpreted as limiting the present application.
[0079] As used herein, the terms "substantially," "substantially," "essentially," and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms may refer to instances where the event or circumstance occurred precisely as well as instances where the event or circumstance occurred very approximately.
[0080] In this specification, unless otherwise specified or limited, relative terms such as "central", "longitudinal", "lateral", "front", "rear", "right", "left", "inner", "outer", "lower", "higher", "horizontal", "vertical", "above", "below", "above", "below", "top", "bottom" and their derivative terms (such as "horizontally", "downwardly", "upwardly", etc.) should be interpreted as referring to the directions described in the discussion or depicted in the drawings. These relative terms are only used for convenience of description and do not require that the present application be constructed or operated in a specific direction.
[0081] For convenience of description, “first”, “second”, “third”, etc. may be used herein to distinguish different components in one figure or a series of figures. “First”, “second”, “third”, etc. are not intended to describe the corresponding components.
[0082] Figures 4 to 13 The manufacturing process of the semiconductor package 100 according to the first embodiment of the present application is shown.
[0083] See also Figure 4 and Figure 5 , a first redistribution layer 21 and a second redistribution layer 22 are respectively fabricated on a first carrier 101 and a second carrier 102. In some embodiments, the material of the first carrier 101 and the second carrier 102 is silicon. Compared with directly constructing a redistribution layer on a substrate, fabricating a redistribution layer on a carrier can achieve a finer line width / line spacing (L / S), for example, 1 μm / 1 μm. The first redistribution layer 21 and the second redistribution layer 22 respectively include a first conductive pillar 41 and a second conductive pillar 42 extending upward.
[0084] See also Figure 6 and Figure 7 , respectively forming a first solder 61 and a second solder 62 on top of the first conductive pillar 41 and the second conductive pillar 42. The third electronic component 33 is bonded to the second redistribution layer 22, and a fourth underfill layer 54 is used to cover the connection point between the third electronic component 33 and the second redistribution layer 22. In some embodiments, the third electronic component 33 is an active component, such as a semiconductor die.
[0085] See also Figure 8, the first electronic component 31 is bonded to the substrate 10, and a second underfill layer 52 is used to cover the connection point between the first electronic component 31 and the substrate 10. In some embodiments, the first electronic component 31 is an active component, such as a semiconductor die. Figure 6 , Figure 7 The structure shown is invertedly bonded to the substrate 10, the first conductive pillar 41 surrounds the first electronic component 31, and the second conductive pillar 42 surrounds the third electronic component 33. The passive component 60 is disposed on the top surface of the substrate 10, and the passive component 60 is located around the substrate 10 and outside the first conductive pillar 41 and the second conductive pillar 42. The passive component 60 is, for example, a capacitor, an inductor, and a resistor.
[0086] See also Fig. 9 For example, a first bottom filling layer 51 and a third bottom filling layer 53 are formed by dispensing and are located between the first redistribution layer 21 and the substrate 10 and between the second redistribution layer 22 and the substrate 10, respectively. The first bottom filling layer 51 covers the first electronic component 31 and the first conductive column 41, and the third bottom filling layer 53 covers the third electronic component 33 and the second conductive column 42.
[0087] Will Fig. 9 The first carrier 101 and the second carrier 102 are removed to obtain Fig.10 The structure shown.
[0088] See also Fig.11 , the second electronic component 32 is bonded to the first redistribution layer 21, and the fourth electronic component 34 is bonded to the second redistribution layer 22. In some embodiments, the second electronic component 32 and the fourth electronic component 34 are active components, such as semiconductor dies.
[0089] See also Fig.12 For example, a fifth bottom filling layer 55 covering the connection point between the second electronic component 32 and the first redistribution layer 21 and a sixth bottom filling layer 56 covering the connection point between the fourth electronic component 34 and the second redistribution layer 22 are formed by dispensing.
[0090] See also Fig.13 , use the packaging layer 70 to cover all structures on the substrate 10, and then form solder balls 63 through a solder ball bond placement (SBBP) process. So far, the manufacturing of the semiconductor package 100 of the first embodiment of the present application is completed. Fig.13 A single semiconductor package 100 is shown. In actual production, multiple semiconductor packages 100 connected laterally are manufactured together. Fig.13 After the steps shown, a singulation process (such as dicing) is performed to obtain Fig.13The singulated semiconductor package 100 is shown. In the first embodiment, active elements are embedded between the first redistribution layer 21 , the second redistribution layer 22 and the substrate 10 .
[0091] Figures 14 to 23 The manufacturing process of the semiconductor package 100 according to the second embodiment of the present application is shown.
[0092] See also Fig.14 and Fig.15 , a first redistribution layer 21 and a second redistribution layer 22 are respectively fabricated on a first carrier 101 and a second carrier 102. In some embodiments, the material of the first carrier 101 and the second carrier 102 is silicon. Compared with directly constructing a redistribution layer on a substrate, fabricating a redistribution layer on a carrier can achieve a finer line width / line spacing (L / S), for example, 1 μm / 1 μm. The first redistribution layer 21 and the second redistribution layer 22 respectively include a first conductive pillar 41 and a second conductive pillar 42 extending upward.
[0093] See also Fig.16 and Fig.17 A first solder 61 and a second solder 62 are formed on the top of the first conductive pillar 41 and the second conductive pillar 42 respectively. The passive element 60 is bonded to the second redistribution layer 22 , and the second conductive pillar 42 surrounds the passive element 60 .
[0094] See also Fig.18 , the passive element 60 is bonded to the substrate 10. Fig.16 , Fig.17 The structure shown is invertedly bonded to the substrate 10. In the second embodiment, the passive element 60 is disposed between the substrate 10 and the first and second redistribution layers 21 and 22. There is no need to dispose passive elements around the substrate 10, which can reduce the lateral size of the final structure.
[0095] See also Fig.19 For example, a bottom filling layer 50 is formed between the first redistribution layer 21 , the second redistribution layer 22 and the substrate 10 by dispensing, and the bottom filling layer 50 covers the passive component 60 and the first conductive column 41 , and the second conductive column 42 .
[0096] Will Fig.19 The first carrier 101 and the second carrier 102 are removed to obtain Fig. 20 The structure shown.
[0097] See also Fig.21, the bottom filling layer 50 is disconnected from between the first redistribution layer 21 and the second redistribution layer 22, so as to obtain the first bottom filling layer 51 and the third bottom filling layer 53 respectively located between the first redistribution layer 21 and the substrate 10 and between the second redistribution layer 22 and the substrate 10. The second electronic component 32 is bonded to the first redistribution layer 21, and the fourth electronic component 34 is bonded to the second redistribution layer 22. In some embodiments, the second electronic component 32 and the fourth electronic component 34 are active components, such as semiconductor dies.
[0098] See also Fig. 22 For example, a fifth bottom filling layer 55 covering the connection point between the second electronic component 32 and the first redistribution layer 21 and a sixth bottom filling layer 56 covering the connection point between the fourth electronic component 34 and the second redistribution layer 22 are formed by dispensing.
[0099] See also Fig.23 , use the packaging layer 70 to cover all structures on the substrate 10, and then form solder balls 63 through a solder ball bond placement (SBBP) process. So far, the manufacturing of the semiconductor package 100 of the second embodiment of the present application is completed. Fig.23 A single semiconductor package 100 is shown. In actual production, multiple semiconductor packages 100 connected laterally are manufactured together. Fig.23 After the steps shown, a singulation process (such as dicing) is performed to obtain Fig.23 The singulated semiconductor package 100 is shown. In the second embodiment, passive components are embedded between the first redistribution layer 21 , the second redistribution layer 22 and the substrate 10 .
[0100] Figures 24 to 31 The manufacturing process of the semiconductor package 100 according to the third embodiment of the present application is shown.
[0101] See also Fig.24 , a first redistribution layer 21 is fabricated on a first carrier 101. In some embodiments, the material of the first carrier 101 is silicon. Compared with directly constructing a redistribution layer on a substrate, fabricating a redistribution layer on a carrier can achieve a finer line width / line spacing (L / S), for example, 1 μm / 1 μm. The first redistribution layer 21 includes a first conductive pillar 41 and a second conductive pillar 42 extending upward.
[0102] See also Fig.25, respectively forming a first solder 61 and a second solder 62 on the top of the first conductive pillar 41 and the second conductive pillar 42. The first electronic component 31 and the third electronic component 33 are bonded to the first redistribution layer 21, and a second underfill layer 52 is used to cover the connection point between the first electronic component 31 and the first redistribution layer 21, and a fourth underfill layer 54 is used to cover the connection point between the third electronic component 33 and the first redistribution layer 21. In some embodiments, the first electronic component 31 and the third electronic component 33 are active components, such as semiconductor dies.
[0103] See also Fig.26 ,Will Fig.25 The structure shown is invertedly bonded to the substrate 10. A passive element 60 is disposed on the top surface of the substrate 10. The passive element 60 is located around the substrate 10 and outside the first conductive column 41 and the second conductive column 42. The passive element 60 is, for example, a capacitor, an inductor, or a resistor.
[0104] See also Fig. 27 For example, a first bottom filling layer 51 is formed between the first redistribution layer 21 and the substrate 10 by dispensing, and the first bottom filling layer 51 covers the first electronic component 31 , the third electronic component 33 , the first conductive column 41 , and the second conductive column 42 .
[0105] Will Fig. 27 The first carrier 101 shown is removed, resulting in Fig.28 The structure shown.
[0106] See also Fig.29 , the second electronic component 32 is bonded to the first redistribution layer 21. In some embodiments, the second electronic component 32 is an active component, such as a semiconductor die.
[0107] See also Fig.30 For example, a fifth bottom filling layer 55 covering the connection point between the second electronic component 32 and the first redistribution layer 21 is formed by dispensing.
[0108] See also Fig.31 , use the packaging layer 70 to cover all structures on the substrate 10, and then form solder balls 63 through a solder ball bond placement (SBBP) process. So far, the manufacturing of the semiconductor package 100 of the third embodiment of the present application is completed. Fig.31 A single semiconductor package 100 is shown. In actual production, multiple semiconductor packages 100 connected laterally are manufactured together. Fig.31 After the steps shown, a singulation process (such as dicing) is performed to obtain Fig.31The singulated semiconductor package 100 is shown. In the third embodiment, a system of active components and passive components is embedded between the first redistribution layer 21 and the substrate 10 .
[0109] Figure 32 to Figure 38 The manufacturing process of the semiconductor package 100 according to the fourth embodiment of the present application is shown.
[0110] See also Fig.32 , a first redistribution layer 21 is fabricated on a first carrier 101. In some embodiments, the material of the first carrier 101 is silicon. Compared with directly constructing a redistribution layer on a substrate, fabricating a redistribution layer on a carrier can achieve a finer line width / line spacing (L / S), for example, 1 μm / 1 μm. The first redistribution layer 21 includes a first conductive column 41 extending upward.
[0111] See also Fig.33 , a first solder 61 is formed on the top of the first conductive column 41. The first electronic component 31 is bonded to the first redistribution layer 21, and a second underfill layer 52 is used to cover the connection point between the first electronic component 31 and the first redistribution layer 21. In some embodiments, the first electronic component 31 is an active component, such as a semiconductor die.
[0112] See also Fig.34 ,Will Fig.33 The structure shown is invertedly bonded to the substrate 10. A passive element 60 is disposed on the top surface of the substrate 10. The passive element 60 is located around the substrate 10 and outside the first conductive column 41. The passive element 60 is, for example, a capacitor, an inductor, or a resistor.
[0113] See also Fig.35 For example, a first bottom filling layer 51 is formed between the first redistribution layer 21 and the substrate 10 by dispensing, and the first bottom filling layer 51 covers the first electronic component 31 and the first conductive column 41. Fig.34 The first carrier 101 is shown removed.
[0114] See also Fig.36 , the second electronic component 32 and the fourth electronic component 34 are bonded to the first redistribution layer 21. In some embodiments, the second electronic component 32 and the fourth electronic component 34 are active components, such as semiconductor dies.
[0115] See also Fig.37 For example, a fifth bottom filling layer 55 covering the connection points of the second electronic component 32 , the fourth electronic component 34 and the first redistribution layer 21 is formed by dispensing.
[0116] See also Fig.38, use the packaging layer 70 to cover all structures on the substrate 10, and then form solder balls 63 through a solder ball bond placement (SBBP) process. So far, the manufacturing of the semiconductor package 100 of the fourth embodiment of the present application is completed. Fig.38 A single semiconductor package 100 is shown. In actual production, multiple semiconductor packages 100 connected laterally are manufactured together. Fig.38 After the steps shown, a singulation process (such as dicing) is performed to obtain Fig.38 The singulated semiconductor package 100 is shown. Compared with the first to third embodiments, the first redistribution layer 21 of the fourth embodiment has more dielectric layers and metal lines, and the first electronic component 31 is wider, so that the first electronic component 31 can be used as a bridge component between the second electronic component 32 and the fourth electronic component 34.
[0117] Figures 39 to 46 The manufacturing process of the semiconductor package 100 according to the fifth embodiment of the present application is shown.
[0118] See also Fig.39 , a first redistribution layer 21 is fabricated on a first carrier 101. In some embodiments, the material of the first carrier 101 is silicon. Compared with directly constructing a redistribution layer on a substrate, fabricating a redistribution layer on a carrier can achieve a finer line width / line spacing (L / S), for example, 1 μm / 1 μm. The first redistribution layer 21 includes a first conductive column 41 extending upward.
[0119] See also Fig.40 , forming a first solder 61 on the top of the first conductive column 41. The first electronic component 31 and the third electronic component 33 are bonded to the first redistribution layer 21, and the connection point between the first electronic component 31 and the first redistribution layer 21 is covered with a second underfill layer 52, and the connection point between the third electronic component 33 and the first redistribution layer 21 is covered with a fourth underfill layer 54. In some embodiments, the first electronic component 31 and the third electronic component 33 are active components, such as semiconductor dies; or passive components, such as capacitors, inductors, and resistors.
[0120] See also Fig.41 ,Will Fig.40 The structure shown is invertedly bonded to the substrate 10. A passive element 60 is disposed on the top surface of the substrate 10. The passive element 60 is located around the substrate 10 and outside the first conductive column 41. The passive element 60 is, for example, a capacitor, an inductor, or a resistor.
[0121] See also Fig.42For example, a first bottom filling layer 51 is formed between the first redistribution layer 21 and the substrate 10 by dispensing, and the first bottom filling layer 51 covers the first electronic component 31 , the third electronic component 33 and the first conductive column 41 .
[0122] Will Fig.42 The first carrier 101 shown is removed, resulting in Fig.43 The structure shown.
[0123] See also Fig.44 , the second electronic component 32, the fifth electronic component 35, and the fourth electronic component 34 are bonded to the first redistribution layer 21. In some embodiments, the second electronic component 32, the fifth electronic component 35, and the fourth electronic component 34 are active components, such as semiconductor dies.
[0124] See also Fig.45 For example, a fifth bottom filling layer 55 covering the connection points among the second electronic component 32 , the fifth electronic component 35 , the fourth electronic component 34 and the first redistribution layer 21 is formed by dispensing.
[0125] See also Fig.46 , use the packaging layer 70 to cover all structures on the substrate 10, and then form solder balls 63 through a solder ball bond placement (SBBP) process. So far, the manufacturing of the semiconductor package 100 of the fifth embodiment of the present application is completed. Fig.46 A single semiconductor package 100 is shown. In actual production, multiple semiconductor packages 100 connected laterally are manufactured together. Fig.46 After the steps shown, a singulation process (such as dicing) is performed to obtain Fig.46 The singulated semiconductor package 100 is shown. In the fourth embodiment, the first electronic component 31 can be used as a bridge element between the second electronic component 32 and the fifth electronic component 35 , and the third electronic component 33 can be used as a bridge element between the fifth electronic component 35 and the fourth electronic component 34 .
[0126] Figures 47 to 54 The manufacturing process of the semiconductor package 100 according to the sixth embodiment of the present application is shown.
[0127] See also Fig.47 , a first redistribution layer 21 is fabricated on a first carrier 101. In some embodiments, the material of the first carrier 101 is silicon. Compared with directly constructing a redistribution layer on a substrate, fabricating a redistribution layer on a carrier can achieve a finer line width / line spacing (L / S), for example, 1 μm / 1 μm. The first redistribution layer 21 includes a first conductive column 41 extending upward.
[0128] See also Fig.48 , a first solder 61 is formed on the top of the first conductive pillar 41. The first electronic component 31 is bonded to the first redistribution layer 21, and a second underfill layer 52 is used to cover the connection point between the first electronic component 31 and the first redistribution layer 21. In some embodiments, the first electronic component 31 is a radio frequency (RF) die, and the first conductive pillar 41 includes a metal material and surrounds the first electronic component 31 to shield the first electronic component 31 from noise.
[0129] See also Fig.49 ,Will Fig.48 The structure shown is invertedly bonded to the substrate 10. Passive components 60 are disposed on the top surface of the substrate 10. The passive components 60 are located around the substrate 10 and outside the first redistribution layer 21. The passive components 60 are capacitors, inductors, and resistors, for example.
[0130] See also Fig.50 For example, a first bottom filling layer 51 is formed between the first redistribution layer 21 and the substrate 10 by dispensing, and the first bottom filling layer 51 covers the first electronic component 31 and the first conductive column 41 .
[0131] Will Fig.50 The first carrier 101 shown is removed, resulting in Fig.51 The structure shown.
[0132] See also Fig.52 , the second electronic component 32 is bonded to the first redistribution layer 21. In some embodiments, the second electronic component 32 is an active component, such as a semiconductor die.
[0133] See also Fig.53 For example, a fifth bottom filling layer 55 covering the connection point between the second electronic component 32 and the first redistribution layer 21 is formed by dispensing.
[0134] See also Fig.54 , use the packaging layer 70 to cover all structures on the substrate 10, and then form solder balls 63 through a solder ball bond placement (SBBP) process. So far, the manufacture of the semiconductor package 100 of the sixth embodiment of the present application is completed. Fig.54 A single semiconductor package 100 is shown. In actual production, multiple semiconductor packages 100 connected laterally are manufactured together. Fig.54 After the steps shown, a singulation process (such as dicing) is performed to obtain Fig.54The monolithic semiconductor package 100 is shown. In the sixth embodiment, the metal line in the portion of the first redistribution layer 21 located outside the first conductive column 41 is used as an antenna component, and the metal line with a fine line width and line spacing is used as the antenna component, and the first conductive column 41 surrounds the first electronic component 31 to shield noise, so that the antenna can achieve a higher frequency (for example, a frequency range of 200-300GHz) and a more precise effect.
[0135] An embodiment of the present application provides a fan-out embedding method, which relates to a fan-out chip last package (FOCLP), which can be used in electronic applications such as HPC, AI, 5G / 6G, and electric vehicles.
[0136] The embodiments of the present application solve the problem in the prior art that directly building the RDL on the embedded substrate increases the difficulty of building the RDL due to the warping of the embedded substrate by indirectly building the RDL and then bonding it to the embedded substrate.
[0137] The embodiments of the present application propose a new structure for embedding components that may be active and / or passive or bridge chips or even antennas or a combination thereof in FO-RDL. Since the FO-RDL is built separately before being bonded to the substrate, there are no trace spacing capabilities or yield challenges. The fan-out chips are also the last to be bonded during assembly, providing all the process and yield advantages of the post-chip process. The embodiments of the present application perfectly combine fan-out RDL technology with embedding technology to provide more advanced packaging for future high-performance electronic applications.
[0138] Referring to the first to sixth embodiments, the present application provides a semiconductor package 100, comprising: a substrate 10; a first redistribution layer 21, disposed on the substrate 10; a first electronic component 31, disposed between the substrate 10 and the first redistribution layer 21; the first redistribution layer 21 comprises a first conductive column 41 extending toward the substrate 10 and electrically connected to the substrate 10, and the first conductive column 41 overlaps the first electronic component 31 in the lateral direction. The embodiment of the present application provides a fan-out embedded structure, the first redistribution layer 21 comprises a first conductive column 41 to match the thickness of the first electronic component 31, and avoids the problem that the first redistribution layer 21 is damaged by the collision of the first electronic component 21.
[0139] In some embodiments, the first conductive pillar 41 is a controlled collapse chip connection (C4) bump.
[0140] In some embodiments, the semiconductor package 100 further includes a first underfill layer 51 located between the first redistribution layer 21 and the substrate 10 and covering the first electronic component 31 .
[0141] In some embodiments, the semiconductor package 100 further includes: a first solder 61 located between the first conductive pillar 41 and the substrate 10 , and a first bottom filling layer 51 covers the first conductive pillar 41 and the first solder 61 .
[0142] In some embodiments, the first underfill layer 51 covers a surface (upper surface) of the first electronic component 31 facing the first redistribution layer 21 .
[0143] In some embodiments, the first underfill layer 51 has a curved surface.
[0144] In some embodiments, the semiconductor package 100 further includes a second bottom filling layer 52 . The first electronic component 31 is electrically connected to the substrate 10 . The second bottom filling layer 52 is located between the first electronic component 31 and the substrate 10 and covers the connection point between the first electronic component 31 and the substrate 10 .
[0145] In some embodiments, the first underfill layer 51 covers the second underfill layer 52 .
[0146] In some embodiments, the first underfill layer 51 covers a surface (lower surface) of the first electronic component 31 that faces the substrate 10 .
[0147] In some embodiments, the semiconductor package 100 further includes: a passive component 60 disposed on the substrate 10 , and the passive component 60 is located outside the first bottom filling layer 51 .
[0148] In some embodiments, the semiconductor package 100 further includes: a second bottom filling layer 52 , the first electronic component 31 is electrically connected to the first redistribution layer 21 , the second bottom filling layer 52 is located between the first electronic component 31 and the first redistribution layer 21 and covers the connection point between the first electronic component 31 and the first redistribution layer 21 .
[0149] In some embodiments, the first underfill layer 51 covers the second underfill layer 52 .
[0150] In some embodiments, the semiconductor package 100 further includes: a second electronic component 32 disposed above the first redistribution layer 21 .
[0151] In some embodiments, the second electronic component 32 is electrically connected to the first electronic component 31 through the first conductive pillar 41 .
[0152] In some embodiments, the semiconductor package 100 further includes: a third electronic component 33 disposed between the substrate 10 and the first redistribution layer 21 , and the first conductive pillar 41 overlaps the third electronic component 33 in a lateral direction.
[0153] In some embodiments, the semiconductor package 100 also includes: a second redistribution layer 22, which is arranged on the substrate 10 side by side with the first redistribution layer 21; a third electronic component 33, which is arranged between the substrate 10 and the second redistribution layer 22; the second redistribution layer 22 includes a second conductive column 42 extending toward the substrate 10 and electrically connected to the substrate 10, and the second conductive column 42 overlaps with the third electronic component 33 in the laterally direction.
[0154] In some embodiments, the semiconductor package 100 further includes a third underfill layer 53 located between the second redistribution layer 22 and the substrate 10 and covering the third electronic component 33 .
[0155] In some embodiments, the semiconductor package 100 further includes: a second solder 62 located between the second conductive pillar 42 and the substrate 10 , and a third bottom filling layer 53 covers the second conductive pillar 42 and the second solder 62 .
[0156] A semiconductor package 100 includes: a substrate 10; a first redistribution layer 21, which is arranged on the substrate 10; a first electronic component 31, a third electronic component 33 and a passive component 60, which are arranged side by side between the substrate 10 and the first redistribution layer 21, and the passive component 60 is located between the first electronic component 31 and the third electronic component 33; the first redistribution layer 21 includes a first conductive column 41 and a second conductive column 42 extending toward the substrate 10 and electrically connected to the substrate 10, and the first conductive column 41 and the second conductive column 42 are respectively arranged around the first electronic component 31 and the third electronic component 33.
[0157] In some embodiments, the first electronic component 31 and the third electronic component 33 are directly connected to the first redistribution layer 21 .
[0158] In some embodiments, the passive element 60 is located between the first conductive pillar 41 and the second conductive pillar 42 .
[0159] The above description is only the preferred embodiment of the utility model, and is not intended to limit the utility model. For those skilled in the art, the utility model can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model shall be included in the protection scope of the utility model.
Claims
1. A semiconductor package, characterized in that: include: substrate; A first redistribution layer is disposed on the substrate; A first electronic component is disposed between the substrate and the first redistribution layer; The first redistribution layer includes a first conductive pillar extending toward the substrate and electrically connected to the substrate, wherein the first conductive pillar overlaps the first electronic component in a lateral direction.
2. The semiconductor package according to claim 1, wherein: Also includes: The first bottom filling layer is located between the first redistribution layer and the substrate and covers the first electronic component.
3. The semiconductor package according to claim 2, wherein: The first underfill layer covers a surface of the first electronic component facing the first redistribution layer.
4. The semiconductor package according to claim 2, wherein: Also includes: A second bottom filling layer, the first electronic component is electrically connected to the substrate, and the second bottom filling layer is located between the first electronic component and the substrate and covers the connection point between the first electronic component and the substrate.
5. The semiconductor package according to claim 4, wherein: The first bottom filling layer covers the second bottom filling layer.
6. The semiconductor package according to claim 2, wherein: The first underfill layer covers a surface of the first electronic component facing the substrate.
7. The semiconductor package according to claim 2, wherein: Also includes: A second bottom filling layer, the first electronic component is electrically connected to the first redistribution layer, the second bottom filling layer is located between the first electronic component and the first redistribution layer and covers a connection point between the first electronic component and the first redistribution layer.
8. The semiconductor package according to claim 7, wherein: The first bottom filling layer covers the second bottom filling layer.
9. The semiconductor package according to claim 1, wherein: Also includes: A second redistribution layer is disposed on the substrate side by side with the first redistribution layer; a third electronic component, disposed between the substrate and the second redistribution layer; The second redistribution layer includes a second conductive pillar extending toward the substrate and electrically connected to the substrate, and the second conductive pillar overlaps the third electronic component in a lateral direction.
10. The semiconductor package according to claim 1, wherein: Also includes: A third electronic component and a passive component are arranged side by side with the first electronic component between the substrate and the first redistribution layer, the first redistribution layer also includes a second conductive column extending toward the substrate and electrically connected to the substrate, the first conductive column and the second conductive column are respectively arranged around the first electronic component and the third electronic component, and the passive component is located between the first conductive column and the second conductive column.