ESD protection circuit and chip

Abstract

The utility model discloses an ESD (Electro-Static Discharge) protection circuit, which comprises a switch unit, a trigger circuit and a clamping circuit, the trigger circuit is connected with an input voltage, the trigger circuit is used for generating a trigger voltage when the input voltage transiently changes, the control end of the switch unit is connected with the trigger circuit to receive the trigger voltage, the first end of the switch unit is connected with the input voltage, and the second end of the switch unit is connected with a reference voltage. The switch unit controls the on-off between the input voltage and the reference voltage based on the trigger voltage, and the clamping circuit is connected with the control end of the switch unit to clamp the voltage of the control end of the switch unit. According to the ESD protection circuit and the chip, the clamping circuit clamps the control end voltage of the switch unit, so that breakdown and damage of the switch unit caused by overhigh trigger voltage are avoided. Meanwhile, the clamping circuit has a grid voltage clamping effect, so that consideration on breakdown prevention of the switch unit can be reduced when values are designed for resistors and capacitors in the trigger circuit, and the circuit design is more flexible and convenient.

Description

Technical Field

[0001] The utility model belongs to the technical field of integrated circuits, and in particular relates to an ESD protection circuit and a chip. Background Art

[0002] Electrostatic discharge (ESD) events of varying degrees will occur during the production, testing, transportation, and use of chips. When an electrostatic discharge event occurs, a large amount of charge will instantly flow into the chip from the outside to the inside. If the chip encounters an electrostatic discharge event or an impact from external electrostatic coupling during operation, the chip system will enter an abnormal state, affecting the normal operation of the chip. By packaging the chip, some static electricity can be prevented from being directly released into the internal circuit of the chip, but the pins of the chip exposed to the outside will still be exposed to the electrostatic environment. In order to prevent static electricity from being released into the internal circuit of the chip through these pins, an ESD protection circuit (electrostatic discharge protection circuit) can be set in the chip, and static electricity can be discharged through the ESD protection circuit to avoid damage to the internal circuit of the chip.

[0003] In the existing ESD protection circuit, commonly used protection devices include diodes, MOS tubes, etc. There are two ways to perform ESD protection through MOS tubes. One method mainly uses the opening of the parasitic triode of the MOS body to discharge the ESD static current, and the other method uses the channel of the MOS tube as a discharge channel. However, using the MOS tube as a protection device has high requirements for its own self-protection ability, otherwise it is easy to break down, so the MOS tube used is often very large, which greatly increases the difficulty of chip design and production.

[0004] Therefore, in view of the above technical problems, it is necessary to provide an ESD protection circuit and chip.

[0005] The information disclosed in this background technology section is only intended to increase the understanding of the overall background of the present invention, and should not be regarded as acknowledging or suggesting in any form that the information constitutes the prior art already known to a person skilled in the art. Utility Model Content

[0006] The utility model aims to provide an ESD protection circuit and chip, which can improve the protection capability and safety of a MOS tube used as a protection device and prevent the MOS tube from being broken down.

[0007] In order to achieve the above-mentioned purpose, a specific embodiment of the utility model provides an ESD protection circuit, including a switch unit, a trigger circuit and a clamping circuit, wherein the trigger circuit is connected to an input voltage, the trigger circuit is used to generate a trigger voltage when the input voltage changes transiently, the control end of the switch unit is connected to the trigger circuit to receive the trigger voltage, the first end of the switch unit is connected to the input voltage, the second end of the switch unit is connected to a reference voltage, the switch unit controls the on and off between the input voltage and the reference voltage based on the trigger voltage, and the clamping circuit is connected to the control end of the switch unit to clamp the voltage of the control end of the switch unit.

[0008] In one or more embodiments of the present invention, the trigger circuit includes a capacitor and a resistor, the first end of the capacitor is connected to the input voltage, the second end of the capacitor and the first end of the resistor are connected to the control end of the switching unit to generate a trigger voltage, and the second end of the resistor is connected to the reference voltage.

[0009] In one or more embodiments of the present invention, the switch unit includes a first transistor.

[0010] In one or more embodiments of the present invention, the clamping circuit includes one or more diodes, which are connected in series to form a diode string, the anode of the diode string is connected to the control end of the switch unit, and the cathode of the diode string is connected to the reference voltage.

[0011] In one or more embodiments of the present invention, the clamping circuit includes one or more second transistors, the control end of the second transistor is connected to the first end, the second transistors are connected in series in sequence and one end is connected to the control end of the switch unit and the other end is connected to the reference voltage.

[0012] In one or more embodiments of the present invention, the clamping circuit includes a voltage regulator diode, a cathode of the voltage regulator diode is connected to the control end of the switch unit, and an anode of the voltage regulator diode is connected to a reference voltage.

[0013] A specific embodiment of the utility model further provides a chip, comprising the above-mentioned ESD protection circuit.

[0014] Compared with the prior art, the ESD protection circuit and chip of the utility model clamps the control terminal voltage of the switch unit through the clamping circuit to prevent the switch unit from being broken down and damaged due to excessive trigger voltage. At the same time, since the clamping circuit has played the role of gate voltage clamping, the consideration of the switch unit's anti-breakdown can be reduced when designing the values ​​of the resistors and capacitors in the trigger circuit, which is more flexible and convenient in circuit design, and is also conducive to increasing the size of the discharge current and improving the overall ESD protection capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the utility model, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 This is a circuit schematic diagram of the ESD protection circuit in the first embodiment of the utility model.

[0017] Figure 2 This is a circuit schematic diagram of the ESD protection circuit in the second embodiment of the present utility model.

[0018] Figure 3 This is a circuit schematic diagram of the ESD protection circuit in the third embodiment of the present utility model. DETAILED DESCRIPTION

[0019] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0020] The words "coupled" or "connected" or "connected" in the specification include both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include connection through other active or passive devices on the basis of achieving the same or similar functional purposes, such as connection through circuits or components such as switches and follower circuits. In addition, in the present utility model, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.

[0021] Embodiment 1

[0022] like Figure 1 As shown, the ESD protection circuit in an embodiment of the present invention includes a switch unit 10 , a trigger circuit 20 and a clamping circuit 30 .

[0023] The trigger circuit 20 is used to generate a trigger voltage when the input voltage Vin changes transiently. The control end of the switch unit 10 is connected to the trigger circuit 20 to receive the trigger voltage, the first end of the switch unit 10 is connected to the input voltage Vin, the second end of the switch unit 10 is connected to the reference voltage, and the switch unit 10 controls the on-off between the input voltage Vin and the reference voltage based on the trigger voltage. The clamp circuit 30 is connected to the control end of the switch unit 10 to clamp the control end voltage of the switch unit 10.

[0024] In one embodiment, the reference voltage is a ground voltage, and the input voltage Vin may come from a circuit in which electrostatic discharge may occur, or may come from a chip pin or pad. In other embodiments, the reference voltage may also be other voltages.

[0025] Specifically, the trigger circuit 20 includes a capacitor C and a resistor R, the first end of the capacitor C is connected to the input voltage Vin, the second end of the capacitor C and the first end of the resistor R are connected to the control end of the switch unit 10, and the second end of the resistor R is connected to the reference voltage.

[0026] The switch unit 10 includes a first transistor M1. A control terminal of the first transistor M1 is connected to the second terminal of the capacitor C to receive a trigger voltage, a first terminal of the first transistor M1 is connected to an input voltage Vin, and a second terminal of the first transistor M1 is connected to a reference voltage.

[0027] In one embodiment, the first transistor M1 is an N-channel MOS transistor, the control end of the first transistor M1 is a gate, the first end of the first transistor M1 is a drain, and the second end of the first transistor M1 is a source. In other embodiments, the first transistor M1 may also be a P-channel MOS transistor or other types of transistors, and the connection method thereof is adaptively adjusted.

[0028] In one embodiment, the clamping circuit 30 includes n diodes D. The n diodes D are connected in series to form a diode string, the anode of the diode string is connected to the control end of the first transistor M1, and the cathode of the diode string is connected to the reference voltage. Wherein, n can be any positive integer, which can be set according to the actual situation in practical applications.

[0029] In actual application scenarios, when an electrostatic discharge event occurs, the input voltage Vin increases rapidly at a speed far exceeding that when the circuit is normally powered on. Based on the frequency characteristics of capacitor C, the impedance of capacitor C is small at this time, and the trigger voltage generated at the second end of capacitor C is quickly pulled up synchronously. When the trigger voltage is greater than the threshold voltage of the first transistor M1, the first transistor M1 is turned on, and a static current discharge channel is formed between the input voltage Vin and the reference voltage, thereby achieving static electricity release.

[0030] When no electrostatic discharge event occurs, even if the input voltage Vin is rising, since the voltage change frequency is lower during normal power-on of the circuit, the impedance of capacitor C is large, the voltage is concentrated on capacitor C, and the trigger voltage generated at the second end of capacitor C is low. Only by adjusting the parameters of capacitor C and resistor R can it be ensured that the trigger voltage is less than the threshold voltage of the first transistor M1 within the normal power-on frequency range, thereby effectively distinguishing the increase in input voltage Vin during electrostatic discharge and normal power-on, and avoiding mis-triggering of the ESD protection.

[0031] When the trigger voltage exceeds the sum of the clamping voltages of n diodes D, n*Vc (assuming the clamping voltage of each diode D is Vc), the diodes D will clamp the control terminal voltage of the first transistor M1 at n*Vc, thereby preventing the first transistor M1 from being broken down and damaged due to too high a trigger voltage.

[0032] At the same time, since the clamping circuit 30 has played the role of gate voltage clamping, when designing and taking values of the resistor R and capacitor C in the trigger circuit 20, the consideration of preventing breakdown of the first transistor M1 can be reduced, which is more flexible and convenient in circuit design, and is also beneficial to increasing the magnitude of the MOS transistor discharge current and improving the overall ESD protection ability.

[0033] In this embodiment, an ESD protection chip is further provided, including the above-mentioned ESD protection circuit.

[0034] Embodiment 2

[0035] As Figure 2 shown, the difference between the ESD protection circuit in this embodiment and that in Embodiment 1 lies only in the structure of the clamping circuit 30.

[0036] Specifically, the clamping circuit 30 includes n second transistors M2. The gates and drains of the second transistors M2 are connected, and the n second transistors M2 are connected in series in sequence, with one end connected to the control terminal of the first transistor M1 and the other end connected to the reference voltage. Among them, n can be any positive integer and can be set according to actual situations in practical applications.

[0037] In one embodiment, the second transistor M2 is an N-channel MOS transistor. The source of the i-th second transistor M2 is connected to the gates and drains of the (i + 1)-th second transistor M2 (i < n). The gates and drains of the first second transistor M2 are connected to the control terminal of the first transistor M1, and the source of the n-th second transistor M2 is connected to the reference voltage. In other embodiments, the second transistor M2 can also be a P-channel MOS transistor or other types of transistors, and their connection methods are adjusted accordingly.

[0038] The structures and functions of the switching unit 10, the trigger circuit 20, and the clamping circuit 30 in this embodiment are the same as those in Embodiment 1.

[0039] By connecting the second transistors M2 in diode connection and connecting them in series, when the trigger voltage exceeds the sum n*Vgs of the clamping voltages of n second transistors M2 (assuming that the clamping voltage of each second transistor M2 is Vgs), the second transistor M2 will clamp the control terminal voltage of the first transistor M1 at n*Vgs, thereby preventing the trigger voltage from being too high and causing the first transistor M1 to break down and be damaged.

[0040] This embodiment also provides an ESD protection chip, including the above-mentioned ESD protection circuit.

[0041] Embodiment 3

[0042] like Figure 3 As shown, the difference between the ESD protection circuit in this embodiment and the first and second embodiments is only the structure of the clamping circuit 30 .

[0043] Specifically, the clamping circuit 30 includes a voltage regulator diode Dz, a cathode of the voltage regulator diode Dz is connected to the control end of the switch unit, and an anode of the voltage regulator diode Dz is connected to the reference voltage.

[0044] The structures and functions of the switch unit 10 , the trigger circuit 20 and the clamp circuit 30 in this embodiment are the same as those in the first embodiment.

[0045] When the trigger voltage exceeds the breakdown voltage Vz of the Zener diode Dz, the Zener diode Dz will clamp the control terminal voltage of the first transistor M1 at Vz, thereby preventing the trigger voltage from being too high and causing the first transistor M1 to break down and be damaged.

[0046] This embodiment also provides an ESD protection chip, including the above-mentioned ESD protection circuit.

[0047] It is obvious to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the embodiments should be regarded as exemplary and non-restrictive from any point of view, and the scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present invention. Any reference numeral in a claim should not be regarded as limiting the claim to which it relates.

[0048] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. An ESD protection circuit, characterized in that: The invention comprises a switch unit, a trigger circuit and a clamp circuit, wherein the trigger circuit is connected to an input voltage, the trigger circuit is used to generate a trigger voltage when the input voltage changes transiently, the control end of the switch unit is connected to the trigger circuit to receive the trigger voltage, the first end of the switch unit is connected to the input voltage, the second end of the switch unit is connected to a reference voltage, the switch unit controls the on-off between the input voltage and the reference voltage based on the trigger voltage, and the clamp circuit is connected to the control end of the switch unit to clamp the voltage of the control end of the switch unit.

2. The ESD protection circuit according to claim 1, characterized in that: The trigger circuit includes a capacitor and a resistor, the first end of the capacitor is connected to the input voltage, the second end of the capacitor and the first end of the resistor are connected to the control end of the switch unit to generate a trigger voltage, and the second end of the resistor is connected to the reference voltage.

3. The ESD protection circuit according to claim 1, characterized in that: The switch unit includes a first transistor.

4. The ESD protection circuit according to claim 1, characterized in that: The clamping circuit includes one or more diodes, which are connected in series in sequence to form a diode string, an anode of the diode string is connected to the control end of the switch unit, and a cathode of the diode string is connected to a reference voltage.

5. The ESD protection circuit according to claim 1, characterized in that: The clamp circuit includes one or more second transistors, the control end of the second transistor is connected to the first end, the second transistors are connected in series in sequence and one end is connected to the control end of the switch unit and the other end is connected to the reference voltage.

6. The ESD protection circuit according to claim 1, characterized in that: The clamping circuit comprises a voltage stabilizing diode, a cathode of the voltage stabilizing diode is connected to the control end of the switch unit, and an anode of the voltage stabilizing diode is connected to a reference voltage.

7. A chip, characterized in that: The invention comprises the ESD protection circuit according to any one of claims 1 to 6.

Images