Filter, inverter and energy storage device

Abstract

The utility model provides a filter, an inverter and an energy storage device. The filter is applied to an inverter circuit, the input side of the inverter circuit is connected with a direct-current bus, and the output side of the inverter circuit is connected with a power grid through a grid-connected port. The filter comprises a harmonic filter circuit, a filter magnetic ring, a common-mode inductor, a common-mode magnetic ring, a differential-mode magnetic ring, a differential-mode capacitor and a common-mode capacitor. In the harmonic filter circuit, a filter inductor is connected between the output side of the inverter circuit and the grid-connected port and is further connected with a filter capacitor, and the filter inductor is further connected with a filter magnetic ring in series. The common-mode inductor is connected in series to one end, close to the grid-connected port, of the filter inductor, and the common-mode magnetic ring and the differential-mode magnetic ring are connected in series between the common-mode inductor and the grid-connected port. The filter inductor, the filter capacitor, the common-mode inductor, the output side of the inverter circuit and the grid-connected port are respectively grounded through the corresponding common-mode capacitors, and the grid-connected port is also connected with the differential-mode capacitor. The filter provided by the utility model can effectively suppress conduction and radiation interference at the grid-connected side of the inverter.

Description

Technical Field

[0001] The present application relates to the field of filtering technology, and in particular to a filter, an inverter and an energy storage device. Background Art

[0002] When grid-connected inverters convert direct current into alternating current, they generate electromagnetic interference (EMI), which pollutes the power grid. Electromagnetic interference can also propagate in the power grid, interfering with other devices. In order to reduce the impact of grid-connected inverters on the power grid, in the restrictions on inverter grid-connected conditions in various countries and industries, the grid-connected side conducted (CE) interference (including common-mode interference and differential-mode interference) and radiated (RE) interference in electromagnetic interference are the focus of monitoring. Therefore, how to effectively suppress the grid-connected side conducted and radiated interference is a technical problem that needs to be solved at present. Utility Model Content

[0003] In view of this, the present application provides a filter, an inverter and an energy storage device, which can effectively suppress the conducted and radiated interference on the grid-connected side of the inverter.

[0004] The first aspect of the present application provides a filter, which is applied to an inverter circuit, wherein the input side of the inverter circuit is connected to a DC bus, and the output side of the inverter circuit is connected to a power grid through a grid-connected port. The filter includes: a harmonic filter circuit, a filter magnetic ring, a common-mode inductor, a common-mode magnetic ring, a differential-mode magnetic ring, a differential-mode capacitor, and a common-mode capacitor; wherein the harmonic filter circuit includes a filter inductor and a filter capacitor, the filter inductor is connected between the output side of the inverter circuit and the grid-connected port and is also connected to the filter capacitor, and the filter inductor is also connected in series with the filter magnetic ring; the common-mode inductor is connected in series at one end of the filter inductor close to the grid-connected port, and the common-mode magnetic ring and the differential-mode magnetic ring are connected in series between the common-mode inductor and the grid-connected port; the filter inductor, the filter capacitor, the common-mode inductor, the output side of the inverter circuit, and the grid-connected port are grounded through corresponding common-mode capacitors, and the grid-connected port is connected to the differential-mode capacitor.

[0005] In one embodiment, the output side of the inverter circuit includes three phase line output terminals, the grid-connected port has three phase line terminals and one neutral line terminal, the three phase line terminals are connected to the three phase line output terminals one by one, and are connected to the three-phase phase lines of the power grid one by one, and the neutral line terminal is connected to the neutral line of the power grid; the harmonic filter circuit includes three filter inductors and three filter capacitors, each filter inductor is connected between a phase line output terminal of the inverter circuit and a corresponding phase line terminal of the grid-connected port, and the three filter inductors are also connected through corresponding filter capacitors; each phase line output terminal is grounded through a corresponding common-mode capacitor, and each phase line terminal and the neutral line terminal are connected through a corresponding differential-mode capacitor.

[0006] In one embodiment, the output side of the inverter circuit includes two output terminals, the grid-connected port has a phase line terminal and a neutral line terminal, the two output terminals are connected to the phase line terminal and the neutral line terminal in a one-to-one correspondence, the phase line terminal is connected to a phase line of a phase of the power grid, and the neutral line terminal is connected to the neutral line of the power grid; the harmonic filter circuit includes two filter inductors and two filter capacitors, one of the filter inductors is connected between one of the output terminals of the inverter circuit and the phase line terminal, and the other filter inductor is connected between the other output terminal of the inverter circuit and the neutral line terminal, and the two filter inductors are also connected through corresponding filter capacitors respectively; the phase line output terminal and the neutral line output terminal are grounded through corresponding common-mode capacitors respectively, and the phase line terminal and the neutral line terminal are connected through differential-mode capacitors.

[0007] In one embodiment, the harmonic filter circuit also includes a power frequency inductor, the filter inductor, the common mode inductor and the power frequency inductor are connected in series in sequence, the filter capacitor is connected between the filter inductor and the power frequency inductor, and the power frequency inductor is grounded through the corresponding common mode capacitor.

[0008] In one embodiment, the filter magnetic ring includes at least one of a first magnetic ring, a second magnetic ring and a third magnetic ring. The first magnetic ring and the second magnetic ring are connected in series at one end of the filter inductor close to the inverter circuit, and the third magnetic ring is connected in series at one end of the filter inductor away from the inverter circuit. The first magnetic ring, the second magnetic ring and the third magnetic ring are all common mode magnetic rings and act on different frequency bands respectively.

[0009] In one embodiment, one of the first magnetic ring, the second magnetic ring and the third magnetic ring is an amorphous nano magnetic ring, and the other two of the first magnetic ring, the second magnetic ring and the third magnetic ring are manganese zinc ferrite magnetic rings and nickel zinc ferrite magnetic rings respectively; the differential mode magnetic ring is an aluminum sendust magnetic ring.

[0010] In one embodiment, the common mode capacitor includes a main capacitor and an auxiliary capacitor, the main capacitor and the auxiliary capacitor are connected in parallel, and the capacitance value of the main capacitor is greater than the capacitance value of the auxiliary capacitor.

[0011] In one embodiment, each filter inductor is connected in series with the same filter magnetic ring; or each filter inductor is connected in series with different filter magnetic rings.

[0012] In one embodiment, each output end of the common-mode inductor is connected in series to a corresponding terminal of the grid-connected port through the same common-mode magnetic ring and the same differential-mode magnetic ring, or each output end of the common-mode inductor is connected in series to a corresponding terminal of the grid-connected port through different common-mode magnetic rings and different differential-mode magnetic rings.

[0013] The second aspect of the present application provides an inverter, which includes: an inverter circuit, a grid-connected port and a filter; the input side of the inverter circuit is connected to a DC bus, and the output side of the inverter circuit is connected to the grid through the grid-connected port; the filter includes a harmonic filter circuit, a filter magnetic ring, a common-mode inductor, a common-mode magnetic ring, a differential-mode magnetic ring, a differential-mode capacitor and a common-mode capacitor, wherein the harmonic filter circuit includes a filter inductor and a filter capacitor, the filter inductor is connected between the output side of the inverter circuit and the grid-connected port and is also connected to the filter capacitor, and the filter inductor is also connected in series with the filter magnetic ring; the common-mode inductor is connected in series to one end of the filter inductor close to the grid-connected port, and a common-mode magnetic ring and a differential-mode magnetic ring are connected in series between the common-mode inductor and the grid-connected port; the filter inductor, the filter capacitor, the common-mode inductor, the output side of the inverter circuit, and the grid-connected port are respectively grounded through corresponding common-mode capacitors, and the grid-connected port is connected to the differential-mode capacitor.

[0014] In one embodiment, the inverter circuit is a three-phase two-level inverter circuit, which includes three inverter bridge arms, both ends of the three inverter bridge arms are connected in parallel to the DC bus, the midpoints of the three inverter bridge arms are used as phase line output ends, and are respectively connected one-to-one with the three phase line terminals of the grid-connected port, wherein each inverter bridge arm includes two switching tubes connected in series.

[0015] In one embodiment, the inverter circuit is a three-phase multi-level inverter circuit, and the inverter circuit includes three inverter bridge arms and three freewheeling bridge arms; both ends of the three inverter bridge arms are connected in parallel to the DC bus, and the midpoints of the three inverter bridge arms are used as phase line output terminals, and are respectively connected one-to-one with the three phase line terminals of the grid-connected port, wherein each inverter bridge arm includes two half-bridge arms connected in series, and the two half-bridge arms each include two switching tubes connected in series; the three freewheeling bridge arms correspond one-to-one to the three inverter bridge arms, and the two ends of each freewheeling bridge arm are respectively connected to the midpoints of the two half-bridge arms in the corresponding inverter bridge arm, and the midpoint of each freewheeling bridge arm is connected to the midpoint of the DC bus, wherein each freewheeling bridge arm includes two diodes connected in series.

[0016] In one embodiment, the inverter circuit is a three-phase multi-level inverter circuit, and the inverter circuit includes three inverter bridge arms and three freewheeling bridge arms; both ends of the three inverter bridge arms are connected in parallel to the DC bus, and the midpoints of the three inverter bridge arms are used as phase line output ends, and are respectively connected one-to-one with the three phase line terminals of the grid-connected port, wherein each inverter bridge arm includes two switching tubes connected in series; the three freewheeling bridge arms correspond one-to-one to the three inverter bridge arms, and the two ends of each freewheeling bridge arm are respectively connected to the midpoint of the corresponding inverter bridge arm and the midpoint of the DC bus, wherein each freewheeling bridge arm includes two switching tubes connected in reverse series.

[0017] In one embodiment, the inverter circuit is a single-phase inverter circuit, which includes two inverter bridge arms, both ends of which are connected in parallel to the DC bus, and the midpoints of the two inverter bridge arms are used as output ends, and are respectively connected one-to-one with the phase line terminal and the neutral line terminal of the grid-connected port, wherein each inverter bridge arm includes two switching tubes connected in series.

[0018] In one embodiment, the inverter further includes a grid-connected switch, which is serially connected to an end of the filter inductor close to the grid-connected port, or to an end of the common-mode inductor far from the grid-connected port.

[0019] The third aspect of the present application provides an energy storage device, which includes an energy storage battery, a DC conversion circuit, a DC bus and an inverter, the inverter includes an inverter circuit, a grid-connected port and a filter, the energy storage battery is connected to the input end of the DC conversion circuit, the output end of the DC conversion circuit and the input side of the inverter circuit are both connected to the DC bus, and the output side of the inverter circuit is connected to the grid through the grid-connected port; wherein the filter is the filter described in the first aspect of the present application or any one of the embodiments of the first aspect, or the inverter is the inverter described in the second aspect of the present application or any one of the embodiments of the second aspect.

[0020] Compared with the prior art, this application has at least the following advantages:

[0021] 1. The filter of the present application can effectively suppress the conducted interference and radiated interference on the output side of the inverter circuit by designing a harmonic filter circuit, a filter magnetic ring, a common-mode inductor, a common-mode capacitor, a differential-mode capacitor, a common-mode magnetic ring and a differential-mode magnetic ring, and combining the harmonic filter circuit, the filter magnetic ring, the common-mode inductor, the common-mode capacitor, the differential-mode capacitor, the common-mode magnetic ring and the differential-mode magnetic ring, thereby facilitating the normal operation of the inverter circuit and the power grid.

[0022] 2. The filter of the present application can select appropriate harmonic filtering circuits and magnetic rings according to actual conditions. It can be designed as a three-phase filter for use in a three-phase inverter circuit, or it can be designed as a single-phase filter for use in a single-phase inverter circuit. Therefore, the filter of the present application has a wide range of applications and better design flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is an application scenario diagram of the filter provided in Example 1 of the present application.

[0024] Figure 2 yes Figure 1 A circuit diagram of an inverter circuit in .

[0025] Figure 3 yes Figure 1 Another circuit diagram of the inverter circuit in .

[0026] Figure 4 yes Figure 1 Another circuit diagram of the inverter circuit in .

[0027] Figure 5 This is a circuit diagram of the filter provided in Example 1 of the present application.

[0028] Figure 6 This is an application scenario diagram of the filter provided in Example 2 of the present application.

[0029] Figure 7 yes Figure 6 A circuit diagram of an inverter circuit in .

[0030] Figure 8 This is a circuit diagram of the filter provided in Example 2 of the present application.

[0031] Fig. 9 The inverter circuit is not used Figure 5 Schematic diagram of conducted interference test results when the filter is shown.

[0032] Fig.10 The inverter circuit is in use Figure 5 Schematic diagram of conducted interference test results when the filter is shown.

[0033] Fig.11 The inverter circuit is not used Figure 5 Schematic diagram of radiated interference test results when the filter is shown.

[0034] Fig.12 The inverter circuit is in use Figure 5 Schematic diagram of radiated interference test results when the filter is shown.

[0035] Main component symbols

[0036] Photovoltaic panels 10

[0037] Energy storage battery 20

[0038] DC conversion circuit 30

[0039] Inverter circuit 40

[0040] Inverter bridge arm 41

[0041] Freewheeling bridge arm 42

[0042] Filter 50

[0043] Harmonic filter circuit 51

[0044] Filter magnetic ring 52

[0045] Grid-connected port 60

[0046] Grid 70

[0047] Grid-connected switch 80

[0048] Inverter 100

[0049] Energy storage device 1000 DETAILED DESCRIPTION

[0050] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only embodiments of a part of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present application. In the absence of conflict, the following different embodiments and features in the embodiments can be combined with each other.

[0051] See also Figure 1 , is a schematic diagram of a scenario in which the filter provided in Example 1 of the present application is applied to an inverter circuit.

[0052] Specifically, Figure 1 The scene includes a photovoltaic module 10, an energy storage battery 20, a DC conversion circuit 30, a DC bus (BUS+, BUS-), an inverter circuit 40, a filter 50, a grid-connected port 60 and a power grid 70. The output end of the photovoltaic module 10 and the positive and negative poles of the energy storage battery 20 are connected to the input end of the DC conversion circuit 30. The output end of the DC conversion circuit 30 and the input side of the inverter circuit 40 are connected to the DC bus BUS+ and BUS-. The DC bus BUS+ and BUS- are connected through bus capacitors Cbus1 and Cbus2 connected in series. Based on such a design, the photovoltaic module 10 and the energy storage battery 20 can both provide a DC voltage to the inverter circuit 40 through the DC conversion circuit 30, and the inverter circuit 40 then converts the DC voltage into an AC voltage. The output side of the inverter circuit 40 can be connected to the load port ( Figure 1 Not shown) connected to the load ( Figure 1 The inverter circuit 40 can then supply power to the load through the load port. The output side (also referred to as the grid-connected side) of the inverter circuit 40 is also connected to the power frequency grid 70 through the grid-connected port 60, and the inverter circuit 40 can then be grid-connected for operation.

[0053] In the first embodiment, the inverter circuit 40 is a three-phase inverter circuit, and its output side has three output terminals, which are phase line output terminals A, B, and C. The power grid 70 corresponds to a three-phase power grid, which has a neutral line N and three-phase lines L1, L2, and L3. The grid-connected port 60 has four terminals, which are a neutral line terminal n and three phase line terminals a, b, and c. The three phase line terminals a, b, and c are connected to the three phase line output terminals A, B, and C in a one-to-one correspondence, and are connected to the three-phase lines L1, L2, and L3 of the power grid 70 in a one-to-one correspondence. The neutral line terminal n is connected to the neutral line N of the power grid 70.

[0054] The circuit structure of the inverter circuit 40 is not limited. Figure 2 As shown, the inverter circuit 40 can be a three-phase two-level inverter circuit. The inverter circuit 40 includes three inverter bridge arms 41, and each inverter bridge arm 41 includes two switch tubes connected in series (i.e., S1_A and S2_A, or S1_B and S2_B, or S1_C and S2_C). Both ends of the three inverter bridge arms 41 are connected in parallel to the DC bus BUS+ and BUS-, and the midpoints of the three inverter bridge arms 41 serve as the three phase line output terminals A, B, and C on the output side. The two switch tubes of the same inverter bridge arm 41 are complementary. Based on this, the voltage outputted by each phase line output terminal of the inverter circuit 40 has two level states.

[0055] For example, Figure 3As shown, the inverter circuit 40 can be a three-phase three-level I-type inverter circuit. The inverter circuit 40 includes three inverter bridge arms 41 and three freewheeling bridge arms 42. The three freewheeling bridge arms 42 correspond to the three inverter bridge arms 41 one by one. Each inverter bridge arm 41 includes two half-bridge arms in series, and the two half-bridge arms each include two switch tubes in series (i.e., S1_A and S2_A, or S3_A and S4_A, or S1_B and S2_B, or S3_B and S4_B, or S1_C and S2_C, or S3_C and S4_C). Each freewheeling bridge arm 42 includes two diodes in series (i.e., D1_A and D2_A, or D1_B and D2_B, or D1_C and D2_C). Both ends of the three inverter bridge arms 41 are connected in parallel between the DC busbars BUS+ and BUS-, and the midpoints of the three inverter bridge arms 41 serve as the three phase line output terminals A, B, and C on the output side. Both ends of the three freewheeling bridge arms 42 are respectively connected to the midpoints of the two half bridge arms in the corresponding inverter bridge arm 41, and the midpoints of the three freewheeling bridge arms 42 are connected to the connection point O between the bus capacitors Cbus1 and Cbus2, and the point O can also be called the midpoint of the DC busbar. Only two adjacent switch tubes in the same inverter bridge arm 41 can be turned on at the same time, such as S1_A and S2_A are turned on at the same time, or S3_A and S4_A are turned on at the same time, or S2_A and S3_A are turned on at the same time. One of the two switch tubes separated by phase is turned on, such as S1_A and S3_A are turned on, or S2_A and S4_A are turned on. Based on this, the voltage output by each phase line output terminal of the inverter circuit 40 has three level states.

[0056] For example, Figure 4As shown, the inverter circuit 40 can be a three-phase three-level T-type inverter circuit. The inverter circuit 40 includes three inverter bridge arms 41 and three freewheeling bridge arms 42, and the three freewheeling bridge arms 42 correspond to the three inverter bridge arms 41 one by one. Each inverter bridge arm 41 includes two switch tubes (i.e., S1_A and S4_A, or S1_B and S4_B, or S1_C and S4_C) connected in series. Both ends of the three inverter bridge arms 41 are connected in parallel to the DC bus BUS+ and BUS-, and the midpoints of the three inverter bridge arms 41 serve as the three phase line output terminals A, B, and C on the output side. Each freewheeling bridge arm 42 includes two switch tubes (i.e., S2_A and S3_A, or S2_B and S3_B, or S2_C and S3_C) connected in reverse series. The two ends of each freewheeling bridge arm 42 are respectively connected to the midpoint of the corresponding inverter bridge arm 41 and the midpoint O of the DC bus. Only two switches in the inverter bridge arm 41 and its corresponding freewheeling bridge arm 42 can be turned on at the same time. It can be that one of the two switches in the same inverter bridge arm 41 is turned on and one of the two switches in the corresponding freewheeling bridge arm 42 is turned on, or both of the two switches in the same inverter bridge arm 41 are turned off and both of the two switches in the corresponding freewheeling bridge arm 42 are turned on. For example, S1_A and S2_A are turned on at the same time, or S3_A and S4_A are turned on at the same time, or S2_A and S3_A are turned on at the same time. Based on this, the voltage outputted by each phase line output terminal of the inverter circuit 40 has three level states.

[0057] Understandably, Figures 2 to 4 This is only an illustrative example of the inverter circuit 40 of this embodiment. In other embodiments, the inverter bridge arm 41 and / or the freewheeling bridge arm 42 may further include more switch tubes, and the on-off modes of the switch tubes may also be more, so that the inverter circuit 40 may be a three-phase inverter circuit with more levels, which may be specifically configured according to actual conditions, and are all within the protection scope of this application.

[0058] like Figure 1 As shown, the filter 50 is a three-phase filter, which is arranged between the output side of the inverter circuit 40 and the grid-connected port 60. It should be understood that the filter 50 and the inverter circuit 40, the grid-connected port 60, and the grid-connected port 60 can be at least partially integrated on the same PCB board, and the filter 50 and the inverter circuit 40, the grid-connected port 60, and the grid-connected port 60 can also be independently arranged, which is not limited here.

[0059] For details, please refer to Figure 5 The filter 50 includes a harmonic filter circuit 51. The harmonic filter circuit 51 is used to filter out the harmonic current output by the inverter circuit 40 to prevent the harmonic current from causing conducted interference and radiated interference.

[0060] In this embodiment, if Figure 5As shown, the harmonic filter circuit 51 includes three filter inductors Lf1-Lf3, three filter capacitors Cf1-Cf3 and three power frequency inductors Lf4-Lf6. The filter inductors Lf1-Lf3, the filter capacitors Cf1-Cf3 and the power frequency inductors Lf4-Lf6 correspond to the phase line output terminals A, B and C on the output side of the inverter circuit 40. Each filter inductor and a corresponding power frequency inductor are connected in series between a phase line output terminal of the inverter circuit 40 and a corresponding phase line terminal of the grid-connected port 60. One end of the three filter capacitors is connected between the corresponding filter inductor and the power frequency inductor, respectively, and the other ends of the three filter capacitors are connected together.

[0061] It can be understood that the connected filter inductor, filter capacitor and power frequency inductor (such as Lf1, Cf1 and Lf4, Lf2, Cf2 and Lf5, Lf3, Cf3 and Lf6) constitute an LCL filter circuit. In high frequency conditions, the inductor impedance is large and the capacitor impedance is small. Therefore, the filter inductor Lf1~Lf3 and the power frequency inductor Lf4~Lf6 can suppress high frequency harmonic currents, and the filter capacitor Cf1~Cf3 can suppress low frequency harmonic currents and provide a low resistance path for high frequency harmonic currents. Therefore, the harmonic filter circuit 51 effectively reduces the harmonic current components injected into the power grid 70.

[0062] Among them, the inductance values ​​of the filter inductors Lf1~Lf3 and the power frequency inductors Lf4~Lf6, and the capacitance values ​​of the filter capacitors Cf1~Cf3 can be selected accordingly according to the actual situation, and no specific limitation is made here. For example, the inductance values ​​of the filter inductors Lf1~Lf3 are all greater than the inductance values ​​of the power frequency inductors Lf4~Lf6. For example, the inductance value of the filter inductor Lf1 can be more than ten times that of the power frequency inductors Lf4~Lf6. Among them, the three filter inductors Lf1~Lf3 can adopt integrated inductance elements (that is, the three filter inductors are integrated into one) according to the actual situation, or they can adopt discrete inductance elements (that is, the three filter inductors are independent of each other). The settings of the three filter capacitors Cf1~Cf3 and the three power frequency inductors Lf4~Lf6 are similar, and will not be repeated here.

[0063] It should be noted that when the inverter circuit 40 is a three-phase multi-level inverter circuit, and the connected filter inductor, filter capacitor and power frequency inductor constitute an LCL filter circuit, the other ends of the filter capacitors Cf1, Cf2, and Cf3 are also connected to the midpoint O of the DC bus.

[0064] In some embodiments, when the power frequency inductors Lf4-Lf6 use inductors with smaller inductance values, the parasitic inductance of the line can also act as the power frequency inductors Lf4-Lf6. Therefore, the harmonic filter circuit 51 can also include filter inductors Lf1-Lf3 and filter capacitors Cf1-Cf3, and the power frequency inductors Lf4-Lf6 are not provided. The connection relationship between the filter inductors Lf1-Lf3 and the filter capacitors Cf1-Cf3 can refer to the above-mentioned related description, which will not be repeated here. The filter inductors and filter capacitors (such as Lf1 and Cf1, Lf2 and Cf2, Lf3 and Cf3) constitute an LC filter circuit, which can be used to filter out harmonics of a specific frequency, and has fewer components and low cost.

[0065] In some embodiments, when the filter inductors Lf1~Lf3 use inductance elements with larger inductance values, the volume of the filter inductors Lf1~Lf3 is large, which is not conducive to integration with other components of the inverter circuit 40 and the filter 50. Therefore, the filter inductors Lf1~Lf3 can be used as external components, and the input lead wires and output lead wires of the filter inductors Lf1~Lf3 are connected to the phase line output terminals A, B, and C of the inverter circuit 40 through the terminal blocks t1~t6.

[0066] like Figure 5 As shown, the inverter circuit 40 further includes a filter magnetic ring 52. The filter inductors Lf1, Lf2, and Lf3 are all connected in series with the filter magnetic ring 52, and the filter magnetic ring 52 can be used to improve the conduction and radiation interference suppression effect.

[0067] In this embodiment, if Figure 5 As shown, the filter magnetic ring 52 includes a first magnetic ring Q1, a second magnetic ring Q2 and a third magnetic ring Q3. The first magnetic ring Q1 and the second magnetic ring Q2 are both connected in series to one end of the filter inductor Lf1-Lf3 close to the inverter circuit 40 (i.e., the input end of the filter inductor), and the third magnetic ring Q3 is connected in series to one end of the filter inductor Lf1-Lf3 away from the inverter circuit 40 (i.e., the output end of the filter inductor). In actual implementation, the first magnetic ring Q1, the second magnetic ring Q2 and the third magnetic ring Q3 need to be arranged in conjunction with the filter inductor Lf1-Lf3, so that the input end lead wire of the filter inductor Lf1-Lf3 is wound around the first magnetic ring Q1 and the second magnetic ring Q2 and then connected to the wiring terminals t1-t3, and the output end lead wire of the filter inductor Lf1-Lf3 is wound around the third magnetic ring Q3 and then connected to the wiring terminals t4-t6.

[0068] In this embodiment, the first magnetic ring Q1, the second magnetic ring Q2 and the third magnetic ring Q3 are all common mode magnetic rings. Moreover, the first magnetic ring Q1, the second magnetic ring Q2 and the third magnetic ring Q3 have different equivalent inductances and act in different frequency bands respectively.

[0069] It should be understood that the materials and number of turns of the first magnetic ring Q1, the second magnetic ring Q2 and the third magnetic ring Q3 can be selected accordingly according to actual conditions, so that the first magnetic ring Q1, the second magnetic ring Q2 and the third magnetic ring Q3 have corresponding equivalent inductances and act on corresponding frequency bands. For example, when the low frequency band of conducted interference is 150KHz-1MHz, the medium frequency band of conducted interference is 1MHz-10MHz, the high frequency band of conducted interference is 10MHz-30MHz, the low frequency band of radiated interference is 30MHz-100MHz, the medium frequency band of radiated interference is 100MHz-300MHz, and the high frequency band of radiated interference is 300MHz-1GHz, the first magnetic ring Q1 can be an amorphous nano-magnetic ring, the number of turns of which can be 3, and the equivalent inductance can reach 6.8μH, and the first magnetic ring Q1 can be used to suppress conducted and radiated interference in the low frequency band. The second magnetic ring Q2 can be a manganese-zinc ferrite magnetic ring, which can have 2 turns and an equivalent inductance of up to 11.8μH. The second magnetic ring Q2 can be used to suppress the conducted interference in the mid-frequency band and the radiated interference in the mid-low frequency band. The third magnetic ring Q3 can be a nickel-zinc ferrite magnetic ring, which can have 2 turns and an equivalent inductance of up to 12.3μH. The third magnetic ring Q3 can be used to suppress the radiated interference in the mid-high frequency band. Therefore, based on the magnetic rings Q1 to Q3, the conducted and radiated interference in the full frequency band can be suppressed.

[0070] In addition, the settings of the first magnetic ring Q1, the second magnetic ring Q2 and the third magnetic ring Q3 can be selected accordingly according to actual conditions. For example, the filter magnetic ring 52 can also include any one or any two of the first magnetic ring Q1, the second magnetic ring Q2 and the third magnetic ring Q3. Moreover, the positions of the first magnetic ring Q1, the second magnetic ring Q2 and the third magnetic ring Q3 can be interchanged, and the magnetic ring material and the number of turns can be changed (that is, the equivalent inductance can be changed). The input lead wires of the filter inductors Lf1~Lf3 can be wound together on the same first magnetic ring Q1 or the same second magnetic ring Q2, or they can be wound separately on different first magnetic rings Q1 or different second magnetic rings Q2. The output lead wires of the filter inductors Lf1~Lf3 can be wound together on the same third magnetic ring Q3, or they can be wound separately on different third magnetic rings Q3.

[0071] like Figure 5 As shown, the inverter circuit 40 further includes a common mode inductor CM1 which is connected in series to one end of the filter inductors Lf1 to Lf3 close to the grid-connected port 60 , and can be used to further filter out common mode interference on the grid-connected side of the inverter circuit 40 .

[0072] In this embodiment, if Figure 5As shown, the three input terminals of the common mode inductor CM1 are connected to the power frequency inductors Lf4 to Lf6 one by one, so that the filter inductors Lf1 to Lf3, the power frequency inductors Lf4 to Lf6 and the common mode inductor CM1 are connected in series in sequence. The coil windings in the common mode inductor CM1 can be wound on the same magnetic core in the common mode inductor CM1 to reduce the consistency difference of the components, thereby avoiding affecting the filtering effect.

[0073] In some other embodiments, the harmonic filter circuit 51 is not provided with power frequency inductors Lf4-Lf6, so the three input terminals of the common mode inductor CM1 are connected to the filter inductors Lf1-Lf3 one by one, that is, the filter inductor and the common mode inductor CM1 are directly connected in series.

[0074] like Figure 5 As shown, the inverter circuit 40 also includes common-mode capacitors (see CY1 to CY36). The three phase line output terminals A, B, and C on the output side of the inverter circuit 40, the filter inductors Lf1 to Lf3, the filter capacitors Cf1 to Cf3, the power frequency inductors Lf4 to Lf6, the three output terminals of the common-mode inductor CM1, the neutral line terminal n of the grid-connected port 60, and the three phase line terminals a, b, and c are grounded respectively through corresponding common-mode capacitors.

[0075] For the sake of distinction, the common-mode capacitors (see CY1 to CY6) connected to the phase line output terminals A, B, and C on the output side of the inverter circuit 40 can be called the first common-mode capacitors. The common-mode capacitors (see CY7 to CY12) connected to the filter inductors Lf1 to Lf3 can be called the second common-mode capacitors. The common-mode capacitors (see CY13) connected to the filter capacitors Cf1 to Cf3 can be called the third common-mode capacitors. The common-mode capacitors (see CY14 to CY19) connected to the power frequency inductors Lf4 to Lf6 can be called the fourth common-mode capacitors. The common-mode capacitors (see CY20 to CY25) connected to the common-mode inductors CM1 can be called the fifth common-mode capacitors. The common-mode capacitors (see CY26 to CY33) connected to the grid-connected port 60 can be called the sixth common-mode capacitors.

[0076] The first common-mode capacitor (see CY1 to CY6 ) is used to provide a ground loop for the common-mode current generated when the inverter circuit 40 is working, thereby reducing the common-mode interference generated by the inverter circuit 40 .

[0077] The second common-mode capacitor (see CY7-CY12) is used to provide a ground loop for the common-mode interference introduced by the stray parasitic capacitance and the charging and discharging of the parasitic inductance of the filter inductors Lf1-Lf3, thereby reducing the common-mode interference caused by the stray parasitic parameters of the filter inductors Lf1-Lf3.

[0078] The third common-mode capacitor (see CY13) is used to provide a ground loop for the common-mode interference introduced by the stray parasitic parameters of the filter capacitors Cf1~Cf3. In addition, when the filter capacitors Cf1~Cf3 are connected to the midpoint O of the DC bus (that is, connected to the DC conversion circuit 30), it is also used to provide a ground loop for the crosstalk introduced by the connection of the filter capacitors Cf1~Cf3 to the midpoint O of the DC bus, thereby reducing the common-mode interference introduced by the filter capacitors Cf1~Cf3.

[0079] The fourth common-mode capacitor (see CY14-CY19) is used to provide a ground loop for the common-mode interference introduced by the stray parasitic capacitance and parasitic inductance charging and discharging of the power frequency inductors Lf4-Lf6, thereby reducing the common-mode interference caused by the stray parasitic parameters of the power frequency inductors Lf4-Lf6.

[0080] The fifth common-mode capacitor (see CY20-CY25) is used to provide a ground loop for the common-mode interference introduced by the stray parasitic capacitance and the parasitic inductance charging and discharging of the common-mode inductor CM1, thereby reducing the common-mode interference caused by the stray parasitic parameters of the common-mode inductor CM1.

[0081] The sixth common-mode capacitor (see CY26 to CY33) is used to provide a ground loop for the common-mode interference generated by the coupling between the PCB board where the inverter circuit 40 is located and the grid-connected port 60, thereby reducing the common-mode interference introduced by the PCB board and the grid-connected port 60.

[0082] Among them, in this embodiment, a common mode capacitor may include two capacitors in parallel, one of which is used as a main capacitor and the other as an auxiliary capacitor. For example, capacitors CY1 and CY2, CY3 and CY4, CY5 and CY6 may constitute three first common mode capacitors, capacitors CY7 and CY8, CY9 and CY10, CY11 and CY12 may constitute three second common mode capacitors, wherein the capacitors with odd numbers are main capacitors and the capacitors with even numbers are auxiliary capacitors. For another example, capacitors CY14 and CY15, CY16 and CY17, CY18 and CY19 may constitute three fourth common mode capacitors, capacitors CY20 and CY21, CY22 and CY23, CY24 and CY25 may constitute three fifth common mode capacitors, capacitors CY26 and CY27, CY28 and CY29, CY30 and CY31, CY32 and CY33 may constitute four sixth common mode capacitors, wherein the capacitors with even numbers are main capacitors and the capacitors with odd numbers are auxiliary capacitors. Alternatively, a common-mode capacitor may also be a capacitor, for example, capacitor CY13 may constitute a third common-mode capacitor.

[0083] In this embodiment, the capacitance value of each capacitor in the first to sixth common-mode capacitors can be set accordingly according to actual conditions, and is not limited here. Among them, the capacitance value of the main capacitor is greater than the capacitance value of the auxiliary capacitor. For example, the capacitance value of the auxiliary capacitor can be 1 / 10, 1 / 100 or 0 of the capacitance value of the main capacitor. For further example, the main capacitors CY1, CY3, CY5, CY26, CY28, CY30, and CY32 are all 10nF, and correspondingly, the auxiliary capacitors CY2, CY4, CY6, CY27, CY29, CY31, and CY33 are all 100pF. The main capacitors CY7, CY9, CY11, CY20, CY22, and CY24 are all 4.7nF, and correspondingly, the auxiliary capacitors CY8, CY10, CY12, CY21, CY23, and CY25 are all 470pF. The main capacitors CY14, CY16, and CY18 are all 1nF, and correspondingly, the auxiliary capacitors CY15, CY17, and CY19 are all 0nF. The third common mode capacitor CY13 is 2.2nF.

[0084] It can be understood that since a differential mode loop is formed between the phase line terminals a, b, c and the neutral line terminal n of the grid-connected port 60, differential mode interference is generated on the grid-connected side of the inverter circuit 40. Figure 5 As shown, the inverter circuit 40 also includes differential mode capacitors CX1 to CX3. Each phase line terminal a / b / c and the neutral line terminal n are connected via corresponding differential mode capacitors CX1 / CX2 / CX3, respectively. The differential mode capacitors CX1 to CX3 can be used to provide a short-circuit path for differential mode interference, thereby reducing differential mode interference. The capacitance values ​​of the differential mode capacitors CX1 to CX3 can be set accordingly according to actual conditions, for example, they can all be set to 1 μF.

[0085] like Figure 5 As shown, the inverter circuit 40 also includes a common mode magnetic ring Q4 and a differential mode magnetic ring Q5. The common mode magnetic ring Q4 and the differential mode magnetic ring Q5 are connected in series between the common mode inductor CM1 and the grid-connected port 60. The common mode magnetic ring Q4 can be used to suppress the common mode interference generated by spatial coupling at the grid-connected port 60, and further attenuate the common mode interference. The differential mode magnetic ring Q5 can be used to suppress the differential mode interference generated by spatial coupling at the grid-connected port 60, and further attenuate the differential mode interference.

[0086] In this embodiment, if Figure 5 As shown, the three output ends of the common-mode inductor CM1 are connected in series with the common-mode magnetic ring Q4 and the differential-mode magnetic ring Q5, and the neutral line terminal n and the three phase line terminals a, b, and c of the grid-connected port 60 are also connected in series with the common-mode magnetic ring Q4 and the differential-mode magnetic ring Q5. Moreover, the three output ends of the common-mode inductor CM1 are connected one by one to the three phase line terminals a, b, and c of the grid-connected port 60 after passing through the common-mode magnetic ring Q4 and the differential-mode magnetic ring Q5.

[0087] In actual implementation, the common-mode inductor CM1 can select the corresponding inductance value according to the actual situation, and the common-mode magnetic ring Q4 and the differential-mode magnetic ring Q5 can select the magnetic rings of the corresponding materials and number of turns (i.e., equivalent inductance) according to the actual situation. For example, the equivalent inductance value of the common-mode inductor CM1 can be 95μH. The common-mode magnetic ring Q4 can be a ferrite magnetic ring, an iron powder core magnetic ring, a Sendust magnetic ring or an amorphous magnetic ring, and its number of turns can be 3 turns, and the equivalent inductance can reach 14.2μH. The differential-mode magnetic ring Q5 can be a Sendust magnetic ring, and its number of turns can be 2 turns, and the equivalent inductance can reach 7.9μH. In addition, the three output lead wires of the common-mode inductor CM1 can be wound together on the same common-mode magnetic ring Q4 or the same differential-mode magnetic ring Q5, or they can be wound on different common-mode magnetic rings Q4 or different differential-mode magnetic rings Q5. The lead wires of the neutral terminal n and the phase terminals a, b, c are wound around the common mode magnetic ring Q4 in the same direction, and the lead wires of the neutral terminal n and the phase terminals a, b, c are wound around the differential mode magnetic ring Q5 in the opposite direction.

[0088] In addition, for the convenience of connection, the three output lead wires of the common mode inductor CM1 can also be connected to the wiring terminals t7-t9 one by one, and the lead wires of the phase line wiring terminals a, b, and c of the grid-connected port 60 can be connected to the wiring terminals t7-t9 one by one after passing through the common mode magnetic ring Q4 and the differential mode magnetic ring Q5, thereby realizing the connection between the output lead wires of the common mode inductor CM1 and the phase line wiring terminals a, b, and c of the grid-connected port 60. One end of the differential mode capacitors CX1-CX3 used for connecting the neutral line wiring terminal n can be connected to the wiring terminal t10, and the neutral line wiring terminal n of the grid-connected port 60 can be connected to the wiring terminal t10 after passing through the common mode magnetic ring Q4 and the differential mode magnetic ring Q5, thereby realizing the connection between the differential mode capacitors CX1-CX3 and the neutral line wiring terminal n of the grid-connected port 60.

[0089] See also Figure 6 , is a schematic diagram of a scenario in which the filter 50 provided in the second embodiment of the present application is applied to the inverter circuit 40. Figure 6 The scene includes a photovoltaic module 10, an energy storage battery 20, a DC conversion circuit 30, a DC bus (BUS+, BUS-), an inverter circuit 40, a filter 50, a grid-connected port 60 and a power grid 70.

[0090] The difference between the second embodiment and the first embodiment is that the inverter circuit 40 of the second embodiment is a single-phase inverter circuit, and its output side has two output terminals, namely, a phase line output terminal AC+ and a neutral line output terminal AC-. The power grid 70 can be a single-phase power grid 70, having a neutral line N and a phase line L. The grid-connected port 60 has two terminals, namely, a neutral line terminal n and a phase line terminal l. The phase line terminal l is connected to the phase line output terminal AC+, and is connected to the phase line L of the power grid 70. The neutral line terminal n is connected to the neutral line output terminal AC-, and is connected to the neutral line N of the power grid 70.

[0091] Among them, Figure 7 As shown, the inverter circuit 40 may include two inverter bridge arms 41. Each inverter bridge arm 41 includes two switch tubes (i.e., S1_A and S2_A, or S1_B and S2_B) connected in series. Both ends of the two inverter bridge arms 41 are connected in parallel between the DC busbars BUS+ and BUS-, and the midpoints of the two inverter bridge arms 41 serve as the phase line output terminal AC+ and the neutral line output terminal AC- of the output side, and are respectively connected to the phase line terminal l and the neutral line terminal n of the grid-connected port 60 in a one-to-one correspondence.

[0092] Understandably, Figure 7 This is only an illustrative example of the inverter circuit 40 in this embodiment. The inverter circuit 40 may also be a single-phase multi-level inverter circuit or any other single-phase inverter circuit. The specific selection may be made according to actual conditions and is within the protection scope of this application.

[0093] The difference between the second embodiment and the first embodiment is that the filter 50 of the second embodiment is a single-phase filter. The filter 50 is arranged between the phase line output terminal AC+ and the neutral line output terminal AC- on the output side of the inverter circuit 40 and the neutral line terminal n and the phase line terminal l of the grid-connected port 60, and is used to suppress the conducted and radiated interference between the phase line output terminal AC+ and the neutral line terminal n, and between the neutral line output terminal AC- and the phase line terminal l. Therefore, the filter 50 of the second embodiment is actually different from the filter 50 of the first embodiment in the number of phases of filtering processing (the second embodiment corresponds to L and N, and the first embodiment corresponds to L1, L2, and L3), so the structure of the filter 50 provided in the second embodiment can be adaptively adjusted with reference to the structure of the filter 50 of the first embodiment.

[0094] For example, Figure 8 As shown, the filter 50 provided in the second embodiment includes a harmonic filter circuit 51 (see Lf1~Lf4, Cf1, Cf2), a filter magnetic ring 52 (see Q1~Q3), a common mode inductor CM1, a common mode capacitor (see CY1~CY21), a differential mode capacitor CX1, a common mode magnetic ring Q4 and a differential mode magnetic ring Q5.

[0095] Among them, the harmonic filter circuit 51 has two filter inductors (see Lf1, Lf2), two filter capacitors (see Cf1, Cf2) and two power frequency inductors (see Lf3, Lf4), the filter inductor Lf1 is connected between the phase line output terminal AC+ and the phase line terminal l of the inverter circuit 40, the filter inductor Lf2 is connected between the neutral line output terminal AC- and the neutral line terminal n of the inverter circuit 40, the filter inductor Lf1 is connected to one end of the filter capacitor Cf1, the filter inductor Lf2 is connected to one end of the filter capacitor Cf2, and the other end of the filter capacitor Cf1 is connected to the other end of the filter capacitor Cf2. Both filter inductors are connected in series with the filter magnetic ring 52. The power frequency inductors Lf3 and Lf4 are respectively connected to the two input ends of the common mode inductor CM1, so that the filter inductor, the power frequency inductor and the common mode inductor CM1 are connected in series in sequence. The phase line output terminal AC+, the neutral line output terminal AC-, the filter inductors Lf1 and Lf2, the two filter capacitors Cf1 and Cf2, the two power frequency inductors Lf3 and Lf4, the two output terminals of the common mode inductor CM1, the neutral line terminal n and the phase line terminal l of the grid-connected port 60 are grounded respectively through corresponding common mode capacitors. The phase line terminal l and the neutral line terminal n are connected through a differential mode capacitor CX1.

[0096] It can be understood that the harmonic filter circuit 51, filter magnetic ring 52, common mode inductor, common mode capacitor, differential mode capacitor, common mode magnetic ring and differential mode magnetic ring of the second embodiment can also refer to the relevant description in the aforementioned first embodiment, and will not be repeated here.

[0097] In addition, in order to verify the filtering effect of the filter 50 in the embodiment of the present application, the embodiment of the present application also tests Figure 5 The filter 50 is shown to test the conducted and radiated interferences at the output side of the inverter circuit 40. In the test, the inverter circuit 40 is in a full-load working state, and the working conditions such as the test environment remain unchanged.

[0098] Specifically, Fig. 9 The output side of the inverter circuit 40 is shown in FIG. Figure 5 The conducted interference test results of the filter 50 in the first embodiment are shown. Fig.10 The output side of the inverter circuit 40 is connected to Figure 5 The conducted interference test results of the filter 50 in the first embodiment are shown. Fig. 9 and Fig.10 In the figure, the red curve is the actual AV average test curve, and the blue curve is the actual QP quasi-peak test curve. The relatively smooth red line is the average standard of the AC conduction standard EN 55011 Class B, and the relatively smooth blue line is the peak standard of the AC conduction standard EN 55011 Class B.

[0099] Fig.11The output side of the inverter circuit 40 is shown in FIG. Figure 5 The radiation interference test results of the filter 50 in the first embodiment are shown. Fig.12 The output side of the inverter circuit 40 is connected to Figure 5 The radiation interference test results of the filter 50 in the first embodiment are shown. Fig.11 and Fig.12 In the figure, the red curve is the actual radiation test curve, and the smoother blue line is the radiation test standard line.

[0100] By comparison Fig. 9 and Fig.10 It can be seen that under the same working conditions, the AV mean and QP quasi-peak values ​​when the filter 50 of the first embodiment is used are smaller than the AV mean and QP quasi-peak values ​​when the filter 50 of the first embodiment is not used. Fig.10 As shown, the actual AV average curve and the actual QP quasi-peak curve when using the filter 50 of the first embodiment are both lower than the corresponding standard line and meet the 6dB margin requirement in the industry. Therefore, by setting the filter 50 of the embodiment of the present application, the conducted interference on the grid-connected side of the inverter circuit 40 can be effectively improved.

[0101] By comparison Fig.11 and Fig.12 It can be seen that under the same working conditions, the radiation when the filter 50 of the first embodiment is used is less than the radiation when the filter 50 of the first embodiment is not used. Fig.12 As shown, the actual radiation test curve when the filter 50 of the first embodiment is used is lower than the standard line. Therefore, by setting the filter 50 of the embodiment of the present application, the radiation interference on the grid-connected side of the inverter circuit 40 can also be effectively improved.

[0102] In general, the embodiment of the present application provides a filter 50, which can effectively suppress the conducted interference and radiated interference on the output side of the inverter circuit 40 by combining the harmonic filter circuit 51, the filter magnetic ring 52, the common mode inductor, the common mode capacitor, the differential mode capacitor, the common mode magnetic ring and the differential mode magnetic ring, thereby facilitating the normal operation of the inverter circuit 40 and the power grid 70.

[0103] It should be understood that electromagnetic interference comes from various sources, and many crosstalks will be generated between circuits of different levels. If targeted conduction and radiation improvement designs are made for each level of circuits to improve the electromagnetic interference on the grid-connected side, it will be more troublesome, and the debugging process will also be time-consuming and labor-intensive. Considering that the output side of the inverter circuit 40 is connected to the power grid 70, the embodiment of the present application designs a filter 50 that can be applied to the output side of the inverter circuit 40. The filter 50 can effectively reduce the conducted interference and radiation interference on the output side of the inverter circuit 40, thereby achieving the purpose of improving the electromagnetic interference on the output side of the inverter circuit 40. Moreover, in actual implementation, the designer can reasonably select the device parameters of the filter 50. During the rectification and debugging process, the designer can fine-tune the device parameters in the filter 50 based on experimental tests, so that the interference measurement value on the output side of the inverter circuit 40 is limited to a preset range, and will not affect the functions of the inverter circuit 40 and other circuits. Therefore, the implementation complexity is low, and rectification and debugging are also easier and more time-saving.

[0104] In the filter 50 of the embodiment of the present application, the harmonic filter circuit 51 can play a harmonic filtering role, the filter magnetic ring 52, the common mode inductor, the common mode capacitor and the common mode magnetic ring can play a common mode filtering role, and the differential mode capacitor and the differential mode magnetic ring can play a differential mode filtering role. Specifically, the harmonic filter circuit 51 can filter out the harmonics output by the inverter circuit 40, and the first common mode capacitor can filter out the common mode interference generated by the inverter circuit 40, thereby suppressing electromagnetic interference from the source. The filter magnetic ring 52 can enhance the filtering effect of the filter inductor in the harmonic filter circuit 51. The common mode inductor can further filter the common mode interference of the line transmission. The common mode magnetic ring and the sixth common mode capacitor can both improve the common mode interference generated by the spatial coupling mode on the grid-connected side of the inverter circuit 40. The differential mode magnetic ring and the differential mode capacitor can both improve the differential mode interference generated by the spatial coupling mode on the grid-connected side of the inverter circuit 40. The second to fifth common-mode capacitors can all reduce the common-mode interference caused by the parasitic parameters of the filter inductor, common-mode capacitor, power frequency inductor, and common-mode inductor in the harmonic filter circuit 51. In addition, when the filter capacitor is connected to the midpoint O of the DC bus, the third common-mode capacitor can also reduce the crosstalk between the front-stage DC conversion circuit 30 and the rear-stage inverter circuit 40. Therefore, the embodiment of the present application can take into account the suppression of conducted interference (including common-mode interference and differential-mode interference) and radiated interference.

[0105] The filter 50 of the embodiment of the present application can select appropriate harmonic filter circuits 51 and magnetic rings Q1~Q5 according to actual conditions. It can be designed as a three-phase filter for application in a three-phase inverter circuit, or it can be designed as a single-phase filter for application in a single-phase inverter circuit. Therefore, the filter 50 of the embodiment of the present application has a wide range of applications and better design flexibility.

[0106] In addition, an embodiment of the present application also provides an inverter.

[0107] Please refer again Figure 1 and Figure 6 The inverter 100 includes an inverter circuit 40, a grid-connected port 60, and a filter 50. The input side of the inverter circuit 40 is connected to the DC bus (BUS+, BUS-), the output side of the inverter circuit 40 is connected to the power grid 70 through the grid-connected port 60, and the filter 50 is arranged between the output side of the inverter circuit 40 and the grid-connected port 60.

[0108] The inverter circuit 40 may be a three-phase inverter circuit, and correspondingly, the filter 50 is a three-phase filter. Figures 1 to 5 The description of the first embodiment is not repeated here. Alternatively, the inverter circuit 40 may be a single-phase inverter circuit, and the filter 50 may be a single-phase filter. Figures 6 to 8 The description of the second embodiment will not be repeated here.

[0109] In the embodiment of the present application, the inverter 100 may further include a grid-connected switch 80 (see Figure 5 K1~K6 and Figure 8 K1~K4, Figure 1 and Figure 7 The grid-connected switch 80 may be disposed in the filter 50, and may be specifically connected in series to one end of the filter inductor close to the grid-connected port 60 or to one end of the common-mode inductor far from the grid-connected port 60. For example, Figure 5 and Figure 8 As shown, the grid-connected switch 80 can be connected between the filter inductor and the power frequency inductor. In another example, the grid-connected switch 80 can be connected between the power frequency inductor and the common mode inductor CM1. The grid-connected switch 80 can be used to control the connection or disconnection between the inverter circuit 40 and the grid-connected port 60, thereby controlling the inverter circuit 40 to be connected to the grid or off the grid.

[0110] The grid-connected switch 80 may be, for example, a relay or other switch device. Moreover, in order to prevent a single relay from sticking and causing the circuit-breaking function to fail, the grid-connected switch 80 may be a two-stage relay or other two-stage switch device. When any one-stage relay or switch device is disconnected, the inverter circuit 40 is disconnected from the grid-connected port 60, and the inverter circuit 40 is also disconnected from the grid. When both the two-stage relays or switch devices are closed, the inverter circuit 40 is connected to the grid-connected port 60, and the inverter circuit 40 can be connected to the grid. In actual implementation, the grid-connected switch 80 can be integrated with at least a portion of the filter 50.

[0111] In addition, an embodiment of the present application also provides an energy storage device.

[0112] Please continue reading Figure 1 and Figure 6The energy storage device 1000 includes an energy storage battery 20, a DC conversion circuit 30, a DC bus (BUS+, BUS-) and an inverter 100. The inverter 100 includes an inverter circuit 40, a grid-connected port 60 and a filter 50. The energy storage battery 20 is connected to the input end of the DC conversion circuit 30, the output end of the DC conversion circuit 30 and the input side of the inverter circuit 40 are both connected to the DC bus, and the output side of the inverter circuit 40 is connected to the power grid 70 through the grid-connected port 60. The filter 50 is arranged between the output side of the inverter circuit 40 and the grid-connected port 60.

[0113] Among them, the inverter circuit 40 and the filter 50 can be selected accordingly according to the actual situation. For example, as shown in the first embodiment, when the power grid 70 is a three-phase power grid, the inverter circuit 40 can adopt a three-phase inverter circuit, and the filter 50 correspondingly adopts a three-phase filter to filter out the conducted interference and radiated interference on the three phase line output terminals A, B, and C on the grid-connected side of the inverter circuit 40. For another example, as shown in the second embodiment, when the power grid 70 is a single-phase power grid, the inverter circuit 40 can adopt a single-phase inverter circuit, and the filter 50 correspondingly adopts a single-phase filter to filter out the conducted interference and radiated interference on the phase line output terminal AC+ and the neutral line output terminal AC- on the grid-connected side of the inverter circuit 40.

[0114] It can be understood that the energy storage battery 20, the DC conversion circuit 30, the DC bus, the inverter circuit 40, the grid-connected port 60 and the filter 50 can all refer to the relevant descriptions in the above embodiments, which will not be repeated here.

[0115] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present application and are not intended to limit it. Although the present application has been described in detail with reference to the preferred embodiments, a person of ordinary skill in the art should understand that the technical solution of the present application may be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present application.

Claims

1. A filter, characterized in that: Applied to an inverter circuit, the input side of the inverter circuit is connected to a DC bus, and the output side of the inverter circuit is connected to a power grid through a grid-connected port; the filter comprises: a harmonic filter circuit, a filter magnetic ring, a common-mode inductor, a common-mode magnetic ring, a differential-mode magnetic ring, a differential-mode capacitor, and a common-mode capacitor; wherein, The harmonic filter circuit includes a filter inductor and a filter capacitor, wherein the filter inductor is connected between the output side of the inverter circuit and the grid-connected port and is also connected to the filter capacitor, and the filter inductor is also connected in series with the filter magnetic ring; The common-mode inductor is connected in series to one end of the filter inductor close to the grid-connected port, and the common-mode magnetic ring and the differential-mode magnetic ring are connected in series between the common-mode inductor and the grid-connected port; The filter inductor, the filter capacitor, the common-mode inductor, the output side of the inverter circuit, and the grid-connected port are respectively grounded through the corresponding common-mode capacitors, and the grid-connected port is connected to the differential-mode capacitor.

2. The filter according to claim 1, characterized in that The output side of the inverter circuit includes three phase line output terminals, the grid-connected port has three phase line terminals and one neutral line terminal, the three phase line terminals are connected to the three phase line output terminals one by one, and are connected to the three-phase lines of the power grid one by one, and the neutral line terminal is connected to the neutral line of the power grid; The harmonic filtering circuit comprises three filter inductors and three filter capacitors, each of the filter inductors is connected between one of the phase line output terminals of the inverter circuit and a corresponding phase line terminal of the grid-connected port, and the three filter inductors are also connected through corresponding filter capacitors respectively; Each of the phase line output terminals is grounded via the corresponding common mode capacitor, and each of the phase line wiring terminals is connected to the neutral line wiring terminal via the corresponding differential mode capacitor.

3. The filter according to claim 1, characterized in that The output side of the inverter circuit includes two output terminals, the grid-connected port has a phase line terminal and a neutral line terminal, the two output terminals are connected to the phase line terminal and the neutral line terminal in a one-to-one correspondence, the phase line terminal is connected to a phase line of the power grid, and the neutral line terminal is connected to the neutral line of the power grid; The harmonic filter circuit comprises two filter inductors and two filter capacitors, wherein one of the filter inductors is connected between one of the output terminals of the inverter circuit and the phase line terminal, and the other filter inductor is connected between the other output terminal of the inverter circuit and the neutral line terminal, and the two filter inductors are also connected through the corresponding filter capacitors respectively; The phase line output terminal and the neutral line output terminal are grounded respectively through the corresponding common mode capacitors, and the phase line wiring terminal and the neutral line wiring terminal are connected through the differential mode capacitor.

4. The filter according to claim 1, characterized in that The harmonic filter circuit also includes a power frequency inductor. The filter inductor, the common mode inductor and the power frequency inductor are sequentially connected in series. The filter capacitor is connected between the filter inductor and the power frequency inductor. The power frequency inductor is grounded through the corresponding common mode capacitor.

5. The filter according to claim 1, characterized in that The filter magnetic ring includes at least one of a first magnetic ring, a second magnetic ring and a third magnetic ring. The first magnetic ring and the second magnetic ring are both connected in series to an end of the filter inductor close to the inverter circuit, and the third magnetic ring is connected in series to an end of the filter inductor away from the inverter circuit. The first magnetic ring, the second magnetic ring and the third magnetic ring are all common mode magnetic rings, and act on different frequency bands respectively.

6. The filter according to claim 5, characterized in that One of the first magnetic ring, the second magnetic ring and the third magnetic ring is an amorphous nano magnetic ring, and the other two of the first magnetic ring, the second magnetic ring and the third magnetic ring are manganese zinc ferrite magnetic rings and nickel zinc ferrite magnetic rings respectively; the differential mode magnetic ring is an aluminum sendust magnetic ring.

7. The filter according to claim 1, characterized in that The common mode capacitor includes a main capacitor and an auxiliary capacitor, the main capacitor and the auxiliary capacitor are connected in parallel, and the capacitance value of the main capacitor is greater than the capacitance value of the auxiliary capacitor.

8. An inverter, characterized in that: The inverter comprises: an inverter circuit, a grid-connected port and a filter; The input side of the inverter circuit is connected to a DC bus, and the output side of the inverter circuit is connected to a power grid through the grid-connected port; The filter includes a harmonic filter circuit, a filter magnetic ring, a common mode inductor, a common mode magnetic ring, a differential mode magnetic ring, a differential mode capacitor and a common mode capacitor, wherein: The harmonic filter circuit includes a filter inductor and a filter capacitor, wherein the filter inductor is connected between the output side of the inverter circuit and the grid-connected port and is also connected to the filter capacitor, and the filter inductor is also connected in series with the filter magnetic ring; The common-mode inductor is connected in series to one end of the filter inductor close to the grid-connected port, and the common-mode magnetic ring and the differential-mode magnetic ring are connected in series between the common-mode inductor and the grid-connected port; The filter inductor, the filter capacitor, the common-mode inductor, the output side of the inverter circuit, and the grid-connected port are respectively grounded through the corresponding common-mode capacitors, and the grid-connected port is connected to the differential-mode capacitor.

9. The inverter according to claim 8, characterized in that: The inverter circuit is a three-phase two-level inverter circuit, which includes three inverter bridge arms, both ends of which are connected in parallel to the DC bus, and the midpoints of the three inverter bridge arms are used as phase line output ends, and are respectively connected one-to-one with the three phase line terminals of the grid-connected port, wherein each of the inverter bridge arms includes two switching tubes connected in series.

10. The inverter according to claim 8, characterized in that: The inverter circuit is a three-phase multi-level inverter circuit, and the inverter circuit includes three inverter bridge arms and three freewheeling bridge arms; both ends of the three inverter bridge arms are connected in parallel to the DC bus, and the midpoints of the three inverter bridge arms are used as phase line output ends, and are respectively connected to the three phase line terminals of the grid-connected port in a one-to-one correspondence, wherein each of the inverter bridge arms includes two half bridge arms connected in series, and the two half bridge arms each include two switch tubes connected in series; The three freewheeling bridge arms correspond one to one with the three inverter bridge arms, the two ends of each freewheeling bridge arm are respectively connected to the midpoints of the two half bridge arms in the corresponding inverter bridge arm, the midpoint of each freewheeling bridge arm is connected to the midpoint of the DC bus, and each freewheeling bridge arm includes two diodes connected in series.

11. The inverter according to claim 8, characterized in that: The inverter circuit is a three-phase multi-level inverter circuit, and the inverter circuit includes three inverter bridge arms and three freewheeling bridge arms; both ends of the three inverter bridge arms are connected in parallel to the DC bus, and the midpoints of the three inverter bridge arms are used as phase line output ends, and are respectively connected to the three phase line terminals of the grid-connected port in a one-to-one correspondence, wherein each of the inverter bridge arms includes two switch tubes connected in series; The three freewheeling bridge arms correspond one to one with the three inverter bridge arms, and the two ends of each freewheeling bridge arm are respectively connected to the midpoint of the corresponding inverter bridge arm and the midpoint of the DC bus, wherein each freewheeling bridge arm includes two switch tubes connected in reverse series.

12. The inverter according to claim 8, characterized in that: The inverter circuit is a single-phase inverter circuit, and the inverter circuit includes two inverter bridge arms, both ends of the two inverter bridge arms are connected in parallel to the DC bus, the midpoints of the two inverter bridge arms are used as output ends, and are respectively connected to the phase line terminal and the neutral line terminal of the grid-connected port in a one-to-one correspondence, wherein each of the inverter bridge arms includes two switching tubes connected in series.

13. The inverter according to claim 8, characterized in that: The inverter further includes a grid-connected switch, which is serially connected to an end of the filter inductor close to the grid-connected port, or to an end of the common-mode inductor far from the grid-connected port.

14. An energy storage device, characterized in that: The energy storage device includes an energy storage battery, a DC conversion circuit, a DC bus and an inverter, the inverter includes an inverter circuit, a grid-connected port and a filter, the energy storage battery is connected to the input end of the DC conversion circuit, the output end of the DC conversion circuit and the input side of the inverter circuit are both connected to the DC bus, and the output side of the inverter circuit is connected to the grid through the grid-connected port; wherein the filter is the filter according to any one of claims 1 to 7, or the inverter is the inverter according to any one of claims 8 to 13.

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