Miniaturized packaging structure of stacked chip unit

Abstract

The utility model discloses a miniaturized packaging structure of a stacked chip unit, which comprises a substrate, an FC chip arranged on the substrate, a WB chip stacked on the FC chip and a WB wire connecting the top surface of the WB chip and the substrate, a pit is arranged on the substrate, the FC chip is arranged at the bottom of the pit, and the WB wire is arranged on the substrate. A set glue overflow interval is arranged between the periphery of the FC chip and the inner wall of the pit. The method has the advantages that the thickness of the stacked chip unit is obviously reduced; the overflow of the bottom filling glue at the periphery of the FC chip is limited by the inner wall of the pit, so that the drop point of the WB can be closer to the FC chip, and the circumferential size of the chip unit is reduced; and the structure is simple, and the structural strength is equivalent to that of a traditional sealing glue structure after plastic packaging by the plastic packaging glue.

Description

Technical Field

[0001] The utility model relates to a miniaturized packaging structure of a stacked chip unit, belonging to the technical field of chip packaging. Background Art

[0002] When WB and FC chips are packaged in multi-chip form, multiple chips are packaged side by side or stacked on the substrate to form a chip unit. Stacked packaging usually involves an FC chip connected to the substrate by flip-chip, one or more WB chips are stacked on top of the FC chip, and the WB lines on the top surface of the WB chip are connected to the corresponding lines on the substrate.

[0003] Since the SIP package of the existing chip unit is that the fc chip is flipped on the substrate and then the WB chip is mounted on the fc chip, the packaging thickness of this structure is relatively large. At the same time, the fc chip needs to be filled with bottom glue. Due to the control of the overflow distance, the landing point of the WB line on the substrate needs to be far away from the fc chip, resulting in an increase in the length and width of the substrate.

[0004] In the production of existing stacked chip units, the FC chip is flipped on the substrate, and then the bottom is filled with glue after reflow soldering, and then the WB chip is mounted on the FC chip, and the WB wire bonding is performed. The wire bonding finger (the landing point on the substrate) needs to leave a certain overflow glue distance from the FC chip, and then plastic sealing is implemented (plastic sealing glue is injected into the packaging mold for overall packaging), and finally ball planting is performed on the bottom surface of the substrate (the connection point between each circuit in the substrate and the corresponding circuits of other components).

[0005] However, with the development of semiconductor technology, the chip unit package thickness is becoming smaller and smaller. However, the existing chip unit SIP package is as mentioned above, the fc chip is flipped on the substrate, and then the WB chip is mounted on the fc chip, and the package thickness and circumferential size are relatively large. Utility Model Content

[0006] The technical problem to be solved by the utility model is: how to miniaturize the chip unit.

[0007] In view of the above problems, the technical solution proposed by the utility model is:

[0008] A miniaturized packaging structure of a stacked chip unit comprises a substrate, an FC chip mounted on the substrate, a WB chip stacked on the FC chip, and a WB line connecting the top surface of the WB chip and the substrate. A pit is provided on the substrate, and the FC chip is mounted at the bottom of the pit.

[0009] Furthermore, there is a set glue overflow interval between the outer periphery of the FC chip and the inner wall of the pit.

[0010] Furthermore, there is bottom filling glue between the FC chip and the pit.

[0011] Furthermore, the bottom filling glue has a glue hanging slope at the periphery of the FC chip in the glue overflow interval, and there is a glue connection space between the glue hanging slope and the inner wall of the pit for final molding glue filling.

[0012] Furthermore, the connection point of the WB line on the substrate is at the edge of the pit.

[0013] Furthermore, it also includes solder balls for connecting the chip unit circuit with other component circuits, and the solder balls are implanted in the circuit terminals at the bottom of the substrate.

[0014] Furthermore, there are two WB chips, which are respectively arranged at two ends of the upper surface of the FC chip. Beneficial Effects

[0015] 1. Significantly reduced the thickness of the stacked chip unit;

[0016] 2. The overflow of the bottom filling glue around the FC chip is limited by the inner wall of the pit, so that the WB line can be closer to the FC chip, thereby reducing the circumferential size of the chip unit;

[0017] 3. The structure is simple, and after being sealed with plastic sealant, it has a structural strength comparable to that of the traditional sealing structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A partial cross-sectional schematic diagram of the packaging structure of the miniaturized stacked chip unit after packaging;

[0019] Figure 2 is a schematic cross-sectional view of the substrate;

[0020] Figure 3 The cross-sectional schematic diagram is a diagram of installing an FC chip in the recess of the substrate and injecting glue to form bottom filling glue.

[0021] In the figure: 1. FC chip; 2. WB chip; 3. WB line; 4. substrate; 401. pit; 5. overflow glue interval; 6. bottom filling glue; 601. glue hanging slope; 7. glue connection space; 8. plastic sealing glue; 9. solder ball. DETAILED DESCRIPTION

[0022] The present invention will be further described below in conjunction with the embodiments and drawings: Embodiment 1

[0023] like Figure 1As shown in FIG. 3 , a miniaturized packaging structure of a stacked chip unit includes a substrate 4, an FC chip 1 mounted on the substrate 4, a WB chip 2 stacked on the FC chip 1, and a WB line 3 connecting the top surface of the WB chip 2 and the substrate 4, characterized in that: a pit 401 is provided on the substrate 4, and the FC chip 1 is mounted at the bottom of the pit 401. In this way, the bottom FC chip 1 can be sunk on the substrate 4, thereby significantly reducing the thickness of the entire stacked chip unit, and effectively realizing the miniaturization of the entire chip unit.

[0024] like Figure 2 , 3 As shown, there is a set glue overflow interval 5 between the outer periphery of the FC chip 1 and the inner wall of the pit 401. This arrangement allows the glue overflow to be limited by the inner wall of the pit 401 when the FC chip 1 is pre-fixed, and the circumferential size of the entire stacked chip unit can be minimized.

[0025] There is a bottom filling glue 6 between the FC chip 1 and the pit 401 for pre-fixing the FC chip to facilitate the subsequent stacking of the WB chip 2 .

[0026] The bottom filling glue 6 has a glue hanging slope 601 on the periphery of the FC chip 1 in the glue overflow interval 5, and there is a glue connection space 7 for the final filling of the plastic sealant 8 between the glue hanging slope 601 and the inner wall of the pit 401. In this way, the bonding between the plastic sealant 8 and the glue hanging slope 601 of the bottom filling glue 6 can be increased to have a larger glue connection surface, and the structural strength of the plastic sealant 8 and the bottom filling glue 6 is strengthened. At the same time, when plastic sealing is implemented, a part of the plastic sealant 8 is located in the glue connection space 7, which also enhances the integrity between the plastic sealant 8 and the substrate 4.

[0027] like Figure 1 As shown, the connection point of the WB line 3 on the substrate 4 is at the edge of the pit 401, so that the connection point can be as close to the FC chip 1 as possible, thereby reducing the circumferential size of the chip unit.

[0028] It also includes solder balls 9 for connecting the chip unit circuit with other component circuits. The solder balls 9 are implanted in the circuit terminals at the bottom of the substrate 4 .

[0029] There are two WB chips 2, which are respectively arranged at two ends of the upper surface of the FC chip.

[0030] The above embodiments are only used to more clearly describe the present invention and cannot be regarded as limiting the protection scope of the present invention. Any modifications in equivalent forms should be regarded as falling within the protection scope of the present invention.

Claims

1. A miniaturized packaging structure of a stacked chip unit, comprising a substrate (4), an FC chip (1) mounted on the substrate (4), a WB chip (2) stacked on the FC chip (1), and a WB line (3) connecting the top surface of the WB chip (2) and the substrate (4), characterized in that: A pit (401) is provided on the substrate (4), and the FC chip (1) is mounted at the bottom of the pit (401).

2. The miniaturized packaging structure of stacked chip units according to claim 1, characterized in that: There is a set glue overflow interval (5) between the outer periphery of the FC chip (1) and the inner wall of the pit (401).

3. The miniaturized packaging structure of stacked chip units according to claim 2, characterized in that: There is bottom filling glue (6) between the FC chip (1) and the pit (401).

4. The miniaturized packaging structure of stacked chip units according to claim 3, characterized in that: The bottom filling glue (6) has a glue hanging inclined surface (601) on the periphery of the FC chip (1) in the glue overflow interval (5), and a glue connection space (7) for final filling of the plastic sealing glue (8) is provided between the glue hanging inclined surface (601) and the inner wall of the pit (401).

5. The miniaturized packaging structure of the stacked chip unit according to any one of claims 1 to 4, characterized in that: The connection point of the WB line (3) on the substrate (4) is at the edge of the pit (401).

6. The miniaturized packaging structure of the stacked chip unit according to any one of claims 1 to 4, characterized in that: It also includes a solder ball (9) for connecting the chip unit circuit with other component circuits, and the solder ball (9) is implanted on the circuit terminal at the bottom of the substrate (4).

7. The miniaturized packaging structure of the stacked chip unit according to any one of claims 1 to 4, characterized in that: There are two WB chips (2), which are respectively arranged at two ends of the upper surface of the FC chip.

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