External circuit structure of heat dissipation packaging chip with exposed top surface
By setting the wire grooves and etching surfaces on the outer periphery of the chip to accommodate external conductors, effective heat dissipation and sealant coverage of the exposed heat dissipation packaging chip on the top surface is achieved, and the problem of difficulty in heat dissipation in traditional packaging structures is solved.
Patent Information
- Application Number
- CN202420497013.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-14
- Publication Date
- 2025-03-04
- Estimated Expiration
- 2034-03-14
AI Technical Summary
The traditional thick film full-wrap plastic-encapsulated power management chip packaging structure makes it difficult for the chip to dissipate heat during operation, which in turn affects the chip performance and load capacity.
An external circuit structure for exposed heat dissipation chip on the top surface is designed. By setting a wire groove leading to the bottom surface of the soldering plate on the outer periphery of the chip, and opening a wire groove on the etching surface to accommodate the external wires, the sealant can cover the external wires.
The heat dissipation performance of the chip is improved while ensuring that the sealant can cover the external conductors, thus solving the problem of difficulty in heat dissipation in traditional packaging structures.
Smart Images
Figure CN222562682U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to an external circuit structure of a heat dissipation package chip with an exposed top surface, belonging to the technical field of chip packaging. Background Art
[0002] The traditional power management chip packaging structure is a thick-film fully wrapped plastic package. The chip is deeply buried in the sealing layer, which makes it difficult to dissipate the heat generated when the chip is running, thereby causing technical problems such as reduced chip performance, reduced load capacity, and weakened transistor conduction ability.
[0003] The reason for using thick film fully wrapped plastic encapsulated power management chip is that the upper surface of the power management chip has multiple external circuit welding pads. The wires welded on the welding pads are bent downward and connected to the circuit on the substrate. Since the upper end of the wire is welded to the welding pad on the upper surface of the welding pad, and the welding pad is located on the upper surface of the chip, the upper section of the wire must be higher than the upper surface of the chip. The main purpose of chip packaging is to encapsulate the external wires to avoid exposing the external wires. In this way, when the sealing glue covers the wires, it naturally causes deep coverage of the upper surface of the chip to form a thick film package. Utility Model Content
[0004] The technical problem to be solved by the utility model is: for a chip packaged in a top surface exposed heat dissipation manner, how to arrange its external connecting wires so that the external connecting wires can be covered by sealing glue during packaging.
[0005] In view of the above problems, the technical solution proposed by the utility model is:
[0006] The invention discloses an external circuit structure of a packaged chip with a top surface exposed for heat dissipation. The welding pads of each external circuit of the chip are arranged in a rectangular shape on the top surface area of a pure wafer body without an internal circuit structure at the periphery of the chip. A wire groove for accommodating external wires is provided at the periphery of the chip and leads to the bottom surface of the welding pad. The upper end of the external wire connected to the substrate at the lower end is connected to the welding pad at the bottom surface of the welding pad through the wire groove.
[0007] The chip periphery other than the rectangularly arranged welding pads is etched to form four etching surfaces, the rear end surface of each welding pad is located on the corresponding etching surface, and the wire groove is opened on the etching surface.
[0008] The etching surface is located on the upper part of the chip.
[0009] The etching surface is a quadrangular pyramidal surface, the upper section of the externally connected wire is located in the wire groove, and the lower section is located outside the chip.
[0010] The etching surface is a rectangular surface, and the periphery of the chip below the four rectangular etching surfaces forms a receiving platform. A secondary welding pad is arranged on the receiving platform corresponding to the welding pad. The external wires are divided into primary wires and secondary wires. The upper section of the primary wire is connected to the welding pad through a wire groove, and the lower end is connected to the secondary welding pad outside the chip. The secondary wire connects the secondary welding pad and the corresponding circuit on the substrate outside the chip.
[0011] The wire groove arranged on the etching surface is extended toward the secondary welding plate on the receiving platform so that all the primary wires are located in the wire groove.
[0012] The primary conductor is a conductive circuit plated in the conductor slot by using a wafer-level electroplating method. Beneficial Effects
[0013] While exposing the top surface of the packaged chip to improve heat dissipation performance, the sealing glue can cover the external wires. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 This is a top view of the chip before packaging described in Example 1;
[0015] Figure 2 It is a partial cross-sectional schematic diagram of the chip packaged in the first embodiment;
[0016] Figure 3 It is a partial cross-sectional schematic diagram of the chip packaged in the second embodiment;
[0017] Figure 4 It is a partial cross-sectional schematic diagram of the chip packaged in the third embodiment;
[0018] Figure 5 It is a partial cross-sectional schematic diagram of the chip packaged in the fourth embodiment;
[0019] Figure 6 It is a partial cross-sectional schematic diagram of a chip package in the prior art.
[0020] In the figure: 1. chip; 101. etching surface; 102. receiving platform; 103. wire groove; 2. external wire; 201. primary wire; 202. secondary wire; 3. welding pad; 4. secondary welding pad; 5. substrate; 6. sealing glue; 7. copper pad; 8. silver paste glue. DETAILED DESCRIPTION
[0021] The utility model is further described below in conjunction with the accompanying drawings: Embodiment 1
[0022] like Figure 1—3 shows an external circuit structure of a packaged chip with exposed top surface for heat dissipation, the improvement of which is that the welding pads 3 of each external circuit of the chip 1 are arranged in a rectangular shape on the top surface area of a pure wafer body without an internal circuit structure at the periphery of the chip, and a wire groove 103 for accommodating an external wire 2 is provided at the periphery of the chip 1 leading to the bottom surface of the welding pad 3, and the upper end of the external wire 2 connected to the substrate 5 at the bottom surface of the welding pad is connected to the welding pad 3 through the wire groove 103. In this way, since the external wire 2 is lower than the top surface of the chip 1, when the top surface of the packaged chip 25 exposes the sealing glue layer, the sealing glue 6 packaged at the periphery of the chip 25 can cover the external wire 2.
[0023] The chip periphery other than the rectangularly arranged welding pads 3 is etched to form four etching surfaces 101 , and the rear end surface of each welding pad 3 is located on the corresponding etching surface 101 , and the wire groove 103 is opened on the etching surface 101 , so that the groove depth of the wire groove 103 can be reduced.
[0024] The etched surface 101 is located on the upper part of the chip 1, so that the original size of the base of the chip 1 can be maintained, which facilitates the placement and fixation of the chip on the substrate.
[0025] In this embodiment, the etching surface 101 is a quadrangular pyramidal surface. The upper section of the external wire 2 is located in the wire groove 103, and the lower section is located outside the chip 1. This structure is relatively simple.
[0026] When the chip 1 described in the present application is packaged, according to normal requirements, the chip 1 needs to be raised with a copper pad 7 so that the total packaging height of the sealing glue 6 reaches the height required by the customer. Silver paste 8 with good thermal conductivity is preferably used between the copper pad 7 and the substrate 5, and between the copper pad 7 and the chip 1. Embodiment 2
[0027] The difference between the embodiment 1 and the embodiment 1 is that the etching surface 101 is a rectangular surface, and a receiving platform 102 is formed on the periphery of the chip below the four rectangular etching surfaces 101. A secondary welding pad 4 is arranged on the receiving platform 102 corresponding to the welding pad 3. The external wire 2 is divided into a primary wire 201 and a secondary wire 202. The upper section of the primary wire 201 is connected to the welding pad 3 through a wire groove 103, and the lower end is connected to the secondary welding pad 4 outside the chip 1. The secondary wire 202 is connected to the secondary welding pad 4 and the corresponding circuit on the substrate 5 outside the chip 1.
[0028] The significance of such an arrangement is that the production of the chip 1 may be completed by multiple manufacturers in relay. The upstream manufacturer may complete the product only to the point where the primary external wire 2 connects the welding pad 3 and the secondary welding pad 25 before packaging. The remaining steps of connecting the secondary external wire 2 to the secondary welding pad 4 and the corresponding circuit on the substrate 5 and the packaging step are completed by the downstream manufacturer. Embodiment 3
[0029] As an option, the difference from the second embodiment is that the wire groove 103 provided on the etching surface 101 is extended on the receiving platform 102 toward the secondary welding pad 4 so that the primary wire 201 is completely located in the wire groove 103 . Embodiment 4
[0030] As an option, the difference from the above embodiment is that the primary conductor 201 is a conductive circuit plated in the conductor groove 103 by wafer-level electroplating.
[0031] The above embodiments are only used to more clearly describe the present invention and cannot be regarded as limiting the protection scope of the present invention. Any modifications in equivalent forms should be regarded as falling within the protection scope of the present invention.
Claims
1. An external circuit structure of a packaged chip with a top surface exposed for heat dissipation, characterized in that: The welding pads (3) of each external circuit of the chip (1) are arranged in a rectangular shape on the top surface area of a pure wafer body without an internal circuit structure at the periphery of the chip. A wire groove (103) for accommodating an external wire (2) is provided at the periphery of the chip (1) and leads to the bottom surface of the welding pad (3). The upper end of the external wire (2) connected to the substrate (5) at the bottom surface of the welding pad is connected to the welding pad (3) through the wire groove (103).
2. The external circuit structure of the top surface exposed heat dissipation package chip according to claim 1, characterized in that: The chip periphery other than the rectangularly arranged welding pads (3) is etched to form four etching surfaces (101), the rear end surface of each welding pad (3) is located on the corresponding etching surface (101), and the wire groove (103) is opened on the etching surface (101).
3. The external circuit structure of the top surface exposed heat dissipation package chip according to claim 2, characterized in that: The etched surface (101) is located on the upper part of the chip (1).
4. The external circuit structure of the top surface exposed heat dissipation package chip according to claim 3, characterized in that: The etching surface (101) is a quadrangular pyramidal surface; the upper section of the external wire (2) is located in the wire groove (103), and the lower section is located outside the chip (1).
5. The external circuit structure of the top surface exposed heat dissipation package chip according to claim 3, characterized in that: The etching surface (101) is a rectangular surface. The outer periphery of the chip below the four rectangular etching surfaces (101) forms a receiving platform (102). A secondary welding pad (4) is arranged on the receiving platform (102) corresponding to the welding pad (3). The external connection wire (2) is divided into a primary wire (201) and a secondary wire (202). The upper section of the primary wire (201) is connected to the welding pad (3) through a wire groove (103), and the lower end is connected to the secondary welding pad (4) outside the chip (1). The secondary wire (202) is connected to the secondary welding pad (4) and a corresponding circuit on the substrate (5) outside the chip (1).
6. The external circuit structure of the top surface exposed heat dissipation package chip according to claim 5, characterized in that: The wire groove (103) provided on the etching surface (101) is extended toward the secondary welding plate (4) on the receiving platform (102), so that the primary wire (201) is completely located in the wire groove (103).
7. The external circuit structure of the top surface exposed heat dissipation package chip according to claim 5, characterized in that: The primary conductor (201) is a conductive circuit plated in the conductor slot (103) using a wafer-level electroplating method.