MOS chip packaging structure

Abstract

According to the MOS chip packaging structure provided by the invention, the two MOS chips are packaged in a back-to-back manner, so that the current conduction path is shortened, the electrical performance of a product is improved, and the packaging size of the product is reduced while the two MOS chips are sealed together.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor packaging technology and, in particular, to a MOS chip packaging structure. Background Art

[0002] As the application scope of MOS power devices gradually expands in various industries, the demand for miniaturization of package size gradually increases while the performance of products is improved. The improvement of product performance is accompanied by an increase in chip area, so it is impossible to meet product requirements.

[0003] In the prior art, the packaging of MOS chips is to space each chip and connect it with the pins. This packaging method has a large packaging size for the overall product and cannot achieve miniaturization design. Summary of the invention

[0004] In order to solve or alleviate the problems in the prior art, the present application provides a MOS chip packaging structure, which is a new packaging structure developed based on wafer-level packaging technology, which improves performance while reducing the packaging size of the product.

[0005] The present application provides a MOS chip packaging structure, including a first MOS chip and a second MOS chip;

[0006] The back side of the first MOS chip is connected to the back side of the second MOS chip through a first conductive layer;

[0007] The front side of the first MOS tube is connected to the wiring layer through the first electrode lead-out layer, and the front side of the second MOS tube is connected to the pin through the second electrode lead-out layer;

[0008] The wiring layer and the pin are connected via a second conductive layer;

[0009] A plastic package is arranged around the wiring layer, the pins, the first MOS chip and the second MOS chip.

[0010] As a preferred embodiment of the present application, the first conductive layer is a conductive adhesive, and the second conductive layer is a metal layer.

[0011] As a preferred embodiment of the present application, the first electrode lead-out layer and the second electrode lead-out layer are both conductive metal balls.

[0012] Compared with the prior art, the MOS chip packaging structure provided in the embodiment of the present application shortens the current conduction path and increases the electrical performance of the product by packaging two MOS chips back to back. While sealing the two MOS chips, the packaging size of the product is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. Some specific embodiments of the present application will be described in detail in an illustrative and non-restrictive manner with reference to the drawings. The same reference numerals in the drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the drawings:

[0014] Figure 1 It is a structural schematic diagram of a MOS chip packaging structure provided by the present application. DETAILED DESCRIPTION

[0015] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only embodiments of a part of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present application.

[0016] like Figure 1 As shown, an embodiment of the present application provides a MOS chip packaging structure, including a first MOS chip 1 and a second MOS chip 2;

[0017] The back side of the first MOS chip 1 is connected to the back side of the second MOS chip 2 via a first conductive layer 3;

[0018] The front side of the first MOS tube is connected to the wiring layer 6 through the first electrode lead-out layer 5, and the front side of the second MOS tube is connected to the pin 7 through the second electrode lead-out layer 4;

[0019] The wiring layer 6 and the pin 7 are connected via a second conductive layer 9;

[0020] A plastic package 8 is disposed around the wiring layer 6 , the pins 7 , the first MOS chip 1 and the second MOS chip 2 .

[0021] In the embodiment of the present application, the first conductive layer 3 is a conductive adhesive, and the second conductive layer 9 is a metal layer.

[0022] In the embodiment of the present application, the first electrode lead-out layer 5 and the second electrode lead-out layer 4 are both conductive metal balls.

[0023] The following is a packaging process of a MOS chip packaging structure provided by this application, and the specific steps are as follows:

[0024] 1. The first electrode lead layer 5 is arranged on the front side of the first MOS chip 1 by means of a ball planting process, and the second electrode lead layer 4 is arranged on the front side of the second MOS chip 2 by means of a ball planting process;

[0025] 2. Fix the second MOS chip 2 on the carrier board;

[0026] 3. Encapsulate the second MOS chip 2 and the second electrode lead-out layer 4 with a plastic package 8;

[0027] 4. Grinding and exposing the second electrode lead-out layer 4 through a grinding process;

[0028] 5. Electroplating the second electrode lead layer 4 onto the pin 7;

[0029] 6. Use the plastic package 6 to plasticize all the pins 7;

[0030] 7. Remove the carrier board to expose the back side of the second MOS chip 2;

[0031] 8. Connect the back side of the second MOS chip 2 to the back side of the first MOS chip 1 through the first conductive layer 3;

[0032] 9. Use a plastic package 8 to plastic-package the first MOS chip 1 and the first electrode lead-out layer 5;

[0033] 10. Grinding and exposing the first electrode lead-out layer 5 through a grinding process;

[0034] 11. Electroplating the wiring layer 6 onto the first electrode lead-out layer 5, connecting the wiring layer 6 to the pin 7 through the second conductive layer 9 to form a conducting circuit;

[0035] 12. Cover the entire device with a plastic package 6;

[0036] 13. Cut the plastic-encapsulated devices into single chips based on each chip;

[0037] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A MOS chip packaging structure, characterized in that: comprising a first MOS chip and a second MOS chip; The back side of the first MOS chip is connected to the back side of the second MOS chip through a first conductive layer; The front side of the first MOS chip is connected to the wiring layer through the first electrode lead-out layer, and the front side of the second MOS chip is connected to the pin through the second electrode lead-out layer; The wiring layer and the pin are connected via a second conductive layer; A plastic package is arranged around the wiring layer, the pins, the first MOS chip and the second MOS chip.

2. A MOS chip packaging structure as claimed in claim 1, characterized in that: The first conductive layer is conductive glue, and the second conductive layer is a metal layer.

3. A MOS chip packaging structure as claimed in claim 2, characterized in that: The first electrode lead-out layer and the second electrode lead-out layer are both conductive metal balls.

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