Pixel array chip

Abstract

The utility model relates to the field of semiconductor devices, and discloses a pixel array chip. The pixel array chip comprises a driving substrate which comprises a circuit layer and a first bonding layer located on the surface of one side of the circuit layer; the epitaxial assembly comprises a pixel function layer, a composite bonding layer located on the side where the first surface of the pixel function layer is located and a plurality of cathode electrodes located on the second surface of the pixel function layer, the composite bonding layer is in bonding connection with the first bonding layer at the room temperature, and the pixel function layer comprises a plurality of pixel function units arranged in an array; each pixel function unit comprises a P-type semiconductor layer, an active layer and an N-type semiconductor layer which are sequentially arranged in a stacked mode, each cathode electrode is electrically connected with the N-type semiconductor layer of the corresponding pixel function unit on the second surface, and the cathode electrodes penetrate through the pixel function layers, the composite bonding layer and the first bonding layer to be electrically connected with the circuit layer. According to the pixel array chip provided by the embodiment of the invention, the pixel function units can be electrically connected with the driving substrate through a simpler structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor devices, and in particular to a pixel array chip. Background Art

[0002] Micro Light Emitting Diode (Micro-LED) display chips are considered to be the most suitable micro-display chips for augmented reality (AR) applications due to their high stability and high brightness.

[0003] At present, in the manufacturing process of Micro-LED display chips, the driving substrate and the epitaxial component are bonded to each other to realize the circuit connection between the epitaxial component and the driving substrate. The epitaxial component includes multiple pixel functional units, each of which includes a P-type semiconductor layer, an active layer, and an N-type semiconductor layer stacked in sequence. Since the P-type semiconductor layer and the N-type semiconductor layer are located on both sides of the active layer, one of them faces the driving substrate and the other faces away from the driving substrate. For example, the P-type semiconductor layer faces the driving substrate and the N-type semiconductor layer faces away from the driving substrate. Therefore, in the prior art, it is necessary to set an additional electrical connection structure on the side of the epitaxial component away from the driving substrate to realize the electrical connection between the N-type semiconductor layer of each pixel functional unit and the driving substrate, which makes the chip structure more complicated. Utility Model Content

[0004] The present application provides a pixel array chip that can realize electrical connection between a pixel functional unit and a driving substrate with a more streamlined structure.

[0005] An embodiment of the present application provides a pixel array chip, which includes: a driving substrate, including a circuit layer and a first bonding layer located on one side surface of the circuit layer; an epitaxial component, including a pixel function layer, a composite bonding layer located on the side where the first surface of the pixel function layer is located, and a plurality of cathode electrodes located on the second surface of the pixel function layer, the second surface is opposite to the first surface, the composite bonding layer is bonded to the first bonding layer at room temperature, the pixel function layer includes a plurality of pixel function units arranged in an array, each of the pixel function units includes a P-type semiconductor layer, an active layer, and an N-type semiconductor layer stacked in sequence, each of the cathode electrodes is electrically connected to the N-type semiconductor layer corresponding to a pixel function unit on the second surface, and the cathode electrode is electrically connected to the circuit layer through the pixel function layer, the composite bonding layer, and the first bonding layer.

[0006] According to the pixel array chip of the embodiment of the present application, the driving substrate includes a circuit layer and a first bonding layer located on one side of the circuit layer, and the epitaxial component includes a pixel function layer and a composite bonding layer located on the side where the first surface of the pixel function layer is located. The composite bonding layer is bonded to the first bonding layer at room temperature, thereby realizing the bonding connection between the driving substrate and the epitaxial component. Since the bonding process is carried out at room temperature, the influence of the stress fluctuation of the epitaxial component on the heating and cooling process is avoided, thereby reducing the performance of the epitaxial component damaged by the bonding process, that is, reducing the influence of the bonding process on the performance of the pixel array chip. Each cathode electrode is electrically connected to the N-type semiconductor layer corresponding to a pixel function unit on the second surface, and the cathode electrode is electrically connected to the circuit layer through the pixel function layer, the composite bonding layer and the first bonding layer, thereby realizing the electrical connection between the electrode on the side away from the driving substrate in each pixel function unit and the driving substrate. The above structure does not need to set an additional electrical connection structure on the side where the second surface of the pixel function layer is located, thereby simplifying the chip structure of the pixel array chip and avoiding the shielding of the pixel function unit by the additional electrical connection structure.

[0007] According to the aforementioned embodiment of the present application, each of the pixel functional units has a polygonal structure, each of the pixel functional units has a non-functional area on the periphery, each of the cathode electrodes is electrically connected to the corresponding pixel functional unit at the corner position of the corresponding pixel functional unit, and the cathode electrode extends to the non-functional area.

[0008] According to any of the foregoing embodiments of the present application, the circuit layer includes a plurality of cathode electrical connection portions corresponding to the plurality of cathode electrodes, and the pixel array chip includes: a plurality of vias, each of the vias extending from the second surface to the corresponding cathode electrical connection portion, the cathode electrode being at least partially located within the corresponding via; and a passivation layer, located at least between the cathode electrode and the side wall of the via.

[0009] According to any of the aforementioned embodiments of the present application, the N-type semiconductor layer of each of the pixel functional units includes a thinning area and a non-thinning area, and the thinning area is thinned from the second surface to the first surface relative to the non-thinning area, and each of the cathode electrodes covers the thinning area corresponding to the pixel functional unit and extends to part of the non-thinning area of ​​the adjacent pixel functional unit, and the passivation layer is also located between the cathode electrode and the non-thinning area of ​​the adjacent pixel functional unit.

[0010] According to any of the aforementioned embodiments of the present application, the thinning thickness value of the thinning zone is 1 / 5 to 2 / 3 of the thickness of the non-thinning zone.

[0011] According to any of the foregoing embodiments of the present application, the thickness of the cathode electrode above the second surface is 0.3 um to 3 um.

[0012] According to any of the foregoing embodiments of the present application, the passivation layer includes at least one of TaN, SiO, SiN, Si, SINO, AlO, AlN or AlNO; and the cathode electrode includes at least one of W, Al, Ag, Au, Cu, Ta or Ti.

[0013] According to any of the foregoing embodiments of the present application, the pixel array chip further includes: a packaging layer, the packaging layer is bonded to the second surface of the pixel function layer by a bonding adhesive, and the packaging layer and the bonding adhesive cover the multiple cathode electrodes.

[0014] According to any of the foregoing embodiments of the present application, the pixel array chip is a micro light emitting diode display chip, and the pixel function unit is a micro light emitting diode unit.

[0015] According to any of the foregoing embodiments of the present application, the pixel array chip is an image acquisition chip, and the pixel function unit is an electro-optical conversion unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0017] Figure 1 A cross-sectional schematic diagram of a driving substrate having a circuit layer is provided in an embodiment of a method for manufacturing a pixel array chip of the present application;

[0018] Figure 2 This is a cross-sectional schematic diagram of forming a first bonding layer on a surface of one side of a circuit layer of a driving substrate in an embodiment of a method for manufacturing a pixel array chip of the present application;

[0019] Figure 3 A cross-sectional schematic diagram of an epitaxial component having a pixel function layer is provided in an embodiment of a method for manufacturing a pixel array chip of the present application;

[0020] Figure 4 This is a cross-sectional schematic diagram of forming a first sub-bonding layer in an embodiment of a method for manufacturing a pixel array chip of the present application;

[0021] Figure 5 A cross-sectional schematic diagram of forming a second sub-bonding layer in an embodiment of a method for manufacturing a pixel array chip of the present application;

[0022] Figure 6A cross-sectional schematic diagram of bonding the composite bonding layer to the first bonding layer at room temperature in an embodiment of a method for manufacturing a pixel array chip of the present application;

[0023] Figure 7 This is a cross-sectional schematic diagram of peeling off the substrate and removing the buffer layer in an embodiment of the method for manufacturing the pixel array chip of the present application;

[0024] Figure 8 A schematic cross-sectional view of patterning a pixel function layer to form a plurality of pixel function units arranged in an array on the pixel function layer in an embodiment of a method for manufacturing a pixel array chip of the present application;

[0025] Fig. 9 A cross-sectional schematic diagram of forming a thinned region in an N-type semiconductor layer of each pixel functional unit in an embodiment of a method for manufacturing a pixel array chip of the present application;

[0026] Fig.10 A cross-sectional schematic diagram of forming a plurality of via holes in an embodiment of a method for manufacturing a pixel array chip of the present application;

[0027] Fig.11 A cross-sectional schematic diagram of forming a passivation layer in an embodiment of a method for manufacturing a pixel array chip of the present application;

[0028] Fig.12 A cross-sectional schematic diagram of forming a plurality of cathode electrodes in an embodiment of a method for manufacturing a pixel array chip of the present application;

[0029] Fig.13 This is a cross-sectional schematic diagram of forming a packaging layer in an embodiment of a method for manufacturing a pixel array chip of the present application;

[0030] Fig.14 A schematic top view of an embodiment of a pixel array chip of the present application;

[0031] Fig.15 This is a top view schematic diagram of an alternative embodiment of the pixel array chip of the present application.

[0032] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0034] It should be noted that all directional indications in the embodiments of the present application, such as up, down, left, right, front, back, etc., are only used to explain the relative position relationship, movement, etc. between the components in a certain specific posture as shown in the accompanying drawings. If the specific posture changes, the directional indication will also change accordingly. When describing the structure of a component, when a layer or an area is referred to as being "above" or "above" another layer or another area, it may refer to being directly above another layer or another area, or containing other layers or areas between it and another layer or another area. Furthermore, if the component is turned over, the layer or the area will be "below" or "below" another layer or another area.

[0035] In addition, the descriptions of "first", "second", etc. in this application are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. The terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "include..." do not exclude the existence of other identical elements in the process, method, article or device including the elements. In addition, the technical solutions between the various embodiments can be combined with each other, but must be based on the ability of ordinary technicians in the field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that the combination of such technical solutions does not exist and is not within the scope of protection required by this application.

[0036] The embodiment of the present application provides a pixel array chip and a method for manufacturing the same. The pixel array chip may be a micro-light emitting diode (Micro-LED) display chip, which includes a plurality of micro-light emitting diode units (i.e., photoelectric conversion units). The pixel array chip may also be an image acquisition chip, which includes a plurality of electro-optical conversion units.

[0037] Hereinafter, an embodiment of a pixel array chip and a manufacturing method thereof will be described mainly by taking a pixel array chip as a Micro-LED display chip as an example.

[0038] The following will be combined with the attached Figures 1 to 13 , an embodiment of a method for manufacturing a pixel array chip is described. The method for manufacturing a pixel array chip includes steps S101 to S113.

[0039] In step S101 , a driving substrate 200 having a circuit layer 210 is provided. Figure 1 A cross-sectional schematic diagram of a driving substrate having a circuit layer is provided in one embodiment of a method for manufacturing a pixel array chip of the present application.

[0040] The circuit layer 210 of the driving substrate 200 includes a driving unit. In this embodiment, the driving substrate 200 is a complementary metal oxide semiconductor (CMOS) driving substrate, that is, in the circuit layer 210 of the driving substrate 200, the driving unit includes a CMOS transistor.

[0041] In step S102 , a first bonding layer 220 is formed on a surface of the circuit layer 210 of the driving substrate 200 . Figure 2 This is a cross-sectional schematic diagram of forming a first bonding layer on a surface of one side of a circuit layer of a driving substrate in an embodiment of a method for manufacturing a pixel array chip of the present application.

[0042] The first bonding layer 220 may be made of a metal material or a non-metal material, such as Cu, Al, Au, Ag, Ta or Ti, or PI, PDMS, silicon, silicon nitride, silicon oxide or silicon oxynitride, etc. Preferably, the first bonding layer 220 is silicon, silicon oxide, silicon nitride or the like.

[0043] In some embodiments, the first bonding layer 220 is at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0044] In this embodiment, the first bonding layer 220 is preferably a SiO2 layer with a thickness of 30 nm to 1000 nm. Further, the first bonding layer 220 is preferably a SiO2 layer with a thickness of 500 nm.

[0045] In one example, step S102 includes: depositing a 2000nm thick SiO2 layer on one surface of the circuit layer 210 of the driving substrate 200 by a chemical vapor deposition (CVD) process, and then thinning the SiO2 layer and performing chemical-mechanical planarization (CMP) to obtain a first bonding layer 220 with a thickness of 500nm and a flatness within 10nm.

[0046] In step S103 , an epitaxial component 100 having a pixel function layer 110 is provided. Figure 3 A cross-sectional schematic diagram of an epitaxial component having a pixel function layer is provided in one embodiment of a method for manufacturing a pixel array chip of the present application.

[0047] In some embodiments, step S103 of providing an epitaxial component 100 having a pixel function layer 110 includes: providing a substrate 191; forming a buffer layer 192 on the substrate 191; and sequentially forming a P-type semiconductor layer 111, an active layer 112, and an N-type semiconductor layer 113 on the buffer layer 192. In this embodiment, the active layer 112 is a multiple quantum well (MQW) layer.

[0048] In step S104 , a first sub-bonding layer 121 is formed on the side where the first surface S1 of the pixel function layer 110 of the epitaxial component 100 is located, and the first sub-bonding layer 121 is a conductive layer. Figure 4 This is a cross-sectional schematic diagram of forming a first sub-bonding layer in an embodiment of a method for manufacturing a pixel array chip of the present application.

[0049] In some embodiments, before step S104 of forming the first sub-bonding layer 121 on the side where the first surface S1 of the pixel function layer 110 of the epitaxial component 100 is located, the method for manufacturing the pixel array chip further includes: forming an ohmic contact layer (not shown) on the side of the P-type semiconductor layer 111 away from the N-type semiconductor layer 113. At this time, step S104 of forming the first sub-bonding layer 121 on the side where the first surface S1 of the pixel function layer 110 of the epitaxial component 100 is located includes: forming the first sub-bonding layer 121 on the side of the ohmic contact layer away from the P-type semiconductor layer 111.

[0050] The ohmic contact layer is formed of a material that forms a good ohmic contact with the P-type semiconductor layer 111, preferably Ni or indium tin oxide (ITO), etc. In this embodiment, the ohmic contact layer is preferably ITO with a thickness of 10nm to 200nm, and further, the ohmic contact layer is preferably ITO with a thickness of 50nm.

[0051] In one example, the step of forming an ohmic contact layer on the side of the P-type semiconductor layer 111 away from the N-type semiconductor layer 113 includes: after forming an ITO layer on the side of the P-type semiconductor layer 111 away from the N-type semiconductor layer 113, placing the epitaxial component 100 into a high temperature quenching annealing (RTA) device, and performing rapid annealing at 650°C for 1 min to form a better ohmic contact.

[0052] The first sub-bonding layer 121 is a conductive layer, for example, including metal conductive materials such as Al, Ag, Au, Cu, Ta or Ti, or including other conductive bonding materials. The first sub-bonding layer 121 can be a composite layer. In the present embodiment, the first sub-bonding layer 121 is a Ti / Al / Ti composite layer, in which the Ti layer thickness ranges from 1nm to 50nm, preferably 15nm, and the Al layer thickness ranges from 100nm to 500nm, preferably 300nm, and the Ti / Al / Ti composite layer has relatively excellent electrical conductivity and can also provide better reflectivity to improve the luminous efficiency of the device. In addition, the Ti layer can be used as an etching barrier layer during the production process of the pixel array chip.

[0053] In some embodiments, the step of forming a first sub-bonding layer 121 on a side of the ohmic contact layer away from the P-type semiconductor layer 111 includes: depositing a Ti / Al / Ti (15 / 300 / 15 nm) composite layer on the surface of the ohmic contact layer by PVD as the first sub-bonding layer 121, wherein the thicknesses of the first Ti layer, the Al layer, and the second Ti layer in the Ti / Al / Ti composite layer are, for example, 15 nm, 300 nm, and 15 nm, respectively.

[0054] In step S105 , a second sub-bonding layer 122 is formed on a side of the first sub-bonding layer 121 away from the pixel function layer 110 , so as to obtain a composite bonding layer 120 including the first sub-bonding layer 121 and the second sub-bonding layer 122 . Figure 5 It is a cross-sectional schematic diagram of forming a second sub-bonding layer in an embodiment of a method for manufacturing a pixel array chip of the present application.

[0055] In some embodiments, the second sub-bonding layer 122 is at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0056] The second sub-bonding layer 122 may be a material layer of silicon, silicon nitride, silicon oxide or silicon oxynitride. Preferably, the second sub-bonding layer 122 is a SiO2 layer with a thickness of 30nm to 1000nm. Further, the second sub-bonding layer 122 is preferably a SiO2 layer with a thickness of 300nm.

[0057] In one example, step S105 includes: depositing a 2000 nm thick SiO2 layer on the side of the first sub-bonding layer 121 away from the pixel function layer 110 by a CVD process, and then thinning the SiO2 layer and performing chemical mechanical planarization to obtain a second sub-bonding layer 122 with a thickness of 300 nm and a flatness within 10 nm.

[0058] In step S106 , the composite bonding layer 120 is bonded to the first bonding layer 220 at room temperature, so that the driving substrate 200 is bonded to the epitaxial component 100 . Figure 6This is a cross-sectional schematic diagram of bonding the composite bonding layer to the first bonding layer at room temperature in one embodiment of the manufacturing method of the pixel array chip of the present application.

[0059] In this embodiment, after step S106 , step S107 is further included. In step S107 , the substrate 191 is peeled off and the buffer layer 192 is removed, so that the N-type semiconductor layer 113 is exposed from the second surface S2 of the pixel function layer 110 . Figure 7 This is a cross-sectional schematic diagram of peeling off the substrate and removing the buffer layer in one embodiment of the method for manufacturing the pixel array chip of the present application.

[0060] In some embodiments, the substrate 191 is peeled off or removed by laser peeling or grinding thinning followed by chemical etching.

[0061] In some embodiments, removing the buffer layer 192 includes: removing the epitaxial buffer layer 192 and the undoped layer (not shown) by an etching process, overetching to the N-type semiconductor layer 113, the overetching depth is 0.1um to 0.3um, preferably 0.2um, to ensure that the buffer layer 192 is completely overetched and does not consume a lot of the N-type semiconductor layer 113.

[0062] In step S108, the pixel function layer 110 is patterned to form a plurality of pixel function units PX arranged in an array on the pixel function layer 110, wherein the first sub-bonding layer 121 is electrically connected to the plurality of pixel function units PX, specifically, the first sub-bonding layer 121 is electrically connected to the P-type semiconductor layer 111 of the plurality of pixel function units PX. Figure 8 The present invention is a schematic cross-sectional view of patterning a pixel function layer in an embodiment of a method for manufacturing a pixel array chip of the present application to form a plurality of pixel function units arranged in an array on the pixel function layer. In some embodiments, the pixel array chip is a display chip, and the pixel function unit PX is a display pixel. For example, when the pixel array chip is a micro-light-emitting diode display chip, the pixel function unit PX is a micro-light-emitting diode unit. The pixel array chip includes an effective display area and a frame area located outside the effective display area. The pixel function units PX are arranged in the effective display area. A common electrode line may be provided in the frame area. The first sub-bonding layer 121 electrically connects the P-type semiconductor layer 111 of the plurality of pixel function units PX to the common electrode line.

[0063] In some embodiments, step S108 includes: defining the pixel area by yellow light and etching process, the etching depth is to completely etch the active layer 112 and over-etch 0.1um to 0.5um, preferably the over-etching depth is 0.2um. Over-etching the active layer 112 can completely define the pixel area and avoid crosstalk. In addition, the accuracy of 0.2um has moderate process requirements and is easier to achieve.

[0064] In some embodiments, the method for manufacturing a pixel array chip further includes steps S109 to S112.

[0065] In step S109 , the pixel function layer 110 is patterned to form a thinned area 113 a and a non-thinned area 113 b in the N-type semiconductor layer 113 of each pixel function unit PX. The thinned area 113 a is thinned from the second surface S2 to the first surface S1 relative to the non-thinned area 113 b. Fig. 9 A cross-sectional schematic diagram of forming a thinned region in an N-type semiconductor layer of each pixel functional unit in an embodiment of a method for manufacturing a pixel array chip of the present application.

[0066] In some embodiments, the thinned thickness of the thinned area 113a is 1 / 5 to 2 / 3 of the thickness of the non-thinned area 113b. The pixel function layer 110 may be patterned by photolithography and etching processes to form the thinned area 113a.

[0067] In step S110 , patterning is performed from the second surface S2 to form a plurality of via holes H1 penetrating from the second surface S2 to the plurality of cathode electrical connection portions 211 of the circuit layer 210 . Fig.10 It is a cross-sectional schematic diagram of forming a plurality of via holes in one embodiment of a method for manufacturing a pixel array chip of the present application.

[0068] In step S111 , a passivation layer 140 is formed on the sidewall of the via hole H1 . Fig.11 It is a cross-sectional schematic diagram of forming a passivation layer in an embodiment of a method for manufacturing a pixel array chip of the present application.

[0069] The passivation layer 140 includes at least one of TaN (tantalum nitride), SiO (silicon oxide), SiN (silicon nitride), Si (silicon), SINO (silicon oxynitride), AlO (aluminum oxide), AlN (aluminum nitride) or AlNO (aluminum oxynitride). Preferably, the passivation layer 140 is a TaN material layer with a thickness ranging from 1 nm to 500 nm, preferably 15 nm in this embodiment.

[0070] In one example, step S111 includes: depositing a TaN insulating layer on the side wall of the via H1 by an atomic layer deposition (ALD) process, a yellow light, and an etching process. By forming a passivation layer 140, it is possible to avoid short circuiting between the P-type semiconductor layer 111 and the N-type semiconductor layer 113, thereby preventing failure of the pixel functional unit PX.

[0071] In step S112 , a plurality of cathode electrodes 130 are formed to electrically connect the N-type semiconductor layers 113 of the plurality of pixel function units PX to the plurality of cathode electrical connection portions 211 via the plurality of via holes H1 , and each cathode electrode 130 covers the thinned area 113 a of the corresponding pixel function unit PX. Fig.12This is a cross-sectional schematic diagram of forming a plurality of cathode electrodes in an embodiment of a method for manufacturing a pixel array chip of the present application.

[0072] The cathode electrode 130 includes at least one of W (tungsten), Al (aluminum), Ag (silver), Au (gold), Cu (copper), Ta (tantalum) or Ti (titanium), preferably W (tungsten) metal. In some embodiments, the thickness of the cathode electrode 130 above the second surface S2 is 0.3um to 3um. For example, the thickness of the cathode electrode 130 above the second surface S2 is 0.6um.

[0073] In some embodiments, a patterned tungsten layer is filled in the via hole H1 as the cathode electrode 130 by CVD process, yellow light and etching process.

[0074] In some embodiments, the cathode electrode 130 further extends onto a portion of the non-thinned area 113 b of the adjacent pixel functional unit PX, and the passivation layer 140 is further located between the cathode electrode 130 and the non-thinned area 113 b of the adjacent pixel functional unit PX.

[0075] In the above embodiment, the N-type semiconductor layer 113 of each pixel functional unit PX includes a thinning area 113a, and the thinning area 113a is formed by thinning the N-type semiconductor layer 113, so that the cathode electrode 130 material with better conductivity can be formed on the surface of the thinning area 113a, which is convenient for improving the conductivity of the electrical connection between the cathode electrode 130 and the N-type semiconductor layer 113. In some embodiments, when the pixel array chip is a micro-light emitting diode display chip, the pixel functional unit PX is a micro-light emitting diode unit, and the thinning area 113a is formed by thinning the N-type semiconductor layer 113, which is convenient for improving the light emission uniformity of the micro-light emitting diode display chip.

[0076] In some embodiments, the method for manufacturing a pixel array chip further includes step S113.

[0077] In step S113 , an encapsulation layer 160 is formed on the side where the second surface S2 of the pixel function layer 110 is located. Fig.13 The encapsulation layer 160 is a cross-sectional schematic diagram of an embodiment of a method for manufacturing a pixel array chip of the present application. The encapsulation layer 160 is, for example, a cover plate, and the encapsulation layer 160 is attached to the second surface S2 of the pixel function layer 110 by means of an adhesive 170 . The encapsulation layer 160 and the adhesive 170 cover a plurality of cathode electrodes 130 .

[0078] Fig.14Schematic diagram of a top view of an embodiment of the pixel array chip of the present application. In some embodiments, each pixel functional unit PX is a polygonal structure, and the periphery of each pixel functional unit PX has a non-functional area L1. In some embodiments, the step S110 of patterning the second surface S2 to form a plurality of via holes H1 extending from the second surface S2 to the plurality of cathode electrical connection portions 211 of the circuit layer 210 includes: patterning the second surface S2 to form via holes H1 extending from the second surface S2 to the cathode electrical connection portion 211 of the circuit layer 210 at the corner positions of each pixel functional unit PX and the non-functional area L1. Fig.14 In this embodiment, the pixel functional unit PX has a rectangular structure, each cathode electrode 130 is located at a corner of the corresponding pixel functional unit PX, and extends to the non-functional area L1 and a portion of the non-thinned area 113b of the adjacent pixel functional unit PX.

[0079] Fig.15 This is a top view of an alternative embodiment of the pixel array chip of the present application. In the alternative embodiment, the pixel function unit PX is a hexagonal structure, and each cathode electrode 130 is located at a corner of the corresponding pixel function unit PX and extends to the non-functional area L1 and a portion of the non-thinned area 113b of the adjacent pixel function unit PX.

[0080] In the above embodiment, each cathode electrode 130 is located at the corner of the corresponding pixel functional unit PX, and the cathode electrode 130 extends to the non-functional area L1, that is, the cathode electrode 130 extends to the pixel spacing area, thereby reducing the coverage and shielding area of ​​the cathode electrode 130 on each pixel functional unit PX, reducing the shielding of light by the cathode electrode 130, and improving the utilization efficiency of the functional area of ​​the pixel functional unit PX.

[0081] In some embodiments, when the pixel array chip is a micro-LED display chip, the pixel function unit PX is a micro-LED unit. Since each cathode electrode 130 is located at a corner of the corresponding pixel function unit PX and the cathode electrode 130 extends to the non-functional area L1, the coverage area of ​​the cathode electrode 130 on the pixel light-emitting area can be reduced, which is convenient for improving the light-emitting brightness of the pixel.

[0082] In some other embodiments, the cathode electrode 130 is not limited to being located at the corner of the corresponding pixel functional unit PX. For example, the cathode electrode 130 is shaped to surround the corresponding pixel functional unit PX, thereby improving the utilization rate of the functional area.

[0083] According to the manufacturing method of the pixel array chip of the embodiment of the present application, the step of forming a first bonding layer 220 on the surface of the circuit layer 210 of the driving substrate 200, the step of forming a first sub-bonding layer 121 on the side of the first surface S1 of the pixel function layer 110 of the epitaxial component 100, and the step of forming a second sub-bonding layer 122 on the side of the first sub-bonding layer 121 away from the pixel function layer 110. Therefore, a composite bonding layer 120 including a first sub-bonding layer 121 and a second sub-bonding layer 122 is formed on the side of the first surface S1 of the pixel function layer 110 of the epitaxial component 100. Afterwards, the composite bonding layer 120 is bonded to the first bonding layer 220 at room temperature, so that the driving substrate 200 is bonded to the epitaxial component 100. Since the bonding process is carried out at room temperature, the influence of the temperature rise and temperature drop process on the stress fluctuation of the epitaxial component 100 is avoided, thereby reducing the damage to the performance of the epitaxial component 100 during the bonding process, that is, reducing the influence of the bonding process on the performance of the pixel array chip. According to the manufacturing method of the pixel array chip of the embodiment of the present application, the first sub-bonding layer 121 is a conductive layer and is electrically connected to the multiple pixel functional units PX, so that the first sub-bonding layer 121 with stronger conductivity can compensate for the conductive performance disadvantage of the semiconductor layer of the multiple pixel functional units PX, thereby providing a more stable electrical connection signal for the multiple pixel functional units PX.

[0084] The present application also provides a pixel array chip. Fig.13 The pixel array chip includes a driving substrate 200 and an epitaxial component 100. The driving substrate 200 includes a circuit layer 210 and a first bonding layer 220 located on one side of the circuit layer 210. The epitaxial component 100 includes a pixel function layer 110, a composite bonding layer 120 located on the side where the first surface S1 of the pixel function layer 110 is located, and a plurality of cathode electrodes 130 located on the second surface S2 of the pixel function layer 110, and the second surface S2 is opposite to the first surface S1. The composite bonding layer 120 is bonded to the first bonding layer 220 at room temperature.

[0085] The pixel function layer 110 includes a plurality of pixel function units PX arranged in an array. Each pixel function unit PX includes a P-type semiconductor layer 111, an active layer 112, and an N-type semiconductor layer 113 stacked in sequence, and the first sub-bonding layer 121 is electrically connected to the P-type semiconductor layer 111 of the plurality of pixel function units PX. Each cathode electrode 130 is electrically connected to the N-type semiconductor layer 113 corresponding to a pixel function unit PX on the second surface S2, and the cathode electrode 130 is electrically connected to the circuit layer 210 through the pixel function layer 110, the composite bonding layer 120, and the first bonding layer 220.

[0086] According to the pixel array chip of the embodiment of the present application, the driving substrate 200 includes a circuit layer 210 and a first bonding layer 220 located on one side of the circuit layer 210, and the epitaxial component 100 includes a pixel function layer 110 and a composite bonding layer 120 located on the side where the first surface S1 of the pixel function layer 110 is located. The composite bonding layer 120 is bonded to the first bonding layer 220 at room temperature, thereby realizing the bonding connection between the driving substrate 200 and the epitaxial component 100. Since the bonding process is carried out at room temperature, the influence of the temperature rise and temperature drop process on the stress fluctuation of the epitaxial component 100 is avoided, thereby reducing the damage to the performance of the epitaxial component 100 by the bonding process, that is, reducing the influence of the bonding process on the performance of the pixel array chip. Each cathode electrode 130 is electrically connected to the N-type semiconductor layer 113 corresponding to a pixel functional unit PX on the second surface S2, and the cathode electrode 130 is electrically connected to the circuit layer 210 through the pixel functional layer 110, the composite bonding layer 120 and the first bonding layer 220, thereby realizing electrical connection between the electrode on the side away from the driving substrate 200 in each pixel functional unit PX and the driving substrate 200. The above structure does not require an additional electrical connection structure to be arranged on the side where the second surface S2 of the pixel functional layer 110 is located, thereby simplifying the chip structure of the pixel array chip and avoiding shielding of the pixel functional unit PX by the additional electrical connection structure.

[0087] In this embodiment, the composite bonding layer 120 includes a first sub-bonding layer 121 located on the side of the first surface S1 of the pixel function layer 110 and a second sub-bonding layer 122 located on the side of the first sub-bonding layer 121 away from the pixel function layer 110. The first sub-bonding layer 121 is a conductive layer and is electrically connected to a plurality of pixel function units PX.

[0088] According to the pixel array chip of the embodiment of the present application, the first sub-bonding layer 121 is a conductive layer and is electrically connected to multiple pixel functional units PX, so that the first sub-bonding layer 121 with stronger conductivity can compensate for the conductive performance disadvantage of the semiconductor layer of the multiple pixel functional units PX, thereby providing a more stable electrical connection signal for the multiple pixel functional units PX.

[0089] In some embodiments, the pixel array chip is a micro light emitting diode display chip, and the pixel function unit PX is a micro light emitting diode unit.

[0090] In some embodiments, the pixel array chip is an image acquisition chip, and the pixel function unit PX is an electro-optical conversion unit.

[0091] Hereinafter, an embodiment of the pixel array chip will be described mainly by taking the pixel array chip as a Micro-LED display chip as an example.

[0092] The first bonding layer 220 may be made of a metal material or a non-metal material, such as Cu, Al, Au, Ag, Ta or Ti, or PI, PDMS, silicon, silicon nitride, silicon oxide or silicon oxynitride, etc. Preferably, the first bonding layer 220 is silicon, silicon oxide, silicon nitride or the like.

[0093] In some embodiments, the first bonding layer 220 is at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0094] In this embodiment, the first bonding layer 220 is preferably a SiO2 layer with a thickness of 30 nm to 1000 nm. Further, the first bonding layer 220 is preferably a SiO2 layer with a thickness of 500 nm.

[0095] The first sub-bonding layer 121 is a conductive layer, for example, including metal conductive materials such as Al, Ag, Au, Cu, Ta or Ti, or including other conductive bonding materials. The first sub-bonding layer 121 can be a composite layer. In the present embodiment, the first sub-bonding layer 121 is a Ti / Al / Ti composite layer or a Ti / Al / Ti / TiN composite layer, in which the Ti layer thickness ranges from 1nm to 50nm, preferably 15nm, the Al layer thickness ranges from 100nm to 500nm, preferably 300nm, and the TiN layer thickness ranges from 1nm to 5nm. The Ti / Al / Ti composite layer or the Ti / Al / Ti / TiN composite layer has relatively excellent electrical conductivity and can also provide better reflectivity to improve the luminous efficiency of the device. In addition, the Ti layer can be used as an etching barrier layer during the production process of the pixel array chip.

[0096] In some embodiments, the second sub-bonding layer 122 is at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0097] The second sub-bonding layer 122 may be a material layer of silicon, silicon nitride, silicon oxide or silicon oxynitride. Preferably, the second sub-bonding layer 122 is a SiO2 layer with a thickness of 30nm to 1000nm. Further, the second sub-bonding layer 122 is preferably a SiO2 layer with a thickness of 300nm.

[0098] In some embodiments, each pixel functional unit PX includes a P-type semiconductor layer 111, an active layer 112, and an N-type semiconductor layer 113 stacked in sequence, and the first sub-bonding layer 121 is electrically connected to the P-type semiconductor layer 111 of multiple pixel functional units PX to also serve as an anode electrode. In this embodiment, the active layer 112 is a multiple quantum well (MQW) layer.

[0099] In the above embodiment, the first sub-bonding layer 121 is electrically connected to the P-type semiconductor layer 111 of the multiple pixel functional units PX to serve as an anode electrode, so that the first sub-bonding layer 121 with stronger conductivity can compensate for the conductive performance disadvantage of the P-type semiconductor layer 111, and realize the interconnection of the P-type semiconductor layer 111 of the multiple pixel functional units PX, thereby providing a more stable anode signal for the multiple pixel functional units PX.

[0100] In some embodiments, the pixel array chip further includes an ohmic contact layer, and the ohmic contact layer is located between the P-type semiconductor layer 111 and the first sub-bonding layer 121 .

[0101] The ohmic contact layer is formed of a material that forms a good ohmic contact with the P-type semiconductor layer 111, preferably Ni or indium tin oxide (ITO), etc. In this embodiment, the ohmic contact layer is preferably ITO with a thickness of 10nm to 200nm, and further, the ohmic contact layer is preferably ITO with a thickness of 50nm.

[0102] In some embodiments, the circuit layer 210 includes a plurality of cathode electrical connection portions 211 corresponding to the plurality of cathode electrodes 130, and the pixel array chip includes a plurality of via holes H1 and a passivation layer 140. Each via hole H1 penetrates from the second surface S2 to the corresponding cathode electrical connection portion 211, and the cathode electrode 130 is at least partially located in the corresponding via hole H1. The passivation layer 140 is at least located between the cathode electrode 130 and the side wall of the via hole H1.

[0103] The passivation layer 140 includes at least one of TaN (tantalum nitride), SiO (silicon oxide), SiN (silicon nitride), Si (silicon), SINO (silicon oxynitride), AlO (aluminum oxide), AlN (aluminum nitride) or AlNO (aluminum oxynitride). Preferably, the passivation layer 140 is a TaN material layer with a thickness ranging from 1 nm to 500 nm, preferably 15 nm in this embodiment.

[0104] The cathode electrode 130 includes at least one of W (tungsten), Al (aluminum), Ag (silver), Au (gold), Cu (copper), Ta (tantalum) or Ti (titanium), preferably W (tungsten) metal. In some embodiments, the thickness of the cathode electrode 130 above the second surface S2 is 0.3um to 3um. For example, the thickness of the cathode electrode 130 above the second surface S2 is 0.6um.

[0105] In some embodiments, the N-type semiconductor layer 113 of each pixel functional unit PX includes a thinning area 113a and a non-thinning area 113b, and the thinning area 113a is thinned from the second surface S2 to the first surface S1 relative to the non-thinning area 113b. Each cathode electrode 130 covers the thinning area 113a of the corresponding pixel functional unit PX and extends to part of the non-thinning area 113b of the adjacent pixel functional unit PX. The passivation layer 140 is also located between the cathode electrode 130 and the non-thinning area 113b of the adjacent pixel functional unit PX.

[0106] In some embodiments, the thinned thickness of the thinned area 113a is 1 / 5 to 2 / 3 of the thickness of the non-thinned area 113b. The pixel function layer 110 may be patterned by photolithography and etching processes to form the thinned area 113a.

[0107] In the above embodiment, the N-type semiconductor layer 113 of each pixel functional unit PX includes a thinning area 113a, and the thinning area 113a is formed by thinning the N-type semiconductor layer 113, so that the cathode electrode 130 material with better conductivity can be formed on the surface of the thinning area 113a, which is convenient for improving the conductivity of the electrical connection between the cathode electrode 130 and the N-type semiconductor layer 113. In some embodiments, when the pixel array chip is a micro-light emitting diode display chip, the pixel functional unit PX is a micro-light emitting diode unit, and the thinning area 113a is formed by thinning the N-type semiconductor layer 113, which is convenient for improving the light emission uniformity of the micro-light emitting diode display chip.

[0108] In some embodiments, the pixel array chip further includes an encapsulation layer 160 , which is, for example, a cover glass or a protective film, and is attached to the second surface S2 of the pixel function layer 110 via an adhesive 170 . The encapsulation layer 160 and the adhesive 170 cover the plurality of cathode electrodes 130 .

[0109] like Fig.14 or Fig.15 In some embodiments, each pixel function unit PX has a polygonal structure, and the periphery of each pixel function unit PX has a non-functional area L1. Each cathode electrode 130 is electrically connected to the corresponding pixel function unit PX at a corner position of the corresponding pixel function unit PX, and the cathode electrode 130 extends to the non-functional area L1.

[0110] In the above embodiment, each cathode electrode 130 is located at the corner of the corresponding pixel functional unit PX, and the cathode electrode 130 extends to the non-functional area L1, that is, the cathode electrode 130 extends to the pixel spacing area, thereby reducing the coverage and shielding area of ​​the cathode electrode 130 on each pixel functional unit PX, reducing the shielding of light by the cathode electrode 130, and improving the utilization efficiency of the functional area of ​​the pixel functional unit PX.

[0111] In some embodiments, when the pixel array chip is a micro-LED display chip, the pixel function unit PX is a micro-LED unit. Since each cathode electrode 130 is located at a corner of the corresponding pixel function unit PX and the cathode electrode 130 extends to the non-functional area L1, the coverage area of ​​the cathode electrode 130 on the pixel light-emitting area can be reduced, which is convenient for improving the light-emitting brightness of the pixel.

[0112] The above description is only a preferred embodiment of the present application, and does not limit the patent scope of the present application. All equivalent structural changes made under the concept of the present application using the contents of the present application specification and drawings, or directly / indirectly used in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A pixel array chip, characterized in that: include: A driving substrate, comprising a circuit layer and a first bonding layer located on a surface of one side of the circuit layer; An epitaxial component includes a pixel function layer, a composite bonding layer located on the side where the first surface of the pixel function layer is located, and a plurality of cathode electrodes located on the second surface of the pixel function layer, wherein the second surface is opposite to the first surface, the composite bonding layer is bonded to the first bonding layer at room temperature, the pixel function layer includes a plurality of pixel function units arranged in an array, each of the pixel function units includes a P-type semiconductor layer, an active layer, and an N-type semiconductor layer stacked in sequence, each of the cathode electrodes is electrically connected to the N-type semiconductor layer corresponding to a pixel function unit on the second surface, and the cathode electrode is electrically connected to the circuit layer through the pixel function layer, the composite bonding layer, and the first bonding layer.

2. The pixel array chip according to claim 1, characterized in that: Each of the pixel functional units has a polygonal structure, and each of the pixel functional units has a non-functional area on its periphery. Each of the cathode electrodes is electrically connected to the corresponding pixel functional unit at a corner position of the corresponding pixel functional unit, and the cathode electrode extends to the non-functional area.

3. The pixel array chip according to claim 1, characterized in that: The circuit layer includes a plurality of cathode electrical connection parts corresponding to the plurality of cathode electrodes, and the pixel array chip includes: a plurality of via holes, each of the via holes extending from the second surface to the corresponding cathode electrical connection portion, and the cathode electrode is at least partially located in the corresponding via hole; The passivation layer is at least located between the cathode electrode and the side wall of the via hole.

4. The pixel array chip according to claim 3, characterized in that: The N-type semiconductor layer of each of the pixel functional units includes a thinning area and a non-thinning area, and the thinning area is thinned from the second surface to the first surface relative to the non-thinning area. Each of the cathode electrodes covers the thinning area corresponding to the pixel functional unit and extends to part of the non-thinning area of ​​the adjacent pixel functional unit. The passivation layer is also located between the cathode electrode and the non-thinning area of ​​the adjacent pixel functional unit.

5. The pixel array chip according to claim 4, characterized in that: The thinning thickness of the thinning area is 1 / 5 to 2 / 3 of the thickness of the non-thinning area.

6. The pixel array chip according to claim 4, characterized in that: The thickness of the cathode electrode above the second surface is 0.3 um to 3 um.

7. The pixel array chip according to claim 3, characterized in that: The passivation layer comprises one of TaN, SiO, SiN, Si, SINO, AlO, AlN or AlNO; The cathode electrode includes one of W, Al, Ag, Au, Cu, Ta or Ti.

8. The pixel array chip according to claim 1, characterized in that: Also includes: An encapsulation layer is adhered to the second surface of the pixel function layer by means of an adhesive, and the encapsulation layer and the adhesive cover the plurality of cathode electrodes.

9. The pixel array chip according to claim 1, characterized in that: The pixel array chip is a micro light emitting diode display chip, and the pixel function unit is a micro light emitting diode unit.

10. The pixel array chip according to claim 1, characterized in that: The pixel array chip is an image acquisition chip, and the pixel function unit is an electro-optical conversion unit.

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