Substrate
By designing a substrate including a conductive substrate, an insulating layer, a metal conductive layer and a solder resist layer, the testing and packaging requirements of high-power chips in different structures are solved, and diversified development evaluation and performance evaluation are achieved, saving costs.
Patent Information
- Application Number
- CN202421194432.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-29
- Publication Date
- 2025-03-18
- Estimated Expiration
- 2034-05-29
AI Technical Summary
The existing technology is difficult to meet the testing and packaging requirements of high-power chips in different structures, resulting in the need to change the copper substrate design every time, which is unable to meet the diverse development evaluation and performance evaluation requirements.
A substrate including a conductive substrate, an insulating layer, a metal conductive layer and a solder resist layer is designed. A platform, a first boss and a second boss are provided on the conductive substrate. The first boss communicates with the second boss for placing and testing chips of different structures.
Through this substrate design, it can meet the test performance evaluation needs of chips with different structural structures, save costs, and conduct a variety of performance tests through the connected second boss, including temperature detection, to meet the aging needs of multiple chips.
Smart Images
Figure CN222637291U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductor manufacturing, in particular to a substrate for testing and packaging high-power chips with various structures. Background Art
[0002] With the advent of the era of big data, intelligence, mobile Internet and cloud computing, higher requirements are placed on the transmission of communication networks, high-performance computers and high-end servers. High-power chips, with their advantages of good directionality, high brightness and long life, have quickly occupied an important position in special lighting.
[0003] As the power of chips increases, higher requirements are placed on the chip packaging optics, thermals and structure. For high-power chips under high current, effective heat dissipation must be used to solve the light decay problem. Thanks to the significant advantages of copper substrates in heat dissipation, high-end lighting on the market currently mainly uses copper substrates to package high-power chips. However, due to the different structural designs for different needs and different chips, the copper substrate design needs to be changed every time in the subsequent product testing and performance evaluation stages, which cannot meet current needs. Therefore, how to design a substrate that can be used to test and package high-power chips of various structures to meet the development evaluation stage and performance evaluation of different structures (such as horizontal chips, vertical chips, etc.) has become one of the difficulties that technicians in this field need to solve.
[0004] It should be noted that the information disclosed in this background technology section is only intended to increase the understanding of the overall background of the utility model, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to a person skilled in the art. Utility Model Content
[0005] The utility model provides a substrate, which includes a conductive substrate, an insulating layer, a metal conductive layer and a solder resist layer. The insulating layer is arranged on the conductive substrate. The metal conductive layer is arranged on the insulating layer. The solder resist layer covers the metal conductive layer. The conductive substrate includes a platform, a first boss and a second boss. The insulating layer covers the platform. The first boss and the second boss are arranged on the platform, the first boss is connected to the second boss, and the area above the first boss is used to set a chip.
[0006] The utility model provides a substrate, which places chips of different structures in the first boss area by setting a connected first boss and a second boss, and performs various performance tests by using the connected second boss, thereby meeting the test performance evaluation requirements of different chip structures and saving costs.
[0007] Other features and beneficial effects of the utility model will be described in the subsequent description, and some of the technical features and beneficial effects can be obviously derived from the description, or can be understood by implementing the utility model. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, some of the drawings described below are some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0009] Figure 1 It is a schematic diagram of a top view of a substrate provided in one embodiment of the utility model;
[0010] Figure 2 is along Figure 1 A schematic diagram of a cross-sectional structure taken along the interception line AA;
[0011] Figure 3 is a schematic diagram of a top view of a substrate provided by another embodiment of the utility model;
[0012] Figures 4 to 7 It is a schematic diagram of a structure in which chips of different structures and numbers are arranged on a substrate.
[0013] Reference numerals:
[0014] 10 - conductive substrate; 100 - platform; 101 - first boss; 102 - second boss; 103 - third boss; 12 - insulating layer; 14 - metal conductive layer; 140 - control circuit; 16 - solder resist layer. DETAILED DESCRIPTION
[0015] In order to make the purpose, technical solutions and advantages of the embodiments of the utility model clearer, the technical solutions in the embodiments of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiments of the utility model. Obviously, the described embodiments are part of the embodiments of the utility model, rather than all of the embodiments; the technical features designed in different implementation modes of the utility model described below can be combined with each other as long as they do not conflict with each other; based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the utility model.
[0016] In the description of the present utility model, it should be understood that the terms "center", "lateral", "up", "down", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present utility model. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present utility model, unless otherwise specified, "multiple" means two or more. In addition, the term "including" and any variation thereof all mean "at least including".
[0017] One embodiment of the utility model provides a substrate, which includes a conductive substrate, an insulating layer, a metal conductive layer and a solder resist layer. The insulating layer is arranged on the conductive substrate. The metal conductive layer is arranged on the insulating layer. The solder resist layer covers the metal conductive layer. Among them, the conductive substrate includes a platform, a first boss and a second boss. The insulating layer covers the platform. The first boss and the second boss are arranged on the platform, the first boss is connected to the second boss, and the area above the first boss is used to set the chip. By setting the connected first boss and the second boss, chips of different structures are placed in the first boss area, and various performance tests are performed by means of the connected second boss, for example, temperature detection is achieved by means of the second boss, so that the board temperature can be adjusted to meet the aging requirements of various chips, and then the test performance evaluation requirements of different chip structures can be met, saving costs.
[0018] In some embodiments, when looking down from the top of the substrate toward the conductive substrate, the area of the first boss is greater than the area of the second boss. Optionally, the area of the first boss is at least twice the area of the second boss. Optionally, when looking down from the top of the substrate toward the conductive substrate, the area of the first boss accounts for 20% to 80% of the area of the conductive substrate; Optionally, when looking down from the top of the substrate toward the conductive substrate, the area of the second boss accounts for 10% to 40% of the area of the conductive substrate, so that the first boss can accommodate more types and more chips.
[0019] In some embodiments, an upper surface of the first boss is flush with an upper surface of the metal conductive layer.
[0020] In some embodiments, the conductive substrate is a copper substrate to enhance heat dissipation performance.
[0021] In some embodiments, the material of the metal conductive layer includes copper metal to enhance heat dissipation performance.
[0022] In some embodiments, the board also includes a third boss, and the opposite ends of the third boss are respectively connected to the first boss and the second boss. Looking down from the top of the substrate toward the conductive substrate, the first boss, the second boss and the third boss form an "I" shape, which is convenient for subsequent circuit control design and realizes temperature detection, so that the board temperature can be adjusted to meet the aging requirements of various chips.
[0023] In some embodiments, the metal conductive layer has multiple independent control circuits to meet the needs of high-power packaging testing, aging and product evaluation of chips of different sizes.
[0024] See also Figure 1 and Figure 2 , Figure 1 1 is a schematic diagram of a top view of a substrate provided in one embodiment of the utility model. Figure 2 is along Figure 1 Schematic diagram of the cross-sectional structure cut by the cutting line AA. In order to achieve at least one of the above advantages or other advantages, an embodiment of the utility model provides a substrate, which is mainly used for testing and packaging high-power chips of various structures. As shown in the figure, the substrate includes a conductive substrate 10, an insulating layer 12, a metal conductive layer 14 and a solder resist layer 16.
[0025] The conductive substrate 10 may be made of metal, such as copper, aluminum, gold, composite metal, etc. In some embodiments, the conductive substrate 10 may be a copper substrate, which has better heat dissipation performance.
[0026] The insulating layer 12 is disposed on the conductive substrate 10. The material of the insulating layer 12 includes a non-conductive material. The non-conductive material is preferably an inorganic material or a dielectric material. The inorganic material may include silica gel. The dielectric material includes an electrical insulating material such as aluminum oxide, silicon nitride, silicon oxide, titanium oxide, or magnesium fluoride. For example, the insulating layer 12 may be silicon dioxide, silicon nitride, titanium oxide, tantalum oxide, niobium oxide, barium titanate, or a combination thereof.
[0027] The metal conductive layer 14 is disposed on the insulating layer 12. The material of the metal conductive layer 14 includes metal materials, such as copper metal, aluminum metal, gold metal, composite metal, etc.
[0028] The solder resist layer 16 covers the metal conductive layer 14. The solder resist layer 16 mainly has the functions of anti-oxidation and insulation. The material of the solder resist layer 16 can be selected from at least one of the group consisting of epoxy resin and polymer. Figure 1 As shown in , the solder resist layer 16 has openings to facilitate the use of fixing and installing the substrate. In some embodiments, the openings on the solder resist layer 16 expose the first boss 101 to facilitate the chip placement; the openings on the solder resist layer 16 expose the second boss 102 to facilitate testing.
[0029] Further, the conductive substrate 10 includes a platform 100, a first boss 101 and a second boss 102. The insulating layer 12 covers the platform 100, but does not cover the upper surfaces of the first boss 101 and the second boss 102. The first boss 101 and the second boss 102 are both arranged on the platform 100, and the first boss 101 is connected to the second boss 102. The area corresponding to the upper portion of the first boss 101 is used to set the chip, and the area above the second boss 102 is not provided with a chip. In this way, by setting the connected first boss 101 and the second boss 102, chips of different structures are placed in the area of the first boss 101, and various performance tests are performed by means of the electrically connected second boss 102, thereby meeting the test performance evaluation requirements of different chip structures and saving costs. In addition, the electrically connected second boss 102 can also help to dissipate heat from the first boss 101.
[0030] In some embodiments, looking down from the top of the substrate toward the conductive substrate 10, the area of the first boss 101 is larger than the area of the second boss 102, so that the first boss 101 can accommodate more types and more chips. Optionally, the area of the first boss 101 is at least twice the area of the second boss 102. Optionally, looking down from the top of the substrate toward the conductive substrate 10, the area of the first boss 101 accounts for 20% to 80% of the area of the conductive substrate 10. Optionally, looking down from the top of the substrate toward the conductive substrate 10, the area of the second boss 102 accounts for 10% to 40% of the area of the conductive substrate 10, and so on. However, the present case is not limited to this. Considering that the second boss 102 can be used for welding thermocouple aging, it can be selected according to the application and appropriately adjust its own area ratio.
[0031] In some embodiments, the upper surface of the first boss 101 is flush with the upper surface of the metal conductive layer 14 .
[0032] In some embodiments, the conductive substrate 10 further includes a third boss 103, and the opposite ends of the third boss 103 are respectively connected to the first boss 101 and the second boss 102. As shown in the figure, the upper and lower ends of the third boss 103 are respectively connected to the second boss 102 and the first boss 101. Looking down from the top of the substrate toward the conductive substrate 10, the first boss 101, the second boss 102 and the third boss 103 form an "I" shape, which is convenient for subsequent circuit control design and temperature detection, so that the board temperature can be adjusted to meet the aging requirements of various chips. In some embodiments, the first boss 101, the second boss 102 and the third boss 103 can be integrally formed. The first boss 101, the second boss 102 and the third boss 103 can be prepared together in the same preparation process.
[0033] In some embodiments, the metal conductive layer 14 has multiple independent control circuits 140. Figure 3 As shown, the metal conductive layer 14 has 8 independent circuit controls, thereby meeting the requirements of high-power packaging testing, aging and product evaluation of chips of different sizes.
[0034] See also Figures 4 to 7 , Figures 4 to 7 It is a schematic diagram of a structure in which chips of different structures and numbers are arranged on a substrate, so that the same substrate can meet the test performance evaluation requirements of different chip structures. The control circuit 140 may be covered with a packaging layer to play a role of protection and isolation.
[0035] In summary, the utility model provides a substrate, which places chips of different structures in the area of the first boss 101 by setting a connected first boss 101 and a second boss 102, and performs various performance tests by using the connected second boss 102, thereby meeting the test performance evaluation requirements of different chip structures and saving costs.
[0036] In addition, those skilled in the art should understand that, although there are many problems in the prior art, each embodiment or technical solution of the utility model can be improved in only one or several aspects, without having to solve all the technical problems listed in the prior art or background technology at the same time. Those skilled in the art should understand that the content not mentioned in a claim should not be used as a limitation on the claim.
[0037] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the utility model.
Claims
1. A substrate, characterized in that: The substrate comprises: Conductive substrate; An insulating layer, disposed on the conductive substrate; A metal conductive layer, disposed on the insulating layer; A solder resist layer, covering the metal conductive layer; The conductive substrate includes a platform, a first boss and a second boss, the insulating layer covers the platform, the first boss and the second boss are arranged on the platform, the first boss is connected to the second boss, and the area above the first boss is used to set the chip.
2. The substrate according to claim 1, characterized in that: Looking down from above the substrate toward the conductive substrate, the area of the first boss is larger than the area of the second boss.
3. The substrate according to claim 2, characterized in that: The area of the first boss is at least twice the area of the second boss.
4. The substrate according to claim 1, characterized in that: The upper surface of the first boss is flush with the upper surface of the metal conductive layer.
5. The substrate according to claim 1, characterized in that: The conductive substrate is a copper substrate.
6. The substrate according to claim 1, characterized in that: The material of the metal conductive layer includes copper metal.
7. The substrate according to claim 1, characterized in that: The conductive substrate further includes a third boss, the opposite ends of which are respectively connected to the first boss and the second boss. When looking down at the conductive substrate from above the substrate, the first boss, the second boss and the third boss form an "I" shape.
8. The substrate according to claim 1, characterized in that: Looking down from the top of the substrate toward the conductive substrate, the area of the first boss accounts for 20% to 80% of the area of the conductive substrate.
9. The substrate according to claim 1, characterized in that: Looking down from the top of the substrate toward the conductive substrate, the area of the second boss accounts for 10% to 40% of the area of the conductive substrate.
10. The substrate according to claim 1, characterized in that: The metal conductive layer has multiple independent control circuits.