Package structure
By setting conductive bumps with height difference in the package structure and raising the second conductive bump with the second pad, the problem of conductive bumps not bonded by substrate warping is solved, the risk of solder ball bridging is reduced, and the bonding reliability of the package structure is improved.
Patent Information
- Application Number
- CN202421333242.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-12
- Publication Date
- 2025-04-18
- Estimated Expiration
- 2034-06-12
AI Technical Summary
In the existing packaging structure, warping of the substrate leads to the problem of unengagement of conductive bumps, increasing the risk of welding ball bridging.
By providing the upper surface of the second conductive bump in the package structure higher than the upper surface of the first conductive bump, the second conductive bump is raised by the second pad, thereby creating a height difference between the first conductive bump and the second conductive bump, reducing the risk of solder ball bridging.
It effectively reduces the risk of welding ball bridging, avoids the problem of unbonding caused by substrate warping, and improves the bonding reliability of the packaging structure.
Smart Images
Figure CN222775310U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and more specifically, to a packaging structure. Background Art
[0002] With the continuous development of the semiconductor industry, the packaging structure has become thinner and thinner, and the spacing between adjacent conductive bumps on the substrate in the packaging structure has become smaller and smaller, so there is a greater risk of bridging between the solder balls on adjacent conductive bumps. In addition, generally speaking, when electroplating is performed in openings of different sizes, the electroplating height will be different accordingly. Usually, when the opening size is larger, the metal layer after electroplating will be higher and thicker. Therefore, when the conductive bump is formed by electroplating, it will be difficult to join later due to the larger size of the conductive bump, thereby increasing the risk of solder ball bridging.
[0003] Furthermore, in response to the current Moore's Law, the line width and line spacing will reach the extreme. After the Intel Embedded Multi-die Interconnect Bridge (Intel EMIB) structure is mass-produced, the overall structure will be transformed from a plane to a three-dimensional (3D) stack, and the volume that can be used during stacking will be properly used. After the Intel EMIB structure is mass-produced, other manufacturers began to envision doing the same structural stacking in the packaging structure (such as the fan-out (FO) structure), and most of them will set a large lateral size and thin substrate including electronic components (such as a deep trench capacitor die (DTC die) including multi-die units) in the packaging structure, but due to the overall structural thickness requirements, the electronic components and the substrate need to be as thin and light as possible. However, when performing flip-chip bonding (FCB) on such a large lateral size and thin substrate, due to the warping of the substrate, especially the high warping at the corners of the substrate, it is easy to cause the problem of non-joint bumps.
[0004] To further explain the problem of bump not bonding, Figure 1A FIG. 1 is a schematic cross-sectional view of a package structure 10 including an electronic component 12 (eg, a deep trench capacitor die) in the prior art. Figure 1B Shows Figure 1A The enlarged schematic diagram of the middle area 16, Figure 2 Shows Figure 1A A schematic diagram of the position of the tube die 14 in the electronic component 12 including multiple tube die 14, and Figure 3 Shows Figure 1A The electron microscope image of the bump not bonding problem at area 16. Figures 1A to 3As shown, the electronic component 12 may include a plurality of tube cores 14 arranged in a 1×4 array as framed by a rectangle 18 (i.e., there are 4 tube cores 14 in a row), a plurality of tube cores 14 arranged in a 1×3 array as indicated by arrows 20 (i.e., there are 3 tube cores 14 in a row), a single tube core 14 (hereinafter referred to as a 1×1 array) as indicated by arrows 32, and a plurality of tube cores 14 arranged in a 4×4 array as indicated by arrows 34 (i.e., there are 16 tube cores 14 in four rows and four columns). When the electronic component 12 is joined, for example, by joining the solder ball 22, the conductive bump 36 on the solder ball, and the pad 38 under the conductive bump 36 to the conductive bump 26 on the redistribution layer 24 below, the distance between the conductive bump 26 and the tube core 14 changes due to the warping of the electronic component 12, and the thickness of the conductive bump 36 is the same as each other (and the thickness of the pad 38 below is the same as each other), so that the solder ball 22 may not be connected to the conductive bump 26, especially at the corner position (as indicated by the arrow 28) of the electronic component 12 and the corner position (as indicated by the arrow 30) of the 1×4 array, resulting in the following problems: Figure 3 The technical problem of non-bonding shown. In addition, the pad 38 under the conductive bump 36 can be considered as part of the redistribution layer. In the case where the electronic component 12 is a deep trench capacitor die including a plurality of dies 14, wherein the plurality of dies 14 are silicon dies, studies have shown that the probability of non-bonding problems occurring at the corners of the dies 14 arranged in a 1×1 array, a 1×3 array, a 1×4 array, and a 4×4 array is 29.03%, 88.1%, 100%, and 93.65%, respectively. It can be seen that the probability of non-bonding problems occurring at the dies 14 arranged in a 1×4 array is the highest. In addition, the package structure 10 may also include a double data rate memory (DDR) 40, a system-on-chip 42, and a graphics processor 44 (GPU). It is not difficult to understand that the existing package structure not only has the risk of solder ball bridging on adjacent conductive bumps, but also has the technical problem of non-bonding. Utility Model Content
[0005] In view of the above problems existing in the prior art, an embodiment of the present application proposes a packaging structure, and the bonding structure can at least reduce the risk of solder ball bridging.
[0006] According to one aspect of the present application, a packaging structure is provided, which includes: a first substrate; a first solder pad, arranged on the first substrate, the first solder pad having a first upper surface and a first bottom surface opposite to the first upper surface; a first conductive bump, arranged on the first upper surface; a second solder pad, arranged on the first substrate, the second solder pad having a second upper surface and a second bottom surface opposite to the second upper surface, the second upper surface is higher than the first upper surface, and the second bottom surface is aligned with the first bottom surface; a second conductive bump, arranged on the second upper surface, wherein the upper surface of the second conductive bump is higher than the upper surface of the first conductive bump; a first solder ball, located on the first conductive bump; and a second solder ball, located on the second conductive bump.
[0007] In one or more embodiments, the packaging structure also includes a dielectric layer that encapsulates the first pad and the second pad, the dielectric layer exposing the upper surface of the first conductive bump and the upper surface of the second conductive bump, wherein the upper surface of the dielectric layer includes a first region located above the first pad and a second region located above the second pad, and the height of the first region is lower than the height of the second region.
[0008] In one or more embodiments, the upper surface of the dielectric layer further includes a connection surface connecting the first region and the second region, and the first region, the connection surface, and the second region are connected together to form a step shape.
[0009] In one or more embodiments, the first conductive bump and the second conductive bump are arranged side by side along a first direction, and in the first direction, a width of the first conductive bump is equal to a width of the second conductive bump.
[0010] In one or more embodiments, in a second direction perpendicular to the first direction, a length of the first conductive bump is equal to a length of the second conductive bump.
[0011] In one or more embodiments, the first conductive bump and the second conductive bump are arranged side by side along a first direction, and in the first direction, a width of the first pad is smaller than a width of the second pad.
[0012] In one or more embodiments, a thickness of the first pad is smaller than a thickness of the second pad.
[0013] In one or more embodiments, the packaging structure also includes a second substrate disposed above the first substrate, the second substrate being electrically connected to the first substrate through the first solder ball and the second solder ball, and the distance between the lower surface of the second substrate and the first bottom surface of the first solder pad is smaller than the distance between the lower surface of the second substrate and the second bottom surface of the second solder pad.
[0014] In one or more embodiments, a third region of the lower surface of the second substrate is located above the first conductive bump, and a fourth region of the lower surface of the second substrate is located above the second conductive bump, and the third region is closer to the upper surface of the first substrate than the fourth region.
[0015] In one or more embodiments, a lower surface of the second substrate protrudes toward the first substrate.
[0016] In one or more embodiments, the package structure further includes a third pad and a fourth pad located on the lower surface of the second substrate, the third pad and the fourth pad electrically connecting the second substrate to the first solder ball and the second solder ball, respectively.
[0017] In one or more embodiments, the package structure further includes a first solder ball and a second solder ball respectively located on the first conductive bump and the second conductive bump, the first solder ball electrically connecting the first conductive bump to the third pad, and the second solder ball electrically connecting the second conductive bump to the fourth pad.
[0018] In one or more embodiments, the package structure further includes a filling layer located between the second substrate and the first substrate, and the filling layer at least surrounds the first solder ball, the second solder ball, the third solder pad, and the fourth solder pad.
[0019] In one or more embodiments, the first pad and the second pad are both single-layer metal layers.
[0020] In one or more embodiments, the first pad is a single metal layer, and the second pad includes two metal layers stacked one above the other.
[0021] In one or more embodiments, the thickness of the first pad is in the range of 0.5 um to 8 um, and the thickness of the second pad is 1.1 times the thickness of the first pad.
[0022] According to another aspect of the present application, a packaging structure is provided, which includes: a first substrate; a first solder pad and a second solder pad, which are arranged on the first substrate; a first conductive bump and a second conductive bump, which are respectively located on the first solder pad and the second solder pad, wherein the thickness of the first solder pad is less than the thickness of the second solder pad so that the upper surface of the first conductive bump is lower than the upper surface of the second conductive bump.
[0023] In one or more embodiments, the packaging structure also includes a second substrate located above the first substrate, and the second substrate is electrically connected to the first substrate through the first conductive bump and the second conductive bump, wherein the distance between the lower surface of the second substrate and the first bottom surface of the first pad is less than the distance between the lower surface of the second substrate and the second bottom surface of the second pad.
[0024] In one or more embodiments, the packaging structure also includes a fifth solder pad located on the first substrate and a third conductive bump located on the fifth solder pad, the first solder pad is located between the second solder pad and the fifth solder pad, and the thickness of the first solder pad is less than the thickness of the fifth solder pad so that the upper surface of the first conductive bump is lower than the upper surface of the third conductive bump.
[0025] In one or more embodiments, the package structure further includes a plurality of solder balls located on the upper surface of the second substrate.
[0026] The beneficial technical effects of the utility model are:
[0027] Since the upper surface of the second conductive bump is higher than the upper surface of the first conductive bump in the packaging structure of the embodiment of the present application, the risk of bridging the first solder ball and the second solder ball respectively located on the first conductive bump and the second conductive bump can at least be reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings without creative work. It is worth noting that according to the standard practice of the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, for the clarity of discussion, the size of each component can be arbitrarily increased or reduced.
[0029] Figure 1A A cross-sectional schematic diagram of a packaging structure in the prior art is shown.
[0030] Figure 1B Shows Figure 1A A magnified schematic diagram of the middle area.
[0031] Figure 2 Shows Figure 1A A schematic diagram of die positions in an electronic component including multiple dies.
[0032] Figure 3 Shows Figure 1A SEM image of the area where the bump non-bonding problem occurs.
[0033] Figure 4A A schematic cross-sectional view of a packaging structure according to an embodiment of the present application is shown.
[0034] Figure 4B A schematic cross-sectional view of a first pad and a first conductive bump according to an embodiment of the present application is shown separately.
[0035] Figure 4C A cross-sectional schematic diagram of a second pad and a second conductive bump according to an embodiment of the present application is shown separately.
[0036] Figure 5 A schematic top view of a packaging structure according to an embodiment of the present application is shown.
[0037] Figure 6 A cross-sectional schematic diagram of a packaging structure according to another embodiment of the present application is shown.
[0038] Figure 7 A cross-sectional schematic diagram of a packaging structure according to another embodiment of the present application is shown.
[0039] Figure 8 A cross-sectional schematic diagram of a packaging structure according to another embodiment of the present application is shown.
[0040] Fig. 9 A cross-sectional schematic diagram of a second pad and a second conductive bump according to an embodiment of the present application is shown.
[0041] Fig.10 Shows Figure 4A A cross-sectional schematic diagram of a packaging structure without showing the first substrate.
[0042] Fig.11 A cross-sectional schematic diagram showing that the second pad according to an embodiment of the present application includes two metal layers.
[0043] Fig.12 A cross-sectional schematic diagram of a packaging structure without showing the first substrate according to another embodiment of the present application is shown.
[0044] FIG. 13A to FIG. 13E The formation of an embodiment according to the present application is shown Figure 8 Schematic cross-sectional views of the package structure at various stages shown.
[0045] FIG. 14A to FIG. 14E Schematic cross-sectional views of various stages of forming a package structure according to another embodiment of the present application are shown.
[0046] FIG. 15A to FIG. 15E Schematic cross-sectional views of various stages of forming a package structure according to another embodiment of the present application are shown. DETAILED DESCRIPTION
[0047] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.
[0048] The following disclosure provides many different embodiments or examples for realizing different features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component may not be in direct contact. Moreover, the present invention may repeatedly refer to numbers and / or letters in various examples. This repetition is only for simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.
[0049] In addition, the embodiments in the present application and the features in the embodiments may be combined with each other in the absence of conflicts. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments. It should be understood that the specific structures shown in the drawings are only for the sake of convenience of explanation and are not intended to limit the present application. When describing a specific figure, other structures not described in the drawings may be provided according to actual needs and are not intended to limit the present application.
[0050] Figure 4A FIG. 1 is a schematic cross-sectional view of a package structure 100 according to an embodiment of the present application. For the sake of clarity, Figure 4B The cross-sectional schematic diagram of the first pad 104 and the first conductive bump 106 according to the embodiment of the present application is shown separately. Figure 4C A cross-sectional schematic diagram of the second pad 108 and the second conductive bump 110 according to an embodiment of the present application is shown separately. FIG. 4A to FIG. 4CThe package structure 100 includes a first substrate 102, a first pad 104 and a second pad 108 disposed on the first substrate 102. The first pad 104 has a first upper surface 104t and a first bottom surface 104b opposite to the first upper surface 104t, and the second pad 108 has a second upper surface 108t and a second bottom surface 108b opposite to the second upper surface 108t. The package structure 100 also includes a first conductive bump 106 disposed on the first upper surface 104t, a second conductive bump 110 disposed on the second upper surface 108t, and a first solder ball 136 and a second solder ball 138 respectively located on the first conductive bump 106 and the second conductive bump 110, the first bottom surface 104b is aligned with the second bottom surface 108b, the second upper surface 108t is higher than the first upper surface 104t, and the upper surface 110t of the second conductive bump 110 is higher than the upper surface 106t of the first conductive bump 106. In the packaging structure 100 of the embodiment of the present application, since the first upper surface 104t of the first solder pad 104 is lower than the second upper surface 108t of the second solder pad 108, the upper surface 106t of the first conductive bump 106 is correspondingly lower than the upper surface 110t of the second conductive bump 110. That is, the second conductive bump 110 is raised by the second solder pad 108, so that a height difference is generated between the first conductive bump 106 and the second conductive bump 110. In this way, there is also a certain height difference between the first solder ball 136 and the second solder ball 138 located on the first conductive bump 106 and the second conductive bump 110 having a certain height difference, thereby at least reducing the risk of bridging the first solder ball 136 and the second solder ball 138.
[0051] although FIG. 4A to FIG. 4C Only one first conductive bump 106 and one second conductive bump 110 are shown in the figure. It is easy to understand that the package structure 100 may also have multiple similar first conductive bumps 106 and second conductive bumps 110. Similarly, there may also be multiple similar first solder balls 136 and second solder balls 138. Figure 4A 104b and the second bottom surface 108b of the first pad 104 and the second bottom surface 108b of the second pad 108 are both directly disposed on the upper surface of the first substrate 102. However, the present application is not limited thereto. The first bottom surface 104b and the second bottom surface 108b may be lower than the upper surface of the first substrate 102 (see Figure 8 ).
[0052] refer to Figure 4AIn some embodiments, in the following description, the direction in which the first conductive bump 106 and the second conductive bump 110 are arranged side by side is referred to as the first direction X, the direction perpendicular to the first direction X and in the same horizontal plane as the first direction X is referred to as the second direction Y, and the vertical direction perpendicular to the first direction X and the second direction Y is referred to as the third direction Z. In some embodiments, in the first direction X, the width (e.g., 35 μm) of the first conductive bump 106 is equal to the width of the second conductive bump 110. In a further embodiment, in the second direction Y, the length of the first conductive bump 106 is equal to the length of the second conductive bump 110. In a further embodiment, the thickness of the first conductive bump 106 is equal to the thickness of the second conductive bump 110. It is not difficult to understand that the thickness or height refers to the dimension in the third direction Z. In an embodiment in which the width, length, and thickness of the first conductive bump 106 are respectively equal to the width, length, and thickness of the second conductive bump 110, the dimensions (e.g., width, length, and thickness) of the first conductive bump 106 and the second conductive bump 110 are exactly the same.
[0053] In some embodiments, in the first direction X, the width of the first pad 104 (e.g., 60 μm) is less than the width of the second pad 108 (e.g., 90 μm). In a further embodiment, the thickness of the first pad 104 is less than the thickness of the second pad 108. In some embodiments, the thickness of the first pad 104 may be 1.6 μm less than the thickness of the second pad 108. In some embodiments, the thickness of the first pad 104 may be in the range of 0.5 μm to 8 μm, and the thickness of the second pad 108 is 1.1 times the thickness of the first pad 104. In an embodiment where the width, length, and thickness of the first conductive bump 106 are respectively equal to the width, length, and thickness of the second conductive bump 110, by making the thickness of the first pad 104 less than the thickness of the second pad 108, the height of the second conductive bump 110 can be raised to increase the spacing between the first conductive bump 106 and the second conductive bump 110, thereby reducing the risk of bridging between the first solder ball 136 and the second solder ball 138. In some embodiments, the first pad 104 and the second pad 108 are both single-layer metal layers. However, the present application is not limited thereto. In other embodiments, the first pad 104 is a single-layer metal layer, and the second pad 108 includes two metal layers stacked up and down (see Fig.12 ).
[0054] Next reference Figure 4AIn some embodiments, the package structure 100 may further include a dielectric layer 112 encapsulating the first pad 104 and the second pad 108, wherein the dielectric layer 112 exposes the upper surface 106t of the first conductive bump 106 and the upper surface 110t of the second conductive bump 110. In this embodiment, the upper surface 112t of the dielectric layer 112 includes a first region 112t1 located above the first pad 104 and a second region 112t2 located above the second pad 108, wherein the height of the first region 112t1 is lower than the height of the second region 112t2. Figure 4A In the illustrated embodiment, the upper surface 112t of the dielectric layer 112 further includes a connection surface 112t3 connecting the first region 112t1 and the second region 112t2. The first region 112t1, the connection surface 112t3 and the second region 112t2 are connected together to form a step shape.
[0055] In some embodiments, Figure 5 A schematic top view of a packaging structure 100 according to an embodiment of the present application is shown. Figure 4A and Figure 5 As shown, the package structure 100 may include a middle region 100A and a corner region (or edge region) 100B surrounding the middle region 100A, wherein the first pad 104 and the first conductive bump 106 may be located in the middle region 100A of the package structure 100, and the second pad 108 and the second conductive bump 110 may be located in the corner region 100B of the package structure 100. However, the present application is not limited thereto, and in other embodiments, the first pad 104 and the first conductive bump 106 may be located in the corner region 100B of the package structure 100, and the second pad 108 and the second conductive bump 110 may be located in the middle region 100A of the package structure 100.
[0056] Figure 6 shows a schematic cross-sectional view of a package structure 200 according to another embodiment of the present application, and Figure 7 FIG. 4 is a schematic cross-sectional view of a package structure 300 according to another embodiment of the present application. Figure 6 and Figure 7 The package structures 200 and 300 shown in FIG. Figure 4A and Figure 5 The package structure 100 shown is similar, wherein the same reference numerals represent the same components, and only the differences are described below. Figure 6In the illustrated embodiment, the first pad 104 and the first conductive bump 106 may be located in the middle region 100A of the package structure 200, while the second pad 108 and the second conductive bump 110 may be located in the corner region 100B of the package structure 200. In some embodiments, the package structure 200 may further include a fifth pad 142 located on the first substrate 102 and a third conductive bump 144 located on the fifth pad 142, and the first pad 104 is located between the second pad 108 and the fifth pad 142. The thickness of the first pad 104 is less than the thickness of the fifth pad 142 so that the upper surface of the first conductive bump 106 is lower than the upper surface of the third conductive bump 144. Figure 7 In the illustrated embodiment, the first pads 104 and the first conductive bumps 106 may be located in the corner region 100B of the package structure 300 , while the second pads 108 and the second conductive bumps 110 may be located in the middle region 100A of the package structure 300 .
[0057] Figure 8 4 is a schematic cross-sectional view of a package structure 400 according to another embodiment of the present application. In some embodiments, the package structure 400 may further include a second substrate 130 disposed above the first substrate 102, and the second substrate 130 is electrically connected to the first substrate 102 through a first solder ball 136 and a second solder ball 138. The distance between the lower surface 130b of the second substrate 130 and the first bottom surface 104b of the first pad 104 is less than the distance between the lower surface 130b of the second substrate 130 and the second bottom surface 108b of the second pad 108. Accordingly, the lower surface 130b of the second substrate 130 protrudes toward the first substrate 102. However, the present application is not limited thereto, and the lower surface 130b of the second substrate 130 protrudes away from the first substrate 102 (not shown). That is, the second substrate 130 is warped, and the lower surface 130b of the second substrate 130 is a curved surface. In some embodiments, the distance between the lower surface 130b of the second substrate 130 and the upper surface of the first conductive bump 106 is equal to the distance between the lower surface 130b of the second substrate 130 and the upper surface of the second conductive bump 110. In the package structure 400 of the embodiment of the present application, even when the second substrate 130 is warped, the first conductive bump 106 can be arranged at a position (e.g., a middle area) where the distance between the first bottom surface 104b and the lower surface 130b of the second substrate 130 is small, and the second conductive bump 110, which is raised by the second pad 108, can be arranged at a position (e.g., a corner area) where the distance between the second bottom surface 108b and the lower surface 130b of the second substrate 130 is large. In this way, the technical problem of non-bonding with the solder ball caused by the warping of the second substrate 130 can be avoided by the first conductive bump 106 and the second conductive bump 110 having different heights.
[0058] In a further embodiment, the lower surface 130b of the second substrate 130 includes a third region 130b3 and a fourth region 130b4, the third region 130b3 is located above the first conductive bump 106, and the fourth region 130b4 is located above the second conductive bump 110, and the third region 130b3 is closer to the upper surface of the first substrate 102 than the fourth region 130b4. Accordingly, the third region 130b3 is also closer to the first bottom surface 104b of the first pad 104 (or the second bottom surface 108b of the second pad 108) than the fourth region 130b4. Figure 8 In the illustrated embodiment, the fourth region 130b4 is closer to the edge of the second substrate 130 than the third region 130b3. In some embodiments, the package structure 400 may further include a third pad 132 and a fourth pad 134 located on the lower surface 130b of the second substrate 130, and the third pad 132 and the fourth pad 134 electrically connect the second substrate 130 to the first solder ball 136 and the second solder ball 138, respectively. It is not difficult to understand that the third pad 132 and the fourth pad 134 are located on the third region 130b3 and the fourth region 130b4, respectively. In some embodiments, the third pad 132 and the fourth pad 134 may be considered as pads of a redistribution layer. The first solder ball 136 electrically connects the first conductive bump 106 to the third pad 132, and the second solder ball 138 electrically connects the second conductive bump 110 to the fourth pad 134. In this embodiment, since the first solder ball 136 and the second solder ball 138 are electrically connected via the first conductive bump 106 and the second conductive bump 110 having a height difference, the risk of bridging of the first solder ball 136 and the second solder ball 138 can be further avoided.
[0059] See next Figure 8As shown, the package structure 400 may further include a filling layer 140 located between the second substrate 130 and the first substrate 102, and the filling layer 140 at least surrounds the first solder ball 136, the second solder ball 138, the third pad 132, and the fourth pad 134. The filling layer 140 is in direct contact with the dielectric layer 112 and in direct contact with the lower surface 130b of the second substrate 130. In some embodiments, the second substrate 130 may include a plurality of insulating layers 146 and conductive wires 148 located in the insulating layers 146, and the conductive wires 148 may be electrically connected to the third pad 132 and the fourth pad 134. In some embodiments, the package structure 400 may further include a plurality of solder balls 150 located on the upper surface of the second substrate 130, and the plurality of solder balls 150 may be electrically connected to the conductive wires 148. In some embodiments, the package structure 400 may further include a conductive column 152 located in the first substrate 102 and connected to the first bottom surface 104b of the first pad 104 and the second bottom surface 108b of the second pad 108. The package structure 400 may further include a conductive pillar 154 located on the lower surface of the first substrate 102. The conductive pillar 154 may be a copper pillar. In other embodiments, the first substrate 102 may further include a deep trench capacitor die ( Figure 8 (not shown), the deep trench capacitor die can be connected to the second substrate 130 through the first conductive bump 106 and the second conductive bump 110 with a height difference. The first conductive bump 106 and the second conductive bump 110 with a height difference are bonded to reduce the risk of non-bonding of the silicon die arranged in 1×1 array, 1×3 array, 1×4 array and 4×4 array in the prior art described above. In addition, compared with the prior art of arranging silicon die in a 2×2 array in the deep trench capacitor die, the present application does not limit the arrangement of the silicon die in the deep trench capacitor die, thereby increasing the layout flexibility.
[0060] Fig. 9 FIG. 1 is a cross-sectional view of a second pad 156 and a second conductive bump 158 according to an embodiment of the present application. Figure 4A and Fig. 9 For explanation. Fig. 9In the illustrated embodiment, the size of the second pad 156 is exactly the same as the size of the first pad 104 (e.g., width, length, and thickness). That is, the width, length, and thickness of the second pad 156 are respectively equal to the width, length, and thickness of the first pad 104. In addition, the thickness of the second conductive bump 158 is greater than the thickness of the first conductive bump 106. In addition, the width of the second conductive bump 158 (e.g., 50 μm) may be greater than the width of the first conductive bump 106 (e.g., 35 μm). In this embodiment, the thickness of the second conductive bump 158 may be increased so that the upper surface 158t of the second conductive bump 158 is higher than the upper surface 106t of the first conductive bump 106, thereby obtaining the first conductive bump 106 and the second conductive bump 158 of different heights. The second pad 156 and the second conductive bump 158 may be replaced as follows FIG. 4A to FIG. 8 The second pad 108 and the second conductive bump 110 are shown. It is easy to understand that the second conductive bump 110 can be heightened by increasing the thickness of the second pad 108 without changing the thickness of the second conductive bump 110, or by increasing the thickness of the second conductive bump 158 itself without changing the thickness of the second pad 156 to heighten the second conductive bump 158.
[0061] To detail the dimensions of the individual components, Fig.10 1 shows a cross-sectional schematic diagram of the package structure 200 without showing the first substrate 102. Fig.11 FIG. 1 shows a cross-sectional schematic diagram of the second pad 108 including two metal layers. Fig.12 FIG. 2 is a cross-sectional view showing that the second pad 156 and the second conductive bump 158 replace the second pad 108 and the second conductive bump 110 in the package structure 200 . Figures 10 to 12As shown, the width of the first pad 104 (or the second pad 156) can be in the range of 10 μm to 1000 microns, and the width of the second pad 108 can be 1.5 times the width of the first pad 104 (or the second pad 156). The thickness of the first pad 104 (or the second pad 156) can be in the range of 0.5 um to 8 um, and the thickness of the second pad 108 is 1.1 times the thickness of the first pad 104 (or the second pad 156). The spacing between the first upper surface 104t of the first pad 104 and the first region 112t1 of the dielectric layer 112 can be in the range of 1.3 um to 25 um, and the spacing between the second upper surface 108t of the second pad 108 (or the upper surface 156t of the second pad 156) and the second region 112t2 of the dielectric layer 112 can be 1.1 times the spacing between the first upper surface 104t and the first region 112t1. The distance between the first bottom surface 104b of the first pad 104 and the highest point of the upper surface of the first solder ball 136 may be 34.55um, and the distance between the second bottom surface 108b of the second pad 108 (or the bottom surface 156b of the second pad 156) and the highest point of the upper surface of the second solder ball 138 may be 36.3um. The first conductive bump 106 and the second conductive bump 110 (or the second conductive bump 158) each include a through hole portion located in the dielectric layer 112 and a line portion located on the upper surface of the dielectric layer 112. In the first direction X, the line portion of the first conductive bump 106 (or the second conductive bump 110) extends 7.5 um from the opposite side walls of the through-hole portion of the first conductive bump 106 (or the second conductive bump 110) to both sides, so that the width of the line portion of the first conductive bump 106 (or the second conductive bump 110) can be 15 um greater than the width of the through-hole portion of the first conductive bump 106 (or the second conductive bump 110). Correspondingly, in the first direction X, the line portion of the second conductive bump 158 extends 12.5 um from the opposite side walls of the through-hole portion of the second conductive bump 158 to both sides, so that the width of the line portion of the second conductive bump 158 can be 25 um greater than the width of the through-hole portion of the second conductive bump 158. When the thickness of the second pad 108 is 3.5 um greater than the thickness of the first pad 104 , the second pad 108 may be configured to include two metal layers, or the second pad 108 may be replaced with the second pad 156 .
[0062] FIG. 13A to FIG. 13E The formation of an embodiment according to the present application is shown Figure 8 Schematic cross-sectional views of the package structure 400 at various stages are shown.
[0063] See also Fig.13A, a semiconductor structure 202 is provided, the semiconductor structure 202 includes a carrier glass 204, a conductive column 154 located on the carrier glass 204, a conductive column 152 and an insulating layer 206 surrounding the conductive column 152, wherein the conductive column 154 is located below the insulating layer 206, and the conductive column 152 protrudes from the upper surface of the insulating layer 206.
[0064] See next Fig. 13B , a first solder pad 104 and a second solder pad 108 are formed on the conductive pillar 152 to obtain a semiconductor structure 208. In some embodiments, the first solder pad 104 and the second solder pad 108 can be formed by electroplating. As shown in the figure, the width of the first solder pad 104 is smaller than the width of the second solder pad 108, and the thickness of the first solder pad 104 is smaller than the thickness of the second solder pad 108. Experiments have found that when electroplating, the wider the pad, the greater the thickness of the resulting pad. Therefore, the present application can use the characteristics of the electroplating process itself to generate solder pads of different thicknesses to pad the conductive bumps (such as conductive bumps located in corner areas) that are easily affected by warping that are formed later. Thereby, it can be achieved despite Fig. 13B The first pad 104 is shown as being located in the middle region, and the second pad 108 is shown as being located in the edge region. However, in other embodiments, the first pad 104 may be located in the edge region, and the second pad 108 may be located in the middle region.
[0065] See next Fig. 13C , a dielectric layer 112 is formed on the first pad 104 and the second pad 108, and openings are formed in the dielectric layer 112 to expose the first pad 104 and the second pad 108, respectively, to obtain a semiconductor structure 210. The dielectric layer 112 may be a polyimide (PI) layer. Since the width of the first pad 104 is smaller than the width of the second pad 108, the height of the first region 112t1 of the dielectric layer 112 is lower than the height of the second region 112t2 of the dielectric layer 112.
[0066] See next Fig.13D , forming the first conductive bump 106 and the second conductive bump 110 in the openings of the dielectric layer 112 exposing the first pad 104 and the second pad 108, respectively, to obtain the semiconductor structure 212. Forming the semiconductor structure 212 may also include forming the first solder ball 136 and the second solder ball 138 on the first conductive bump 106 and the second conductive bump 110, respectively, and the alloy layer 214 located between the first conductive bump 106 and the first solder ball 136, and between the second conductive bump 110 and the second solder ball 138, respectively.
[0067] See next Fig.13E ,Will Fig.13DThe semiconductor structure 212 is turned upside down, and the semiconductor structure 212 is bonded to the second substrate 130, and a filling layer 140 is formed to obtain a package structure 400. The carrier glass 204 (see Fig.13D ) may occur before or after the semiconductor structure 212 is bonded to the second substrate 130 .
[0068] FIG. 14A to FIG. 14E Schematic cross-sectional views at various stages of forming a package structure 500 according to another embodiment of the present application are shown. The package structure 500 is similar to the package structure 400, except that the second pad 108 may include two metal layers.
[0069] See also Fig.14A , a semiconductor structure 302 is provided, the semiconductor structure 302 and the Fig.13E The semiconductor structure 202 shown is the same and will not be repeated here.
[0070] See next Fig. 14B , a first pad 104 and a second pad 108 are formed on the conductive pillar 152 to obtain a semiconductor structure 308. In some embodiments, the first pad 104 and the second pad 108 can be formed by electroplating. As shown in the figure, the second pad 108 can include two metal layers 108A and 108B, and the metal layer 108B is located on the metal layer 108A.
[0071] FIG. 14C to FIG. 14E The dielectric layer 112 is formed, the first conductive bump 106 and the second conductive bump 110 are formed, and the second substrate 130 is bonded to obtain the package structure 500 and FIG. 13C to FIG. 13E The same is not repeated here.
[0072] FIG. 15A to FIG. 15E Schematic cross-sectional views of various stages of forming a package structure 600 according to another embodiment of the present application are shown. Package structure 600 is similar to package structure 400, except that second pads 156 and second conductive bumps 158 replace second pads 108 and second conductive bumps 110 in package structure 400.
[0073] See also Fig.15A , a semiconductor structure 402 is provided, and the semiconductor structure 402 is as follows Fig.13E The semiconductor structure 202 shown is the same and will not be repeated here.
[0074] See next Fig. 15B , a first pad 104 and a second pad 156 are formed on the conductive pillar 152 to obtain a semiconductor structure 408. As shown in the figure, the first pad 104 and the second pad 156 have the same size (ie, width, thickness, and length). Fig. 13BThe first pad 104 is shown as being located in the middle region, and the second pad 156 is shown as being located in the edge region. However, in other embodiments, the first pad 104 may be located in the edge region, and the second pad 156 may be located in the middle region.
[0075] See next Fig. 15C , a dielectric layer 112 is formed on the first pad 104 and the second pad 156, and openings are formed in the dielectric layer 112 to expose the first pad 104 and the second pad 156, respectively, to obtain a semiconductor structure 410. As shown in the figure, compared with the first pad 104, the portion of the dielectric layer 112 at the second pad 156 can be thicker than the portion of the dielectric layer 112 at the first pad 104, so that the height of the first region 112t1 of the dielectric layer 112 is lower than the height of the second region 112t2 of the dielectric layer 112. The portion of the dielectric layer 112 at the second pad 156 can be double-layered, while the portion of the dielectric layer 112 at the first pad 104 can be single-layered.
[0076] See next Fig.15D , first conductive bumps 106 and second conductive bumps 158 are formed in the openings of dielectric layer 112 that expose first pad 104 and second pad 156 , respectively, to obtain semiconductor structure 412 . Second conductive bumps 158 are thicker than first conductive bumps 106 .
[0077] See next Fig.15E ,Will Fig.15D The semiconductor structure 412 is turned upside down, and the semiconductor structure 412 is bonded to the second substrate 130, and a filling layer 140 is formed to obtain a packaging structure 600. The carrier glass 204 (see Fig.15D ) may occur before or after the semiconductor structure 412 is bonded to the second substrate 130 .
[0078] According to another aspect of the present application, another packaging structure is provided. Figure 4AThe package structure 100 includes a first substrate 102, a first pad 104 and a second pad 108 disposed on the first substrate 102, and a first conductive bump 106 and a second conductive bump 110 disposed on the first pad 104 and the second pad 108, respectively, wherein the thickness of the first pad 104 is less than the thickness of the second pad 108 so that the upper surface 106t of the first conductive bump 106 is lower than the upper surface 110t of the second conductive bump 110. By setting the thickness of the first pad 104 to be less than the thickness of the second pad 108 so that the upper surface 106t of the first conductive bump 106 is lower than the upper surface 110t of the second conductive bump 110, the second pad 108 can be used to pad the second conductive bump 110, so that a height difference is generated between the first conductive bump 106 and the second conductive bump 110, thereby at least reducing the risk of bridging between the first conductive bump 106 and the second conductive bump 110.
[0079] In the package structure provided by the utility model, the second conductive bump is raised by the second pad, so that a height difference is generated between the first conductive bump and the second conductive bump, thereby reducing the risk of bridging of the first solder ball and the second solder ball respectively located on the first conductive bump and the second conductive bump. In addition, in an embodiment where the package structure includes a warped second substrate, by using the first conductive bump with the height difference to join with the second conductive bump, the first conductive bump can be set at a position with a smaller distance from the second substrate (for example, the middle area), and the second conductive bump raised by the second pad can be set at a position with a larger distance from the second substrate (for example, the corner area). In this way, the technical problem of non-joining caused by the warping of the second substrate can be avoided by the first conductive bump and the second conductive bump with different heights. In addition, the present application can generate pads of different thicknesses to raise the conductive bumps (for example, the conductive bumps located in the corner area) that are easily affected by the warping formed later by the characteristics of the electroplating process itself, so that the problem of non-joining can be improved by 80%. In some embodiments, the first substrate and the second substrate can be wafers.
[0080] It should be understood that the various features of the various embodiments of the present application can be replaced and combined. The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any combination of the various embodiments within the spirit and principle of the present application, as well as any modification, equivalent replacement, improvement, etc. made to the embodiments, shall be included in the protection scope of the present application.
Claims
1. A packaging structure, characterized in that: include: a first substrate; A first pad is disposed on the first substrate, wherein the first pad has a first upper surface and a first bottom surface opposite to the first upper surface; A first conductive bump, disposed on the first upper surface; A second pad is disposed on the first substrate, the second pad having a second upper surface and a second bottom surface opposite to the second upper surface, the second upper surface is higher than the first upper surface, and the second bottom surface is aligned with the first bottom surface; a second conductive bump disposed on the second upper surface, wherein the upper surface of the second conductive bump is higher than the upper surface of the first conductive bump, a first solder ball, located on the first conductive bump; as well as The second solder ball is located on the second conductive bump.
2. The packaging structure according to claim 1, characterized in that: Also included is a dielectric layer encapsulating the first pad and the second pad, wherein the dielectric layer exposes an upper surface of the first conductive bump and an upper surface of the second conductive bump, The upper surface of the dielectric layer includes a first region located above the first pad and a second region located above the second pad, and a height of the first region is lower than a height of the second region.
3. The packaging structure according to claim 2, characterized in that: The upper surface of the dielectric layer further includes a connection surface connecting the first region and the second region, and the first region, the connection surface and the second region are connected together to form a step shape.
4. The packaging structure according to claim 1, characterized in that: The first conductive bump and the second conductive bump are arranged side by side along a first direction, and in the first direction, a width of the first conductive bump is equal to a width of the second conductive bump.
5. The packaging structure according to claim 1, characterized in that: The first conductive bump and the second conductive bump are arranged side by side along a first direction, and in the first direction, a width of the first pad is smaller than a width of the second pad.
6. The packaging structure according to claim 5, characterized in that: The thickness of the first pad is smaller than the thickness of the second pad.
7. The packaging structure according to claim 1, characterized in that: It also includes a second substrate arranged above the first substrate, the second substrate is electrically connected to the first substrate through the first solder ball and the second solder ball, and the distance between the lower surface of the second substrate and the first bottom surface of the first solder pad is smaller than the distance between the lower surface of the second substrate and the second bottom surface of the second solder pad.
8. The packaging structure according to claim 7, characterized in that: A third area of the lower surface of the second substrate is located above the first conductive bump, and a fourth area of the lower surface of the second substrate is located above the second conductive bump, and the third area is closer to the upper surface of the first substrate than the fourth area.
9. The packaging structure according to claim 7, characterized in that: A lower surface of the second substrate protrudes toward the first substrate.
10. The packaging structure according to claim 7, characterized in that: The invention also includes a third solder pad and a fourth solder pad located on the lower surface of the second substrate, wherein the third solder pad and the fourth solder pad electrically connect the second substrate to the first solder ball and the second solder ball, respectively.