Device and electronic device
By designing the structure of the trench including air bags around the three-dimensional capacitor in electronic devices, the problems of plate deformation and trench electroactivity during the manufacturing process are solved, and efficient and stable capacitor performance is achieved.
Patent Information
- Application Number
- CN202421467288.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2024-06-14
- Filing Date
- 2024-06-25
- Publication Date
- 2025-05-30
- Estimated Expiration
- 2034-06-25
AI Technical Summary
In existing electronic devices, there is a problem of plate deformation during the manufacturing process of three-dimensional capacitors, and the electroactivity of the trench affects the efficiency of the capacitor.
An electronic device is designed, including at least two three-dimensional capacitors, each surrounded by a groove including an air bag. By forming capacitors and grooves in the first insulating layer and absorbing stress using air bags, the plate is avoided while maintaining inelectroactiveness of the grooves.
This achieves avoiding plate deformation during the manufacturing process and maintaining efficient performance of the capacitor while avoiding potential problems caused by the electroactivity of the trench.
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Figure CN222927501U_ABST
Abstract
Description
[0001] Cross-reference to related applications
[0002] This application claims the benefit of priority of French Patent Application No. FR2306700, entitled "Dispositif électronique", filed on June 27, 2023, which is incorporated herein by reference in its entirety to the maximum extent permitted by law. Technical field
[0003] The present disclosure generally relates to electronic devices and methods of manufacturing the same, and to devices including three-dimensional capacitors. Background art
[0004] There are several types of capacitors. A particularly common type of capacitor corresponds to the so-called MOM capacitor or metal-oxide-metal capacitor. Such a capacitor includes a stack of two conductive layers (preferably made of metal), which are separated by an insulating layer (preferably made of an oxide, such as silicon oxide).
[0005] The MOM capacitor can be, for example, planar, i.e., the stack covers a planar layer. The MOM capacitor can also be three-dimensional, i.e., it covers a non-planar layer, such as including cavities. Thus, for the same chip surface area, a three-dimensional capacitor can have a capacitance significantly higher than that of a planar capacitor. Summary of the invention
[0006] Embodiments overcome all or part of the disadvantages of known electronic devices.
[0007] One embodiment provides an electronic device including at least two three-dimensional capacitors, each capacitor being surrounded by a trench including an air bag.
[0008] Another embodiment provides a method of manufacturing an electronic device, the method including forming at least two three-dimensional capacitors, each capacitor being surrounded by a trench including an air bag.
[0009] According to one embodiment, the capacitors and the trenches are in a first insulating layer.
[0010] According to one embodiment, each capacitor is located in a first region of a first layer, and each trench is located in a second region of the first layer, and the second region is separated from the first region by a third region of the first layer.
[0011] According to one embodiment, each third region is not covered by a conductive material.
[0012] According to one embodiment, each capacitor includes a first stack of two conductive layers separated by an insulating layer, the first stack conformally extending over the first region of the first layer, the first region including at least two first cavities, and the first stack filling the first cavities.
[0013] According to one embodiment, each trench includes a second stack of layers identical to those of the first stack, the second stack extending conformally in a second cavity, and an airbag located in the second cavity and partially defined by the second stack.
[0014] According to one embodiment, the device includes a second layer that encloses each second cavity and partially defines the airbag located in the second cavity.
[0015] According to one embodiment, each first region is covered with a third layer made of the material of the second layer.
[0016] According to one embodiment, the second layer extends in the second cavity by less than 20% of the height of the second cavity.
[0017] According to one embodiment, each airbag extends to at least half of the height of the first cavity.
[0018] According to one embodiment, the trenches surrounding at least two adjacent capacitors include a common portion.
[0019] According to one embodiment, the trenches surrounding at least two adjacent capacitors are separated from each other by a portion of the first layer.
[0020] According to one embodiment, the device includes a filter, and the capacitors form part of the filter.
[0021] According to one embodiment, the method includes: forming a first cavity and a second cavity in a first layer; forming a third stack of two conductive layers separated by an insulating layer in a conformal form, the first cavity being filled while the second cavity is not filled, forming a fourth non-conformal layer that encloses the second cavity; etching the third stack and a fourth layer in a third region to form the first stack and the second stack, and the second layer and the third layer.
[0022] According to one embodiment, the formation of the fourth layer is performed by physical vapor deposition or plasma-enhanced chemical vapor deposition.
[0023] According to one aspect of the present disclosure, there is provided an electronic device including: a first insulating layer; at least two three-dimensional capacitors in the first insulating layer; and a plurality of trenches in the first insulating layer surrounding the at least two capacitors, each of the plurality of trenches including an airbag.
[0024] According to one embodiment, the first insulating layer includes a first plurality of cavities.
[0025] According to one embodiment, each capacitor is located in a first region of the first insulating layer, each trench is located in a second region of the first insulating layer, and the second region of the first insulating layer is separated from the first region along a first direction by a third region of the first insulating layer.
[0026] According to one embodiment, each capacitor includes a first stack of two conductive layers separated by a second insulating layer, the first stack extending over a first region of the first insulating layer and filling the first plurality of cavities.
[0027] According to one embodiment, each of the plurality of trenches includes a second stack having the same layers as the first stack, the second stack extending into a second cavity, and an air pocket being located in the second cavity.
[0028] According to one embodiment, each first stack is separated from a corresponding second stack by a first gap in a first direction, each first gap overlapping a corresponding third region.
[0029] According to one embodiment, the device includes a second layer that encloses each of the plurality of trenches and partially defines the air pocket located in the second cavity.
[0030] According to one embodiment, each first region is covered by a third layer made of the material of the second layer.
[0031] According to one embodiment, the second layer extends in a second direction perpendicular to the first direction in the second cavity by less than 20% of the depth of the second cavity.
[0032] According to one embodiment, each air pocket extends in the second direction by at least half of the depth of the first cavity.
[0033] According to one embodiment, the plurality of trenches surrounding the at least two capacitors are shared by the at least two capacitors.
[0034] According to one embodiment, the plurality of trenches surrounding the at least two capacitors are separated from each other by a plurality of portions of the first insulating layer.
[0035] According to one embodiment, the device includes a filter that includes the at least two capacitors.
[0036] According to another aspect of the present disclosure, there is provided a device including: a first insulating layer having a first surface; a first plurality of trenches extending in a first direction from the first surface in the first insulating layer; a second plurality of trenches separated from the first plurality of trenches in a second direction perpendicular to the first direction, the second plurality of trenches extending in the first direction from the first surface; air-filled cavities in each of the second plurality of trenches; and a first stack of layers in the first plurality of trenches.
[0037] According to one embodiment, the first stack of layers includes: a first conductive layer directly on a substrate in the first plurality of trenches; a second insulating layer on the first conductive layer; and a second conductive layer on the second insulating layer.
[0038] According to one embodiment, the device further includes a second stack of layers in each of the second plurality of trenches, the second stack of layers being separated from the first stack of layers along a second direction.
[0039] According to one embodiment, the device further includes a first cover layer on the second plurality of trenches. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] The above and other features and advantages, as well as other features and advantages, will be described in detail in the remainder of the disclosure of specific embodiments given in a illustrative rather than restrictive manner with reference to the accompanying drawings, in which:
[0041] Figure 1A A cross-sectional view of an embodiment of a device including a three-dimensional capacitor is shown;
[0042] Figure 1B Is shown Figure 1A a top view of an embodiment of;
[0043] Figure 2A Shows the manufacturing Figure 1A and Figure 1B a step of the method of the device of;
[0044] Figure 2B Shows the manufacturing Figure 1A and Figure 1B another step of the method of the device of;
[0045] Figure 2C Shows the manufacturing Figure 1A and Figure 1B another step of the method of the device of;
[0046] Figure 3A and Figure 3B Show the illustration Figure 1A and Figure 1B two views of two arrangements of the capacitor of; DETAILED DESCRIPTION
[0047] In the various figures, like features have been indicated with like reference numerals. Specifically, the common structural and / or functional features in the various embodiments may have the same reference numerals and may be arranged with the same structure, dimensions, and material properties.
[0048] For clarity, only the steps and elements that contribute to understanding the described embodiments have been illustrated and described in detail.
[0049] Unless otherwise specified, when referring to two elements being connected together, this means a direct connection without any intermediate element other than a conductor, and when referring to two elements being coupled together, this means that the two elements can be connected or they can be coupled via one or more other elements.
[0050] In the following description, when referring to terms that define an absolute position (such as the terms "edge", "rear / back", "top", "bottom", "left", "right", etc.), or terms that define a relative position (such as the terms "upper", "lower", "upper part", "lower part", etc.), or terms that define a direction (such as the terms "horizontal", "vertical", etc.), unless otherwise specified, it refers to the orientation of the accompanying drawings.
[0051] Unless otherwise specified, the expressions "about", "approximately", "substantially" and "circa" mean plus or minus 10%, preferably plus or minus 5%.
[0052] Figure 1A A cross-sectional view of a device 10 including a three-dimensional capacitor 12 is shown. Figure 1B Shown is Figure 1A a top view of an embodiment of
[0053] The device 10 includes an insulating layer 14. The layer 14 is made of an electrically insulating material (such as silicon oxide), for example. The layer 14 corresponds to a layer of a metallization level of an interconnect network, for example. Thus, the layer 14 covers a semiconductor substrate (not shown), for example. The layer 14 covers one or more other insulating layers, for example, each of the other insulating layers includes a metallization or a conductive via.
[0054] The layer 14 includes a collection of cavities 16. The cavities 16 are of the same size, for example. Each trench 16 extends from the upper surface of the layer 14 to an internal level of the layer 14. In other words, each trench does not penetrate the layer 14. In other words, the height of the cavity 16 is lower than the height of the layer 14.
[0055] The collection of cavities 16 are all present in a region 17 of the layer 14. The collection of cavities 16 are arranged in an array in the region 17, for example. Each collection of cavities 16 includes at least two cavities (between 2 and 3000 cavities), for example. Each cavity 16 is separated from the nearest cavity 16 in the same collection only by a portion of the layer 14.
[0056] The capacitor 12 is formed inside and on top of the cavity 16. The capacitor 12 is a metal-insulator-metal capacitor, for example. In other words, the capacitor 12 includes a conductive layer 18, an insulating layer 20 and a conductive layer 22. The conductive layers 18 and 22 are made of metal, for example. The layer 20 is made of a dielectric material.
[0057] The layer 18 corresponding to the lower electrode of the capacitor 12 covers the walls and the bottom of the cavities 16 of the set. The layer 18 also covers the portions of the upper surface of the layer 14 located between the cavities 16 and the portions of the upper surface of the layer 14 surrounding the cavities 16. In other words, the layer 18 completely covers the upper surface of the region 17 of the layer 14 and the interior of the cavities 16. Thus, the layer 18 conformally covers the region 17 of the layer 14.
[0058] The layer 20 extends over the layer 18, for example, over the entire layer 18. The layer 20 extends conformally over the layer 18. The layer 20 extends over the portions of the layer 18 located in the cavities 16 and over the portions of the layer 18 located on the upper surface of the layer 14.
[0059] The layer 22 corresponding to the upper electrode of the capacitor 12 extends over the layer 20, for example, over the entire layer 20. Specifically, the layer 22 extends in the cavities 16, preferably extending at least half of the height of the cavities 16. The dimensions of the cavities 16 and the layers 18, 20, 22 are selected such that the cavities 16 are completely filled by the layers 18, 20, 22.
[0060] The layers 18, 20, 22 only extend in the region 17. The region 17 is surrounded by the region 24 of the layer 14. The layers 18, 20, 22 do not extend over the upper surface of the region 24.
[0061] The region 24 is preferably made only of the material of the layer 14. The region 24 preferably does not include a conductive material. The region 24 is preferably not covered by a conductive material.
[0062] The layer 14 also includes a region 26. The region 26 surrounds the region 24. Thus the region 26 surrounds the region 17. The region 26 (preferably at all points) is separated from the region 17 by the region 24.
[0063] The device 10 includes a trench 27. The trench 27 includes a cavity 28 located in the region 26. The cavity 28 forms a ring. The cavity 28 surrounds the regions 17 and 24. Thus, the cavity 28 surrounds the set of cavities 16.
[0064] The dimensions of the cavity 28 are preferably larger than the dimensions of one of the cavities 16. More specifically, the height of the cavity 28 is preferably greater than the height of one of the cavities 16. At least one of the dimensions of the opening of the cavity 28, i.e., the dimensions of the cavity 28 in the plane of the upper surface of the layer 14, is larger than the dimensions of the opening of one of the cavities 16. Preferably, all the dimensions of the opening of the cavity 28 are larger than the dimensions of the opening of the cavity 16.
[0065] The trench 27 includes a stack of layers 30, 32, 34 that conformally extends in region 26. Layer 30 is made of the same material as layer 18 and has a thickness that is substantially equal to the thickness of layer 18. Similarly, layer 32 is made of the same material as layer 20 and has a thickness that is substantially equal to the thickness of layer 20. Similarly, layer 34 is made of the same material as layer 22 and has a thickness that is substantially equal to the thickness of layer 22.
[0066] Layer 30 conformally covers region 26. Thus, layer 30 covers the sidewalls and bottom of cavity 28. Layer 30 also covers a portion of the upper surface of layer 14 that is located in region 26.
[0067] Layer 32 conformally covers layer 30. Preferably, layer 30 is completely covered by layer 32. Thus, layer 32 extends in cavity 28 and above the upper surface of region 26.
[0068] Layer 34 conformally covers layer 32. Preferably, layer 32 is completely covered by layer 34. Thus, layer 34 extends in cavity 28 and above the upper surface of region 26.
[0069] Layers 30, 32, 34 only extend in region 26. Layers 30, 32, 34 do not extend above the upper surface of region 24.
[0070] The trench 27 also includes layer 36. Layer 36 extends over a portion of layer 34 that is located outside cavity 28. Thus, layer 36 extends in front of the upper surface of region 26. Layer 36 also extends over the opening of cavity 28. Cavity 28 is thus enclosed by layer 36. Layer 36 preferably includes a first portion that extends in the plane of the upper surface of layer 14 and a second portion that extends in the upper portion of the cavity. Preferably, the second portion extends from the opening of cavity 28 to a height that is less than 20% of the height of cavity 28, preferably to a height that is less than 10% of the height of cavity 28. Layer 36 does not fill cavity 28. Thus, a cavity or pocket 37 filled with a gas (such as air) remains in cavity 28. Pocket 37 is defined by layer 34 and layer 36. Pocket 37 preferably extends for at least 50% of the height of cavity 16, more preferably for at least 75% of the height of cavity 16.
[0071] Device 10 also includes layer 38 made of the material of layer 36. Layer 38 preferably completely covers layer 22.
[0072] Layer 36 preferably does not extend above the upper surface of region 24. Similarly, layer 38 preferably does not extend above the upper surface of region 24.
[0073] Layers 36 and 38 are made of, for example, an insulating material or a conductive material, such as a metal.
[0074] For example, device 10 includes connection elements (not shown) that enable the connection of the upper electrode 22 and the lower electrode 18 of capacitor 12 to a circuit. The connection elements correspond, for example, to conductive vias that pass through layer 38 to layer 22 or that pass through layers 38 and 20 to layer 18 in a portion of layer 20 that is not covered by layer 22.
[0075] Filling cavity 16 with a material layer creates stress on layer 14. More specifically, filling cavity 16 with a material layer creates a lateral stress on layer 14, as Figure 1A and Figure 1B indicated by the arrows in. The filling of each cavity 16 creates stress that adds to the stress generated by the other cavities 16. During the formation of a board that includes only filled cavities 16, the filling of the cavities 16 may create stress sufficient to distort the board, thus disrupting the manufacturing steps. A distorted board may not be able to be fed into a machine that performs the steps of the manufacturing method.
[0076] Pocket 37 enables the absorption of stress generated by layers 18, 20, 22 in cavity 16. Thus, regions 17 and 24 are subjected to the stress generated by layers 18, 20, 22 in cavity 16 located in region 17, but not to the stress generated by other regions 17 located outside trench 27.
[0077] Trench 27 is preferably electrically insulating. In other words, layers 30, 32, 34 are preferably not coupled to electronic components and not coupled to conductive elements. For example, the sole purpose of trench 27 is to absorb the stress generated by capacitor 12.
[0078] The presence of gas in pocket 37 may cause unwanted elements to be present in the cavity and in contact with layer 34. However, since trench 27 does not have an electrical function, the formation of defects on layer 34 does not change the absorption of the stress generated by capacitor 12.
[0079] Figures 2A to 2C Shows the steps of a method for manufacturing Figure 1A and Figure 1B device 10, preferably in succession.
[0080] Figure 2A Shows the steps of a method for manufacturing Figure 1A and 1B a device.
[0081] During this step, layer 14 is formed. Layer 14 is formed, for example, on a substrate or support (not shown). Layer 14 is, for example, a planar layer. Then the upper and lower surfaces of layer 14 are parallel.
[0082] Figure 2AThe steps then include forming cavity 16 in region 17 and forming cavity 28 in region 26. The formation of cavities 16 and 28 is preferably carried out simultaneously by the same etching step.
[0083] Forming cavities 16 and 28 includes, for example, forming a mask (not shown) over the upper surface of layer 14. The mask (not shown) includes openings facing the positions of cavities 16 and 18, and the size of the openings is substantially equal to the size of the openings of cavities 16 and 18. Forming the cavities then includes etching layer 14 through the mask openings. The difference between the size of the opening of trench 16 and the size of the opening of trench 28 results in a height difference of the cavities formed during etching.
[0084] Figure 2B Illustrates another step of the method of manufacturing Figure 1A and Figure 1B the device.
[0085] During this step, a stack of layers 40, 42, 44 is conformally formed over at least regions 17, 24, and 26, preferably over the entire layer 14.
[0086] Layer 40 is made of the materials of layers 18 and 30. The thickness of layer 40 is substantially equal to the thickness of layers 18 and 30. Layer 42 is made of the materials of layers 20 and 32. The thickness of layer 42 is substantially equal to the thickness of layers 20 and 32. Layer 44 is made of the materials of layers 22 and 34. The thickness of layer 44 is substantially equal to the thickness of layers 22 and 34.
[0087] Layer 40 conformally covers regions 17, 24, 28. Preferably, layer 40 conformally covers the entire layer 14. Thus, layer 40 covers the sidewalls and bottoms of cavities 16 and 28. Layer 40 also covers the upper surfaces of regions 17, 24, 26 of layer 14.
[0088] Layer 42 conformally covers layer 40. Preferably, layer 42 completely covers layer 40. Specifically, layer 42 covers the portions of layer 40 located in cavities 16 and 28 and on the upper surfaces of regions 17, 24, 26.
[0089] Similarly, layer 44 conformally covers layer 42. Preferably, layer 44 completely covers layer 42. Specifically, layer 44 covers the portions of layer 42 located in cavities 16 and 28 and on the upper surfaces of regions 17, 24, 26. The thickness of layer 44 is such that after forming layer 44, cavity 16 is filled with the stack of layers 40, 42, 44. The thicknesses of layers 40, 42, 44 are such that cavity 28 is not filled with layers 40, 42, 44. The dimensions of cavity 28 and layers 40, 42, 44 are such that the portions of layer 44 extending above the opposite sidewalls of cavity 28 for at least half of the height of cavity 28 do not touch.
[0090] Figure 2C shows another step of a method of manufacturing Figure 1A and Figure 1B a device.
[0091] During this step, a non-conformal layer 46 is formed on the structure resulting from the step of Figure 2B . The layer 46 is made of the materials of layers 36 and 38. The layer 46 is formed in such a way as to enclose the cavity 28 while holding the air bag 37 in the cavity 28. The layer 46 is formed, for example, by physical vapor deposition (PVD) method and the layer 46 is made of metal, for example, or by plasma enhanced chemical vapor deposition (PECVD) method and the layer 46 is made of a dielectric (such as silicon oxide), for example.
[0092] After the step of Figure 2C , the method further includes the step of etching portions of the layers 40, 42, 44, 46 located on the region 24. Thereby, the layers 18, 20, 22, 30, 32, 34 are formed.
[0093] The method further includes forming connection elements (not shown) allowing the connection of the electrodes 18 and 22.
[0094] Figure 3A and Figure 3B shows two views Figure 1A and Figure 1B illustrating two arrangements of the capacitor shown in Figure 3A and 3B . Each arrangement includes four capacitors 12. However, the device may include any number of capacitors 12, for example, at least two capacitors. The capacitors 12 are used in a filter, for example.
[0095] In Figure 3A and Figure 3B , the region 26 including the trench 27 is shown by a single line, the region 17 including the capacitor 12 is shown by a shaded rectangle, and the region 24 separating the regions 26 and 17 is shown by a white strip of a separated rectangle and a single line.
[0096] According to the embodiment of view Figure 3A , a first example of the arrangement is illustrated, where the trench 27 forms a grid defining the region 24. In the embodiment of view Figure 3A , the trench 27 forms columns and rows of a grid and defines an array of positions, each position including the region 17 and the region 24, preferably, including a single region 17 and a single region 24. Thus, all the trenches 27 are coupled to each other.
[0097] Two adjacent capacitors are separated by a single trench 27. Thus, two adjacent capacitors are separated by a portion of the region 24, the trench 27, and a portion of another region 24.
[0098] According to the view Figure 3BAn embodiment illustrates a second example of the arrangement. The device includes an array of components. The components include region 17, region 24, and region 26. Different components are separated from each other by portion 50 of substrate 14. Thus, trenches 27 are independent of each other. In other words, trenches 27 are separated from each other by portion 50.
[0099] Two adjacent capacitors are separated by two trenches 27. Thus, two adjacent capacitors are separated by a portion of region 24, trench 27, portion 50, trench 27, and a portion of another region 24.
[0100] Although in Figure 3A and Figure 3B the capacitors 12 are aligned in rows and columns, the capacitors can be aligned in rows, for example, and have offset columns.
[0101] In addition, a device including capacitors 12 can include a portion where the capacitors are arranged according to a first arrangement and a portion where the capacitors are arranged according to a second arrangement.
[0102] One advantage of the described embodiment is that a board with high-density three-dimensional capacitors can be formed without causing any deformation.
[0103] Another advantage of the described embodiment is that since trenches 27 are not electroactive, the presence of air pockets does not cause any damage and does not affect the efficiency of the capacitors.
[0104] Another advantage of the described embodiment is that forming trenches 27 and capacitors 12 simultaneously enables avoiding deformation of the board and enables avoiding an increase in the forming steps.
[0105] Multiple embodiments and variant embodiments have been described. Those skilled in the art will understand that certain features of these multiple embodiments and variant embodiments can be combined, and those skilled in the art will conceive of other variant embodiments.
[0106] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variant embodiments is within the capabilities of those skilled in the art.
[0107] An electronic device (10) includes at least two three-dimensional capacitors (12), each capacitor (12) being surrounded by a trench (27) including an air pocket (37).
[0108] A method of manufacturing an electronic device (10) includes forming at least two three-dimensional capacitors (12), each capacitor (12) being surrounded by a trench (27) including an air pocket (37).
[0109] The capacitors (12) and trenches (27) are in a first insulating layer (14).
[0110] Each capacitor (12) is located in a first region (17) of a first layer (14), and each trench (27) is located in a second region (26) of the first layer (14). The second region of the first layer is separated from the first region (17) by a third region (24) of the first layer (14).
[0111] Each third region (24) is not covered with a conductive material.
[0112] Each capacitor (12) includes a first stack (18, 20, 22) of two conductive layers separated by an insulating layer. The first stack extends conformally over the first region of the first layer, which includes at least two first cavities (16). The first stack fills the first cavities (16).
[0113] Each trench (27) includes a second stack (30, 32, 34) of the same layers as the first stack (18, 20, 22). The second stack extends conformally in a second cavity (28). An air pocket (37) is located in the second cavity (28) and is partially defined by the second stack (30, 32, 34).
[0114] The device (10) includes a second layer (36) that encloses each second cavity (28) and partially defines the air pocket (37) located in the second cavity.
[0115] Each first region (17) is covered with a third layer (38) made of the material of the second layer (36).
[0116] The second layer (36) extends in the second cavity (28) for less than 20% of the height of the second cavity.
[0117] Each air pocket (37) extends for at least half of the height of the first cavity (16).
[0118] The trenches (27) surrounding at least two adjacent capacitors (12) include a common portion.
[0119] The trenches (27) surrounding at least two adjacent capacitors (12) are separated from each other by a portion (50) of the first layer.
[0120] The device includes a filter, and the capacitors form part of the filter.
[0121] The method includes forming first and second cavities in a first layer; forming a third stack of two conductive layers conformally separated by an insulating layer, with the first cavity being filled and the second cavity not being filled, forming a fourth non-conformal layer that encloses the second cavity; and etching the third stack and the fourth layer in the third region to form the first stack and the second stack, and the second layer and the third layer.
[0122] The formation of the fourth layer is carried out by physical vapor deposition method or plasma enhanced chemical vapor deposition method.
[0123] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments may be modified if concepts of various patents, applications and publications are required to provide further embodiments.
[0124] Based on the above detailed description, these and other changes can be made to the embodiments. Generally, in the appended claims, the terms used should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and the full scope of equivalent forms given by these claims. Therefore, the claims are not limited by the present disclosure.
Claims
1. An electronic device, characterized in that: include: a first insulating layer; at least two three-dimensional capacitors in the first insulating layer; as well as A plurality of trenches are formed in the first insulating layer around the at least two capacitors, each trench of the plurality of trenches comprising an air pocket.
2. The device according to claim 1, characterized in that The first insulating layer includes a first plurality of cavities.
3. The device according to claim 2, characterized in that Each capacitor is located in a first region of the first insulating layer, each trench is located in a second region of the first insulating layer, and the second region of the first insulating layer is separated from the first region along a first direction by a third region of the first insulating layer.
4. The device according to claim 3, characterized in that Each capacitor comprises a first stack of two conductive layers separated by a second insulating layer, the first stack extending over a first region of the first insulating layer and filling the first plurality of cavities.
5. The device according to claim 4, characterized in that Each of the plurality of grooves includes a second stack having the same layers as the first stack, the second stack extending into the second cavity, and the air pocket is located in the second cavity.
6. The device according to claim 5, characterized in that Each first stack is separated from a corresponding second stack along a first direction by a first gap, and each first gap overlaps with a corresponding third region.
7. The device according to claim 5, characterized in that A second layer is included that closes each of the plurality of grooves and partially defines an air pocket within the second cavity.
8. The device according to claim 7, characterized in that Each of the first regions is covered by a third layer made from the material of the second layer.
9. The device according to claim 7, characterized in that The second layer extends in the second cavity along a second direction perpendicular to the first direction to less than 20% of the depth of the second cavity.
10. The device according to claim 6, characterized in that Each of the air pockets extends along the second direction to at least half of the depth of the first cavity.
11. The device according to claim 1, characterized in that The plurality of trenches surrounding the at least two capacitors are shared by the at least two capacitors.
12. The device according to claim 1, characterized in that The plurality of trenches surrounding the at least two capacitors are separated from each other by portions of a first insulating layer.
13. The device according to claim 1, characterized in that The device comprises a filter, and the filter comprises the at least two capacitors.
14. A device, characterized in that include: A first insulating layer having a first surface; a first plurality of trenches extending in the first insulating layer from the first surface along a first direction; a second plurality of grooves separated from the first plurality of grooves along a second direction perpendicular to the first direction, the second plurality of grooves extending from the first surface along the first direction; an air-filled cavity in each groove of the second plurality of grooves; as well as A first stack of layers in the first plurality of trenches.
15. The device according to claim 14, characterized in that Wherein a first stack of layers comprises: a first conductive layer directly on the substrate in the first plurality of trenches; a second insulating layer on the first conductive layer; and The second conductive layer is on the second insulating layer.
16. The device according to claim 15, characterized in that Also included is a second stack of layers in each of the second plurality of trenches, the second stack of layers separated from the first stack of layers along a second direction.
17. The device according to claim 16, characterized in that Also included is a first capping layer on the second plurality of trenches.
Citation Information
Patent Citations
process FOR THE PRODUCTION OF CERTAIN PHOSPHONOTHIOUREIDS IN A SINGLE REACTOR
FR2306700A2