Core capacity 485 signal and address control signal switching circuit

Abstract

The utility model provides a nuclear capacity 485 signal and address control signal switching circuit which is characterized in that the nuclear capacity 485 signal and address control signal switching circuit comprises a main control chip, an RS485 communication circuit, an address signal circuit, an AND gate circuit and a phase inverter, two signal transmission pins of the RS485 communication circuit and a signal output pin of the address signal circuit are respectively connected to an RJ45 line concentration terminal, and the AND gate circuit is connected with the phase inverter. The AND gate circuit comprises a first AND gate unit and a second AND gate unit, a signal transmitting pin of the RS485 communication circuit is connected with an output pin of the first AND gate unit, and an input pin of the address signal circuit is connected with an output pin of the second AND gate unit; the main control chip is provided with a first GPIO (General Purpose Input / Output) pin for outputting or receiving a 485 communication signal in a time-sharing manner, a second GPIO pin for outputting a read-write switching signal and a third GPIO pin for outputting an address signal; the circuit is simple and ingenious in structure, not only solves the conflict problem when the capacity checking device collects multiple storage battery monomers, but also has better electrical isolation performance.

Description

Technical Field

[0001] The utility model relates to a battery core capacity device, in particular to a core capacity 485 signal and address control signal switching circuit. Background Art

[0002] Remote online battery capacity verification devices need to respond to commands from higher-level devices on the network and provide feedback on capacity data in real time. This requires establishing a communication circuit between the device and the battery cells and resolving the issue of unique address identification for the device. Furthermore, the device often needs to perform capacity verification on multiple battery cells simultaneously. When sending and receiving address signals to the battery cells, failing to report data from only one battery cell at a time can cause signal conflicts and confusion. Furthermore, the main control chip, with its limited GPIO resources, struggles to allocate more GPIO pins to control signal transmission and reception. Utility Model Content

[0003] The utility model proposes a core capacity 485 signal and address control signal switching circuit, the specific technical content of which is as follows:

[0004] A core capacity 485 signal and address control signal switching circuit, comprising a main control chip, an RS485 communication circuit, an address signal circuit, an AND gate circuit and an inverter, wherein the two signal transmission pins of the RS485 communication circuit and the signal output pin of the address signal circuit are respectively connected to the RJ45 hub terminal, the AND gate circuit comprises a first AND gate unit and a second AND gate unit, the signal transmission pin of the RS485 communication circuit is connected to the output pin of the first AND gate unit, and the input pin of the address signal circuit is connected to the output pin of the second AND gate unit; the main control chip is configured for time-sharing output or reception of 485 communication The first GPIO pin of the master control chip is connected to the output pin of the inverter, and the other input pin is connected to the first GPIO pin of the master control chip; the second GPIO pin is connected to the read-write switching pin of the RS485 communication circuit; the input pin of the inverter is connected to the third GPIO pin of the master control chip.

[0005] In one or more embodiments of the present invention, an optocoupler circuit for isolation is provided between the signal transmitting pin of the RS485 communication circuit and the output pin of the first AND gate unit, between the read / write switching pin of the RS485 communication circuit and the second GPIO pin of the main control chip, and between the signal receiving pin of the RS485 communication circuit and the first GPIO pin of the main control chip.

[0006] In one or more embodiments of the present invention, a first optocoupler circuit is provided between the signal transmission pin of the RS485 communication circuit and the output pin of the first AND gate unit. The first optocoupler circuit includes a first optocoupler unit and a first transistor. The base of the first transistor is connected to the output end of the first optocoupler unit, the collector of the first transistor is connected to the signal transmission pin of the RS485 communication circuit, and the emitter of the first transistor is grounded.

[0007] In one or more embodiments of the present invention, a second optocoupler circuit is provided between the signal receiving pin of the RS485 communication circuit and the first GPIO pin of the main control chip. The second optocoupler circuit includes a second optocoupler unit and a second transistor. The base of the second transistor is connected to the output end of the second optocoupler unit, the collector of the second transistor is connected to the first GPIO pin of the main control chip, and the emitter of the second transistor is grounded.

[0008] In one or more embodiments of the present invention, a third optocoupler circuit is provided between the read-write switching pin of the RS485 communication circuit and the second GPIO pin of the main control chip. The third optocoupler circuit includes a third optocoupler unit. The input end of the third optocoupler unit is connected to the second GPIO pin of the main control chip, and the output end thereof is connected to the read-write switching pin of the RS485 communication circuit.

[0009] In one or more embodiments of the present invention, the address signal circuit includes a fourth optocoupler unit and a transient voltage suppression diode, and the transient voltage suppression diode is connected to the output end of the fourth optocoupler unit.

[0010] In one or more embodiments of the present invention, two signal transmission pins of the RS485 communication circuit are respectively connected to transient voltage suppression diodes.

[0011] In one or more embodiments of the present invention, the AND gate circuit uses an integrated AND gate chip with multiple built-in AND gate units, wherein: two AND gate units form a group, and each group matches an RS485 communication circuit, an address signal circuit and an RJ45 hub terminal.

[0012] Compared with the prior art, the advantages of the present invention are as follows: both the 485 communication signal and the address signal are transmitted through the RJ45 hub terminal. In the default state, the 485 communication is maintained. When the main control chip initiates a one-key address signal, the combination design of the AND gate circuit and the inverter stops the reception / transmission of the 485 communication signal when the main control chip reports the address signal. After the battery cell receives the address reception request, the battery cell address is reported through the 485 communication signal. This time-sharing sampling control avoids conflicts when the core capacity device collects data from multiple battery cells, and avoids the waste of the main control chip GPIO caused by the single-machine measurement of the core capacity device. This is particularly important for core capacity occasions with multiple battery cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a principle block diagram of the utility model.

[0014] Figure 2 This is the schematic diagram of the RS485 communication circuit and address signal circuit.

[0015] Figure 3 The schematic diagram of the optocoupler circuit adapted to the RS485 communication circuit.

[0016] Figure 4 This is the circuit schematic diagram of the AND gate circuit and inverter. DETAILED DESCRIPTION

[0017] The following is combined with the attached Figures 1 to 4 , further describe this application plan:

[0018] See attached Figure 1 The core capacity 485 signal and address control signal switching circuit includes a main control chip 1, an RS485 communication circuit 2, an address signal circuit 3, an AND gate circuit 4 and an inverter 5. The signal transmission pin A and the signal transmission pin B of the RS485 communication circuit 2 and the signal output pin of the address signal circuit 3 are respectively connected to the corresponding pins of the RJ45 hub terminal. The AND gate circuit 4 includes a first AND gate unit 41 and a second AND gate unit 42. The signal transmission pin DI of the RS485 communication circuit 2 is connected to the output pin of the first AND gate unit 41, and the input pin of the address signal circuit 2 is connected to the output pin of the second AND gate unit 42; the main control chip 1 is configured with a first GPIO pin ( Figure 1 GPIO-1 in the figure), the second GPIO pin for outputting read / write switching signals ( Figure 1 GPIO-2 in the figure shown) and the third GPIO pin for outputting address signals ( Figure 1GPIO-3 in the figure); the input pin of the inverter 5 is connected to the third GPIO pin of the main control chip 1 to receive the address signal ADD_in sent by the main control chip 1, and the address signal ADD_in is inverted to generate an enable signal EN; one input pin of the first AND gate unit 41 is connected to the output pin of the inverter 5 to obtain the enable signal EN, and the other input pin is connected to the first GPIO pin of the main control chip 1 to obtain the TXD signal. Finally, according to the functional characteristics of the AND gate unit, a corresponding communication signal TXD_D_U is generated at its output pin, and the communication signal TXD_D_U is output to the RS485 communication circuit 2 signal transmitting pin DI; one input pin of the second AND gate unit 42 is connected to the first GPIO pin of the main control chip 1 to obtain the TXD signal, and the other input is connected to the third GPIO pin of the main control chip 1 to obtain the address signal ADD_in, and finally generates the corresponding address signal ADD_OUT at its output pin according to the functional characteristics of the AND gate unit; the second GPIO pin is connected to the read-write switching pin RE / DE of the RS485 communication circuit 2, and the main control chip 1 controls the switching of the receiving / sending state of the RS485 communication circuit 2; the signal receiving pin RO of the RS485 communication circuit 2 is connected to the first GPIO pin of the main chip 1.

[0019] In this circuit, the transmission and reception of 485 communication signals is implemented by one GPIO pin, while the address signal is implemented by another GPIO pin. In the default state, 485 communication is maintained. When the main control chip battery cell initiates a one-key address reception signal, the address signal ADD_in is output to a valid level, thereby generating an enable signal EN for controlling the suspension of 485 communication through the inverter. After the battery cell receives the address reception request, it reports the battery cell address through the 485 communication signal. This time-sharing control design avoids conflicts caused by multiple battery cells reporting addresses at the same time.

[0020] See attached Figure 4 The AND gate circuit 4 of this circuit utilizes an integrated AND gate chip with multiple built-in AND gate units. Two AND gate units form a group, with each group matching an RS485 communication circuit 2, an address signal circuit 3, and an RJ45 bus terminal. This allows a single device to simultaneously control the capacity of multiple battery cells. Furthermore, this circuit uses a single GPIO to control the transmission and reception of 485 communication signals, conserving GPIO resources. This allows for the design of more capacity control circuits while using the same GPIO resources as the main control chip 1. This allows a single capacity control device to simultaneously control the capacity of multiple battery cells, while avoiding the waste of the main control chip's GPIOs caused by traditional single-unit measurement. This is particularly important for multi-battery capacity control applications.

[0021] This circuit also has an isolation design. Optocoupler circuits for isolation are respectively provided between the signal transmitting pin DI of the RS485 communication circuit 2 and the output pin of the first AND gate unit, between the read-write switching pin of the RS485 communication circuit and the second GPIO pin of the main control chip, and between the signal receiving pin of the RS485 communication circuit and the first GPIO pin of the main control chip.

[0022] For details, see the attached Figure 3 A first optocoupler circuit is provided between the signal transmission pin DI of the RS485 communication circuit 2 and the output pin of the first AND gate unit 41. The first optocoupler circuit includes a first optocoupler unit U1 and a first transistor Q2. The base of the first transistor Q2 is connected to the output end of the first optocoupler unit U1, the collector of the first transistor Q2 is connected to the signal transmission pin DI of the RS485 communication circuit 2, and the emitter of the first transistor Q2 is grounded.

[0023] A second optocoupler circuit is provided between the signal receiving pin RO of the RS485 communication circuit 2 and the first GPIO pin of the main control chip 1. The second optocoupler circuit includes a second optocoupler unit U2 and a second transistor Q1. The base of the second transistor Q1 is connected to the output end of the second optocoupler unit U2, the collector of the second transistor Q1 is connected to the first GPIO pin of the main control chip 1, and the emitter of the second transistor Q1 is grounded.

[0024] A third optocoupler circuit is provided between the read-write switching pin RE / DE of the RS485 communication circuit 2 and the second GPIO pin of the main control chip 1. The third optocoupler circuit includes a third optocoupler unit U3. The input end of the third optocoupler unit U3 is connected to the second GPIO pin of the main control chip 1, and the output end thereof is connected to the read-write switching pin RE / DE of the RS485 communication circuit 2.

[0025] See attached Figure 2 The address signal circuit 3 includes a fourth optocoupler unit U4 and a transient voltage suppressor diode TVS3. The transient voltage suppressor diode TVS3 is connected to the output of the fourth optocoupler unit U4 to stabilize the voltage at the RJ45 integrated terminal pin. Similarly, the signal transmission pins A and B of the RS485 communication circuit 2 are connected to transient voltage suppressor diodes TVS1 and TVS2, respectively, to stabilize the voltage at the RJ45 integrated terminal pin.

[0026] This circuit structure is simple and ingenious. It not only solves the problem of optimizing the utilization of the GPIO resources of the main control chip under multi-core capacity circuits, but also has better electrical isolation performance to ensure stable interaction of core capacity data.

[0027] The above preferred embodiments should be regarded as examples of the implementation methods of the present application scheme. Any technical deductions, replacements, improvements, etc. that are identical or similar to the present application scheme or made based on it should be regarded as within the scope of protection of this patent.

Claims

1. A core capacity 485 signal and address control signal switching circuit, characterized in that: The invention comprises a main control chip, an RS485 communication circuit, an address signal circuit, an AND gate circuit and an inverter. The two signal transmission pins of the RS485 communication circuit and the signal output pin of the address signal circuit are respectively connected to the RJ45 hub terminal. The AND gate circuit comprises a first AND gate unit and a second AND gate unit. The signal transmission pin of the RS485 communication circuit is connected to the output pin of the first AND gate unit, and the input pin of the address signal circuit is connected to the output pin of the second AND gate unit. The main control chip is configured with a first GPIO pin for time-sharing output or reception of 485 communication signals, a second GPIO pin for outputting a read-write switching signal, and a third GPIO pin for outputting an address signal. One input pin of the first AND gate unit is connected to the output pin of the inverter, and the other input pin is connected to the first GPIO pin of the main control chip. One input pin of the second AND gate unit is connected to the first GPIO pin of the main control chip, and the other input pin is connected to the third GPIO pin of the main control chip. The second GPIO pin is connected to the read-write switching pin of the RS485 communication circuit. The input pin of the inverter is connected to the third GPIO pin of the main control chip.

2. The core capacity 485 signal and address control signal switching circuit according to claim 1, characterized in that: Optocoupler circuits for isolation are respectively provided between the signal transmitting pin of the RS485 communication circuit and the output pin of the first AND gate unit, between the read-write switching pin of the RS485 communication circuit and the second GPIO pin of the main control chip, and between the signal receiving pin of the RS485 communication circuit and the first GPIO pin of the main control chip.

3. The core capacity 485 signal and address control signal switching circuit according to claim 2, characterized in that: A first optocoupler circuit is provided between the signal transmission pin of the RS485 communication circuit and the output pin of the first AND gate unit. The first optocoupler circuit includes a first optocoupler unit and a first transistor. The base of the first transistor is connected to the output end of the first optocoupler unit, the collector of the first transistor is connected to the signal transmission pin of the RS485 communication circuit, and the emitter of the first transistor is grounded.

4. The core capacity 485 signal and address control signal switching circuit according to claim 2, characterized in that: A second optocoupler circuit is provided between the signal receiving pin of the RS485 communication circuit and the first GPIO pin of the main control chip. The second optocoupler circuit includes a second optocoupler unit and a second transistor. The base of the second transistor is connected to the output end of the second optocoupler unit, the collector of the second transistor is connected to the first GPIO pin of the main control chip, and the emitter of the second transistor is grounded.

5. The core capacity 485 signal and address control signal switching circuit according to claim 2, characterized in that: A third optocoupler circuit is provided between the read-write switching pin of the RS485 communication circuit and the second GPIO pin of the main control chip. The third optocoupler circuit includes a third optocoupler unit. The input end of the third optocoupler unit is connected to the second GPIO pin of the main control chip, and the output end thereof is connected to the read-write switching pin of the RS485 communication circuit.

6. The core capacitance 485 signal and address control signal switching circuit according to claim 1, characterized in that: The address signal circuit includes a fourth optical coupling unit and a transient voltage suppression diode, and the transient voltage suppression diode is connected to the output end of the fourth optical coupling unit.

7. The core capacity 485 signal and address control signal switching circuit according to claim 1, characterized in that: The two signal transmission pins of the RS485 communication circuit are respectively connected with transient voltage suppression diodes.

8. The core capacitance 485 signal and address control signal switching circuit according to any one of claims 1 to 7, characterized in that: The AND gate circuit adopts an integrated AND gate chip with multiple built-in AND gate units, wherein two AND gate units form a group, and each group matches an RS485 communication circuit, an address signal circuit and an RJ45 hub terminal.

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