Negative-voltage-resistant high-voltage ESD protection circuit

Abstract

The utility model discloses a high-voltage ESD protection circuit resistant to negative voltage, which comprises a first high-voltage ESD device, a low-voltage ESD breakdown device and a second high-voltage ESD device, the first high-voltage ESD device is used for releasing positive ESD energy of a chip IO interface, the low-voltage ESD breakdown device is used for releasing negative ESD energy of the chip IO interface, and the second high-voltage ESD device is used for releasing negative ESD energy of the chip IO interface. And the second high-voltage ESD device is used for isolating the positive ESD energy of the IO interface of the chip and discharging the negative ESD energy of the IO interface of the chip. The negative-voltage-resistant high-voltage ESD protection circuit can achieve high-voltage ESD protection, has the advantages of being simple in structure and small in area, and enables a chip IO interface to work normally under the negative voltage condition.

Description

Technical Field

[0001] The utility model relates to the technical field of analog circuits and semiconductor integration, and in particular to a negative pressure-resistant high-voltage ESD protection circuit. Background Art

[0002] Electrostatic discharge (ESD) refers to a phenomenon in which the chip is damaged due to the accumulation and release of static electricity during the production, manufacturing, transportation, and use of integrated circuits. With the development of modern integrated circuit technology, the feature size of transistors has become smaller and smaller, and the integration has become higher and higher, resulting in the chip's own anti-static ability becoming weaker and weaker. At the same time, the application scenarios of chips have not reduced static electricity, which has caused the ESD problem to gradually become an important issue facing modern integrated circuit design. Compared with low-voltage ESD protection, high-voltage ESD has a wide operating voltage range, and the breakdown characteristics of high-voltage devices themselves are weaker than those of low-voltage devices, which makes the design of high-voltage ESD protection circuits a difficulty in chip design. Utility Model Content

[0003] In response to the problems existing in the prior art, the utility model provides a negative pressure-resistant high-voltage ESD protection circuit, which can achieve high-voltage ESD protection, has the characteristics of simple structure and small area, and enables the chip IO interface to work normally under negative voltage conditions.

[0004] To achieve the above technical objectives, the present invention adopts the following technical solutions: a negative pressure-resistant high-voltage ESD protection circuit, comprising: a first high-voltage ESD device, a low-voltage ESD breakdown device and a second high-voltage ESD device, the first high-voltage ESD device being used to release the positive ESD energy of the chip IO interface, the low-voltage ESD breakdown device being used to release the negative ESD energy of the chip IO interface, and the second high-voltage ESD device being used to isolate the positive ESD energy of the chip IO interface and discharge the negative ESD energy of the chip IO interface.

[0005] Furthermore, the first high-voltage ESD device is a first high-voltage N-type MOS transistor, the gate and source of the first high-voltage N-type MOS transistor are short-circuited, the source of the first high-voltage N-type MOS transistor is also connected to the chip IO interface, and the drain of the first high-voltage N-type MOS transistor is connected to the power supply.

[0006] Furthermore, a resistor is connected in series between the gate and source of the first high-voltage N-type MOS transistor.

[0007] Furthermore, the first high-voltage ESD device is a first high-voltage diode, an anode of the first high-voltage diode is connected to the chip IO interface, and a cathode of the first high-voltage diode is connected to a power supply.

[0008] Furthermore, the low-voltage ESD breakdown device is composed of a fully isolated low-voltage N-type enhancement MOS transistor and a resistor. The source of the fully isolated low-voltage N-type enhancement MOS transistor is connected to the chip IO interface, the gate of the fully isolated low-voltage N-type enhancement MOS transistor is connected to one end of the resistor, and the other end of the resistor is connected to the drain of the fully isolated low-voltage N-type enhancement MOS transistor. The drain of the fully isolated low-voltage N-type enhancement MOS transistor is also connected to the isolation well ISO.

[0009] Furthermore, a resistor is connected in series between the drain of the fully isolated low-voltage N-type enhancement mode MOS transistor and the isolation well ISO.

[0010] Furthermore, the second high-voltage ESD device is a second high-voltage N-type MOS transistor, the source and gate of the second high-voltage N-type MOS transistor are short-circuited, and the source of the second high-voltage N-type MOS transistor is also grounded; the drain of the second high-voltage N-type MOS transistor is connected to one end of the fully isolated low-voltage N-type enhancement MOS transistor and the resistor.

[0011] Furthermore, a resistor is connected in series between the source and the gate of the second high-voltage N-type MOS transistor.

[0012] Furthermore, the second high-voltage ESD device is a second high-voltage diode, the anode of the second high-voltage diode is grounded, and the cathode of the second high-voltage diode is connected to one end of the fully isolated low-voltage N-type enhancement mode MOS transistor and the resistor.

[0013] Compared with the prior art, the present invention has the following beneficial effects: when the chip IO interface is in positive ESD, the ESD energy is directly discharged into the power path by the first high-voltage ESD device; when the chip IO interface is in negative ESD, the ESD energy first passes through the second high-voltage ESD device, and then breaks down the low-voltage ESD breakdown device to form a discharge path, releasing ESD energy, so that the high-voltage ESD protection circuit has the characteristic of being resistant to negative pressure; and the first high-voltage ESD device and the second high-voltage ESD device are in positive conduction rather than breakdown during the ESD discharge process, so the area of the first high-voltage ESD device and the second high-voltage ESD device can be made relatively small, and although the low-voltage ESD breakdown device is in breakdown conduction during the ESD discharge process, it is a low-voltage device, so the area can also be made relatively small in comparison. Therefore, the present invention makes full use of the high voltage resistance of the high-voltage device and the easy breakdown characteristics of the low-voltage device, and realizes the negative pressure resistance of the high-voltage ESD protection circuit with a simple circuit and a small area. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a block diagram of the negative pressure-resistant high-voltage ESD protection circuit of the utility model;

[0015] Figure 2 A circuit structure diagram of a negative pressure-resistant high-voltage ESD protection circuit provided by the utility model;

[0016] Figure 3 This is a circuit structure diagram of another negative pressure-resistant high-voltage ESD protection circuit provided by the utility model. DETAILED DESCRIPTION

[0017] The technical solution of the present utility model will be further explained below with reference to the accompanying drawings.

[0018] like Figure 1 This is a block diagram of a negative-pressure-resistant high-voltage ESD protection circuit of the utility model. The high-voltage ESD protection circuit includes: a first high-voltage ESD device 11, a low-voltage ESD breakdown device 12, and a second high-voltage ESD device 13. The first high-voltage ESD device 11 is used to release the positive ESD energy of the chip IO interface; the low-voltage ESD breakdown device 12 is used to release the negative ESD energy of the chip IO interface; the second high-voltage ESD device 13 is used to isolate the positive ESD energy of the chip IO interface and discharge the negative ESD energy of the chip IO interface, thereby protecting the low-voltage ESD breakdown device 12. The high-voltage ESD protection circuit of the present invention has two working states: (1) When the chip IO interface is in the normal working range and is at high voltage, the low-voltage ESD breakdown device 12 will work in a safe area due to the protection of the second high-voltage ESD device 13; when the chip IO interface is in the normal working range and is at negative pressure, the second high-voltage ESD device 13 will be in a forward conduction state, and the negative pressure can be transmitted to the low-voltage ESD breakdown device 12, and the negative pressure will be isolated by the low-voltage ESD breakdown device 12; (2) The chip IO interface is in an ESD discharge state: When the chip IO interface is in a forward ESD state, the ESD energy is blocked by the first high-voltage ESD device 13. The ESD device 11 is directly discharged into the power path; when the chip IO interface is in negative ESD, the ESD energy first passes through the second high-voltage ESD device 13, and then breaks down the low-voltage ESD breakdown device 12 to form a discharge path. The first high-voltage ESD device 11 and the second high-voltage ESD device 13 are in forward conduction rather than breakdown during the ESD discharge process, so the area of the first high-voltage ESD device 11 and the second high-voltage ESD device 13 can be made relatively small. Although the protection low-voltage ESD breakdown device 12 is breakdown-conducted during the ESD discharge process, it is a low-voltage device, so the area can also be made relatively small in comparison. The utility model fully utilizes the high voltage resistance of high-voltage devices and the easy breakdown characteristics of low-voltage devices, and realizes a high-voltage ESD protection circuit that can withstand negative pressure with a simple circuit and a small area.

[0019] like Figure 2This is a circuit structure diagram of a negative-voltage-resistant high-voltage ESD protection circuit provided by the present invention. In the high-voltage ESD protection circuit, the first high-voltage ESD device 11 is a first high-voltage N-type MOS transistor 21. The gate and source of the first high-voltage N-type MOS transistor 21 are short-circuited. The source of the first high-voltage N-type MOS transistor 21 is also connected to the chip IO interface, and the drain of the first high-voltage N-type MOS transistor 21 is connected to the power supply. The low-voltage ESD breakdown device 12 is composed of a fully isolated low-voltage N-type enhancement-type MOS transistor 24 and a resistor 26. The source of the fully isolated low-voltage N-type enhancement-type MOS transistor 24 is connected to the chip IO interface. The gate of the fully isolated low-voltage N-type enhancement-mode MOS transistor 24 is connected to one end of a resistor 26, the other end of which is connected to the drain of the fully isolated low-voltage N-type enhancement-mode MOS transistor 24. The drain of the fully isolated low-voltage N-type enhancement-mode MOS transistor 24 is also connected to the isolation well ISO. The second high-voltage ESD device 13 is a second high-voltage N-type MOS transistor 25. The source and gate of the second high-voltage N-type MOS transistor 25 are short-circuited, and the source of the second high-voltage N-type MOS transistor 25 is also grounded. The drain of the second high-voltage N-type MOS transistor 25 is connected to the end of the fully isolated low-voltage N-type enhancement-mode MOS transistor 24 that is connected to the resistor 26. In the present invention, the operating voltages of the first high-voltage N-type MOS transistor 21 and the second high-voltage N-type MOS transistor 25 both exceed 5V, while the operating voltage of the fully isolated low-voltage N-type enhancement-mode MOS transistor 24 is below 5V.

[0020] When the chip IO interface is exposed to positive voltage ESD energy, this negative voltage-resistant high-voltage ESD protection circuit directly discharges the ESD energy into the power path through the parasitic body diode 22 of the first high-voltage N-type MOS transistor 21. When the chip IO interface is exposed to negative voltage ESD energy, the ground terminal has a higher voltage than the chip IO interface. The ESD energy first flows upward through the body diode 27 of the second high-voltage N-type MOS transistor 25, and then breaks down the fully isolated low-voltage N-type enhancement-mode MOS transistor 24, forming a discharge path and releasing the negative ESD energy. Because the first and second high-voltage N-type MOS transistors 21 and 25 are in forward conduction during the ESD energy discharge process rather than in a breakdown process, the areas of the first and second high-voltage N-type MOS transistors 21 and 25 can be reduced. Although the fully isolated low-voltage N-type enhancement-mode MOS transistor 24 breaks down during the ESD energy discharge process, it is a low-voltage device and therefore can be relatively small in area. Therefore, the area of the high-voltage ESD protection circuit is small.

[0021] In a technical solution of the present invention, a resistor is connected in series between the gate and source of the first high-voltage N-type MOS transistor 21 to enhance the ESD capability of the first high-voltage N-type MOS transistor 21 .

[0022] In a technical solution of the present invention, a resistor is connected in series between the drain of the fully isolated low-voltage N-type enhancement mode MOS transistor 24 and the isolation well ISO to enhance the ESD capability of the fully isolated low-voltage N-type enhancement mode MOS transistor 24 .

[0023] In a technical solution of the present invention, a resistor is connected in series between the source and gate of the second high-voltage N-type MOS transistor 25 to enhance the ESD capability of the second high-voltage N-type MOS transistor 25 .

[0024] like Figure 3 This is a circuit structure diagram of another negative-voltage-resistant high-voltage ESD protection circuit provided by the present invention. In the high-voltage ESD protection circuit, the first high-voltage ESD device 11 is a first high-voltage diode 31, the anode of the first high-voltage diode 31 is connected to the chip IO interface, and the cathode of the first high-voltage diode 31 is connected to the power supply; the low-voltage ESD breakdown device 12 is composed of a fully isolated low-voltage N-type enhancement mode MOS transistor 24 and a resistor 26, the source of the fully isolated low-voltage N-type enhancement mode MOS transistor 24 is connected to the chip IO interface, the gate of the fully isolated low-voltage N-type enhancement mode MOS transistor 24 is connected to one end of the resistor 26, the other end of the resistor 26 is connected to the drain of the fully isolated low-voltage N-type enhancement mode MOS transistor 24, and the drain of the fully isolated low-voltage N-type enhancement mode MOS transistor 24 is also connected to the isolation well ISO; the second high-voltage ESD device 13 is a second high-voltage diode 32, the anode of the second high-voltage diode 32 is grounded, and the cathode of the second high-voltage diode 32 is connected to one end connected to the fully isolated low-voltage N-type enhancement mode MOS transistor 24 and the resistor 26. In the present invention, the operating voltages of the first high-voltage diode 31 and the second high-voltage diode 32 are both greater than 5V.

[0025] When the chip IO interface is in the state of positive voltage ESD energy, the high-voltage ESD protection circuit directly discharges the ESD energy into the power supply path through the first high-voltage diode 31. When the chip IO interface is in the state of negative voltage ESD energy, the ground terminal has a higher level than the chip IO interface. The ESD energy first passes through the second high-voltage diode 32 upward, and then breaks down the fully isolated low-voltage N-type enhancement MOS transistor 24, forming a discharge path to release the negative ESD energy.

[0026] The above are only preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, certain improvements and modifications that do not depart from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A negative pressure resistant high voltage ESD protection circuit, characterized in that: include: A first high-voltage ESD device (11), a low-voltage ESD breakdown device (12), and a second high-voltage ESD device (13), wherein the first high-voltage ESD device (11) is used to release positive ESD energy of a chip IO interface, the low-voltage ESD breakdown device (12) is used to release negative ESD energy of the chip IO interface, and the second high-voltage ESD device (13) is used to isolate the positive ESD energy of the chip IO interface and discharge the negative ESD energy of the chip IO interface.

2. A negative pressure resistant high voltage ESD protection circuit according to claim 1, characterized in that: The first high-voltage ESD device (11) is a first high-voltage N-type MOS transistor (21), the gate and source of the first high-voltage N-type MOS transistor (21) are short-circuited, the source of the first high-voltage N-type MOS transistor (21) is also connected to the chip IO interface, and the drain of the first high-voltage N-type MOS transistor (21) is connected to a power supply.

3. A negative pressure resistant high voltage ESD protection circuit according to claim 2, characterized in that: A resistor is connected in series between the gate and source of the first high-voltage N-type MOS transistor (21).

4. The negative pressure-resistant high-voltage ESD protection circuit according to claim 1, characterized in that: The first high-voltage ESD device (11) is a first high-voltage diode (31), the anode of the first high-voltage diode (31) is connected to the chip IO interface, and the cathode of the first high-voltage diode (31) is connected to the power supply.

5. A negative pressure-resistant high-voltage ESD protection circuit according to any one of claims 2 to 4, characterized in that: The low-voltage ESD breakdown device (12) is composed of a fully isolated low-voltage N-type enhancement MOS transistor (24) and a resistor (26); the source of the fully isolated low-voltage N-type enhancement MOS transistor (24) is connected to a chip IO interface; the gate of the fully isolated low-voltage N-type enhancement MOS transistor (24) is connected to one end of the resistor (26); the other end of the resistor (26) is connected to the drain of the fully isolated low-voltage N-type enhancement MOS transistor (24); and the drain of the fully isolated low-voltage N-type enhancement MOS transistor (24) is also connected to an isolation well ISO.

6. The negative pressure-resistant high-voltage ESD protection circuit according to claim 5, characterized in that: A resistor is connected in series between the drain of the fully isolated low-voltage N-type enhancement MOS transistor (24) and the isolation well ISO.

7. The negative pressure-resistant high-voltage ESD protection circuit according to claim 5, characterized in that: The second high-voltage ESD device (13) is a second high-voltage N-type MOS transistor (25), the source and gate of the second high-voltage N-type MOS transistor (25) are short-circuited, and the source of the second high-voltage N-type MOS transistor (25) is also grounded; the drain of the second high-voltage N-type MOS transistor (25) is connected to one end connected to the fully isolated low-voltage N-type enhancement MOS transistor (24) and the resistor (26).

8. The negative pressure-resistant high-voltage ESD protection circuit according to claim 7, characterized in that: A resistor is connected in series between the source and the gate of the second high-voltage N-type MOS transistor (25).

9. The negative pressure-resistant high-voltage ESD protection circuit according to claim 7, characterized in that: The second high-voltage ESD device (13) is a second high-voltage diode (32), the anode of the second high-voltage diode (32) is grounded, and the cathode of the second high-voltage diode (32) is connected to one end of a fully isolated low-voltage N-type enhancement mode MOS transistor (24) and a resistor (26).

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