Integrated circuit chip aging test device

Abstract

The utility model discloses an aging test device for an integrated circuit chip. The aging test device comprises a daughter board and a mother board, the daughter board is provided with a daughter board connecting piece and a peripheral application circuit used for being connected with the tested chip in a matched mode, and the peripheral application circuit is used for maintaining normal work of the tested chip. The mother board is provided with a power input end, an output voltage detection end and a plurality of stations, each station is provided with a daughter board mother port connector and a mother board circuit, the input end of the daughter board mother port connector is connected with the power input end through the mother board circuit, and the output end of the daughter board mother port connector is connected with the output voltage detection end. The daughter board connecting piece is connected with the daughter board mother port connector; the mother board circuit is respectively used for monitoring input voltage and input current and protecting a power supply circuit. On the premise of ensuring the test accuracy, the integrated circuit chip aging test device can be suitable for aging tests and performance tests after aging of various types of integrated circuit chips, so that the test cost is effectively saved, and the test period is shortened.

Description

Technical Field

[0001] The utility model belongs to the technical field of integrated circuit product aging, in particular to an integrated circuit chip aging test device. Background Art

[0002] Before mass production, integrated circuit chips generally undergo performance testing and burn-in testing. Performance testing is a mass production test of the chip's functionality and performance, while burn-in testing is used to ensure the chip's lifespan and reliability. Only integrated circuit chips that pass both tests are considered good quality. Traditional burn-in testing equipment typically consists of a burn-in printed circuit board (PCB) with at least 77 stations. Each station has a dedicated chip test socket. The chip under test is placed in the socket, and the pins of the chip under test are connected to the circuits on the burn-in PCB board, allowing multiple chips to undergo high-temperature and high-pressure burn-in experiments.

[0003] However, there are many types of chips, and their packaging forms and pin arrangements are different. Therefore, different types of burn-in printed circuit boards need to be customized for different types of chips under test. However, customizing burn-in printed circuit boards takes a long time, which extends the test cycle and reduces test efficiency. In addition, the cost of existing chip test sockets is high, which increases the cost of chip burn-in testing. Utility Model Content

[0004] The purpose of the utility model is to provide an integrated circuit chip aging test device, which can be applied to various types of integrated circuit chip aging tests and performance tests after aging while ensuring test accuracy, thereby effectively saving test costs and shortening test cycles.

[0005] To achieve the purpose of this utility model, the utility model provides the following technical solution: an integrated circuit chip aging test device, comprising:

[0006] A daughterboard, wherein the daughterboard is provided with a daughterboard connector and a peripheral application circuit for connecting to the chip under test, and the peripheral application circuit maintains the normal operation of the chip under test;

[0007] A motherboard, wherein the motherboard is provided with a power input terminal, an output voltage detection terminal, and a plurality of workstations, and the workstations are provided with a daughterboard female connector and a motherboard circuit; wherein the input terminal of the daughterboard female connector is connected to the power input terminal through the motherboard circuit, and the output terminal of the daughterboard female connector is connected to the output voltage detection terminal;

[0008] The daughterboard connector is connected to the daughterboard mother connector; the motherboard circuit is used to monitor the input voltage of the power input end and limit the input current of the power input end, while the daughterboard connector is used to connect the chip under test with the daughterboard mother connector.

[0009] On the basis of the above technical solution, the following subsidiary technical solutions are further included:

[0010] Preferably, the motherboard circuit includes a peripheral current limiting circuit, wherein the peripheral current limiting circuit is connected to the power input terminal and is also connected to the input terminal of the daughterboard female connector.

[0011] Preferably, the motherboard circuit also includes an input voltage indication circuit connected in parallel with the peripheral current limiting circuit, wherein the input voltage indication circuit is connected to the power input end and also connected to the input end of the daughterboard mother port connector.

[0012] Preferably, the input voltage indication circuit includes a lamp bead and a resistor, the peripheral application circuit includes a 0-ohm resistor and a capacitor, and the peripheral current limiting circuit includes a fuse.

[0013] Preferably, the daughter board is provided with a connector for connecting the peripheral application circuit and the chip under test.

[0014] Preferably, the connecting member is a 0 ohm resistor.

[0015] Preferably, the connecting part is a sub-daughter board, wherein the sub-daughter board is provided with a sub-daughter board connecting part, and the sub-daughter board is provided with a sub-daughter board female port connector, wherein the sub-daughter board female port connector is connected to the peripheral application circuit, and the sub-daughter board connecting part is used for connecting the chip under test and the sub-daughter board female port connector.

[0016] Preferably, the secondary daughter board connector is a pin header, and the secondary daughter board female connector is a retaining spring.

[0017] Preferably, the daughterboard connector includes a gold finger or a pin header, and the daughterboard female connector includes a gold finger slot or a retaining spring.

[0018] Preferably, the workstations are arranged in an array.

[0019] Compared with the prior art, the present invention has the following positive effects: the daughterboard connector facilitates the connection of the power signal and input and output signals of the chip under test with the daughterboard female connector. At the same time, the daughterboard connector and the daughterboard female connector facilitate the installation of the daughterboard and the motherboard. The peripheral application circuit is used to maintain the normal operation of the chip under test. The motherboard circuit is used to monitor the input voltage and limit the input current, thereby protecting the power supply line and the chip under test. The power input terminal facilitates the connection of the power supply, and the output voltage detection terminal facilitates the connection of the detection equipment.

[0020] The daughterboard connector facilitates connection to the motherboard. It also allows for interconnection with performance test equipment after being disconnected from peripheral application circuits, allowing for acquisition of chip performance parameters. This not only simplifies and accelerates the aging performance test process, but also avoids external influences that may occur during chip capture in existing technologies.

[0021] The chip under test is installed on the daughter board, and the daughter board is installed on the motherboard, which replaces the existing technology of replacing the entire aging test board. It is no longer necessary to customize the entire aging test board according to the chips under test in different packaging forms, which greatly reduces the testing cost, shortens the testing cycle, and improves the testing efficiency. It is suitable for aging test solutions for a variety of different packaged products. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 This is a schematic diagram of a motherboard in an embodiment of the present utility model;

[0024] Figure 2 This is a front view of the daughter board in the embodiment of the present utility model;

[0025] Figure 3 This is a cross-sectional view of a daughter board in an embodiment of the present utility model;

[0026] Figure 4 This is a schematic diagram of the assembly of the daughter board and the mother board in the embodiment of the present utility model;

[0027] Figure 5 This is a cross-sectional view of the secondary sub-board in the embodiment of the present utility model;

[0028] Figure 6 This is a circuit diagram of a peripheral current limiting circuit in an embodiment of the present utility model;

[0029] Figure 7This is a circuit diagram of the input voltage indicating circuit in an embodiment of the present utility model.

[0030] In the figure: 100, motherboard; 110, power input terminal; 120, output voltage detection terminal; 130, work station; 131, peripheral current limiting circuit; 132, input voltage indication circuit; 133, daughterboard female port connector; 200, daughterboard; 210, daughterboard connector; 220, peripheral application circuit; 221, 0 ohm resistor; 230, sub-daughterboard female port connector; 300, chip under test; 400, sub-daughterboard; 410, sub-daughterboard connector. DETAILED DESCRIPTION

[0031] In the description of the present invention, it should be noted that, unless otherwise specified, "plurality" means two or more; the terms "upper," "lower," "front," "back," "left," "right," "top," "bottom," "inner," "outer," "front end," "back end," "head," "tail," etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings and are intended only to facilitate the description of the present invention and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific direction, be constructed and operate in a specific direction, and therefore should not be construed as limiting the present invention. In addition, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0032] It should also be noted that, in the description of this utility model, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; and direct or indirect connections through an intermediary. Those skilled in the art will understand the specific meanings of these terms in this utility model depending on the specific circumstances.

[0033] The specific implementation of the present invention will be further described in detail below with reference to the accompanying drawings.

[0034] Example 1

[0035] like Figure 1-7 As shown, the present invention discloses a first embodiment of an integrated circuit chip burn-in test device, which is connected to a chip under test 300 and includes a motherboard 100 and a daughterboard 200 selectively electrically connected to the motherboard 100. The daughterboard 200 is provided with a daughterboard connector 210 in the form of a pin header and a peripheral application circuit 220 for matching with the chip under test 300. The peripheral application circuit 220 is used to maintain the normal operation of the chip under test 300.

[0036] The motherboard 100 is provided with a power input terminal 110, an output voltage detection terminal 120 and 78 workstations 130. The workstations 130 are arranged in a 6*13 array. Each workstation 130 is provided with a daughterboard female connector 133 and a motherboard circuit. The daughterboard female connector 133 is a spring clip. The input terminal of the daughterboard female connector 133 is connected to the power input terminal 110 through the motherboard circuit, and the output terminal of the daughterboard female connector 133 is connected to the output voltage detection terminal 120. The daughterboard connector 210 is plugged into the daughterboard female connector 133; the motherboard circuit is used to monitor the input voltage of the power input terminal 110 and limit the input current of the power input terminal 110 respectively. The pin header and spring clip facilitate the disassembly and assembly of the daughterboard 200 and the motherboard 100.

[0037] The daughter board 200 is provided with a connector for connecting the peripheral application circuit 220 and the chip under test 300; the connector is a sub-daughter board 400, and the chip under test 300 is arranged on the sub-daughter board 400. The sub-daughter board 400 is provided with a sub-daughter board connector 410, which is a pin header. The sub-daughter board connector 410 is connected to the chip under test 300 through the sub-daughter board 400; the daughter board 200 is provided with a sub-daughter board female connector 230, which is a retaining spring. The sub-daughter board female connector 230 is connected to the peripheral application circuit 220, and the sub-daughter board connector 410 is plugged into the sub-daughter board female connector 230.

[0038] Preferably, the motherboard circuit includes a peripheral current limiting circuit 131 and an input voltage indicating circuit 132. The input voltage indicating circuit 132 is connected in parallel with the peripheral current limiting circuit 131. The peripheral current limiting circuit 131 is respectively connected to the power input terminal 110 and the input terminal of the daughterboard mother connector 133. The input voltage indicating circuit 132 is respectively connected to the power input terminal 110 and the input terminal of the daughterboard mother connector 133. The input voltage indicating circuit 132 includes a lamp bead and a resistor, while the peripheral application circuit includes a 0 ohm resistor 221 and a capacitor. The peripheral current limiting circuit 131 includes a fuse. The input voltage indicating circuit 132 is used to monitor the input voltage of the power input terminal 110. The peripheral current limiting circuit 131 facilitates limiting the input current of the power input terminal 110. The power input terminal 110 facilitates access to the power supply. The output voltage detection terminal 120 facilitates access to the detection equipment.

[0039] Example 2

[0040] like Figures 1 to 7As shown, the present invention discloses a second embodiment of an integrated circuit chip burn-in test device, which is used to connect to a chip under test 300 and includes a motherboard 100 and a daughterboard 200 selectively electrically connected to the motherboard 100. The daughterboard 200 is provided with a daughterboard connector 210 and a peripheral application circuit 220 for matching with the chip under test 300. The daughterboard connector 210 comprises 20 gold fingers, with 10 gold fingers provided on each side of the daughterboard 200. The peripheral application circuit 220 is used to maintain the normal operation of the chip under test 300.

[0041] The motherboard 100 is provided with a power input terminal 110, an output voltage detection terminal 120 and 78 workstations 130. The workstations 130 are arranged in a 6*13 array. Each workstation 130 is provided with a daughterboard mother port connector 133 and a motherboard circuit. The daughterboard mother port connector 133 is a gold finger slot. The input terminal of the daughterboard mother port connector 133 is connected to the power input terminal 110 through the motherboard circuit, and the output terminal of the daughterboard mother port connector 133 is connected to the output voltage detection terminal 120. The daughterboard connector 210 is plugged into the daughterboard mother port connector 133; the motherboard circuit is used to monitor the input voltage of the power input terminal 110 and limit the input current of the power input terminal 110 respectively. The gold fingers and gold finger slots facilitate the disassembly and assembly of the daughterboard 200 and the motherboard 100.

[0042] The daughter board 200 is provided with a connector for connecting the peripheral application circuit 220 and the chip under test 300 ; the connector is preferably a 0-ohm resistor 221 , and the chip under test 300 is connected to the peripheral application circuit 220 via the 0-ohm resistor 221 .

[0043] Preferably, the motherboard circuit includes a peripheral current limiting circuit 131 and an input voltage indicating circuit 132. The input voltage indicating circuit 132 is connected in parallel with the peripheral current limiting circuit 131. The peripheral current limiting circuit 131 is respectively connected to the power input terminal 110 and the input terminal of the daughterboard mother connector 133, and the input voltage indicating circuit 132 is respectively connected to the power input terminal 110 and the input terminal of the daughterboard mother connector 133; the input voltage indicating circuit 132 includes a lamp bead and a resistor, while the peripheral application circuit includes a 0 ohm resistor 221 and a capacitor, and the peripheral current limiting circuit 131 includes a fuse; the input voltage indicating circuit 132 is used to monitor the input voltage of the power input terminal 110, the peripheral current limiting circuit 131 facilitates limiting the input current of the power input terminal 110, the power input terminal 110 facilitates the access of the power supply, and the output voltage detection terminal 120 facilitates the access of the detection equipment.

[0044] The working principle of the present invention is as follows: according to the tested chip 300 of different packaging forms and pin arrangements, the peripheral application circuit 220 matched therewith is integrated on the daughter board 200; a gold finger is set on one side of the daughter board 200, 10 gold fingers are set on the front side of the daughter board, and 10 gold fingers are set on the back side, and the power signal, input and output signal of the tested chip 300 are connected to the gold fingers accordingly; 78 workstations 130 are arranged in a 6*13 array on the designed motherboard 100, and each workstation 130 is provided with a peripheral current limiting circuit 131, an input voltage indication circuit 132 and a daughter board mother port connector 133; a 0 ohm resistor 221 and a capacitor are welded to the peripheral application circuit 220, and a lamp bead and a resistor are welded to the input voltage On the indication circuit 132, the fuse is welded to the peripheral current limiting circuit 131; the chip under test 300 is welded to the daughter board 200, the daughter board 200 is connected to the performance test machine, and the data parameters of the chip under test 300 before aging are recorded; the chip under test 300 is connected to the peripheral application circuit 220 through the 0 ohm resistor 221, and then the daughter board 200 is connected to the motherboard 100 through the gold finger and the gold finger slot to ensure that all 78 daughter boards 200 are connected normally; the output voltage detection terminal 120 is connected to the monitoring circuit, the power supply is connected to the power input terminal 110, and the output detection point can detect the output voltage normally. After confirmation, the daughter board 200 and the motherboard 100 are placed in the aging box for high temperature and high humidity dynamic aging test.

[0045] After the aging test is completed, the daughter board 200 is removed from the motherboard 100, and the 0 ohm resistor 221 connected to the peripheral application circuit 220 is removed using a high-temperature soldering iron; the aged chip under test 300 is connected to a performance testing instrument for performance testing; by comparing the performance test data before and after aging, the failure rate and life of the chip under test 300 are estimated.

[0046] After adopting the above technical solution, the utility model has the following benefits: the chip under test is installed on the daughter board, and the daughter board is installed on the motherboard, which replaces the replacement of the entire aging test board in the existing technology. It is no longer necessary to customize the entire aging test board according to the chips under test in different packaging forms, which greatly reduces the testing cost, shortens the testing cycle, and improves the testing efficiency. It is suitable for aging test solutions for a variety of different packaged products.

[0047] The above are only preferred implementations of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with this technical field can make several modifications and improvements without departing from the creative concept of the present invention, which should be included in the protection scope of the present invention.

Claims

1. An integrated circuit chip aging test device, characterized in that It includes: A daughterboard, wherein the daughterboard is provided with a daughterboard connector and a peripheral application circuit for connecting to the chip under test, and the peripheral application circuit maintains the normal operation of the chip under test; A motherboard, wherein the motherboard is provided with a power input terminal, an output voltage detection terminal, and a plurality of workstations, and the workstations are provided with a daughterboard female connector and a motherboard circuit; wherein the input terminal of the daughterboard female connector is connected to the power input terminal through the motherboard circuit, and the output terminal of the daughterboard female connector is connected to the output voltage detection terminal; The daughterboard connector is connected to the daughterboard mother connector; the motherboard circuit is used to monitor the input voltage of the power input end and limit the input current of the power input end, while the daughterboard connector is used to connect the chip under test with the daughterboard mother connector.

2. The integrated circuit chip aging test device according to claim 1, characterized in that: The motherboard circuit includes a peripheral current limiting circuit, wherein the peripheral current limiting circuit is connected to the power input terminal and is also connected to the input terminal of the daughterboard female port connector.

3. The integrated circuit chip aging test device according to claim 2, characterized in that: The motherboard circuit also includes an input voltage indicating circuit connected in parallel with the peripheral current limiting circuit, wherein the input voltage indicating circuit is connected to the power input terminal and also connected to the input terminal of the daughterboard mother port connector.

4. The integrated circuit chip aging test device according to claim 3, wherein: The input voltage indication circuit includes a lamp bead and a resistor, the peripheral application circuit includes a 0-ohm resistor and a capacitor, and the peripheral current limiting circuit includes a fuse.

5. The integrated circuit chip aging test device according to claim 1, wherein: The daughter board is provided with a connector for connecting the peripheral application circuit and the chip under test.

6. The integrated circuit chip aging test device according to claim 5, characterized in that: The connecting piece is a 0 ohm resistor.

7. The integrated circuit chip aging test device according to claim 5, characterized in that: The connecting part is a sub-daughter board, wherein the sub-daughter board is provided with a sub-daughter board connecting part, and the sub-daughter board is provided with a sub-daughter board female port connector, wherein the sub-daughter board female port connector is connected to the peripheral application circuit, and the sub-daughter board connecting part is used to connect the chip under test and the sub-daughter board female port connector.

8. The integrated circuit chip aging test device according to claim 7, characterized in that: The secondary daughter board connecting piece is a pin header, and the secondary daughter board female connector is a clip.

9. The integrated circuit chip aging test device according to claim 1, wherein: The daughter board connector includes a gold finger or a pin header, and the daughter board female connector includes a gold finger slot or a clip.

10. The integrated circuit chip aging test device according to claim 1, wherein: The workstations are arranged in an array.

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