Power-on control circuit

Abstract

The utility model discloses a power-on control circuit, which comprises a controller, a grid voltage control circuit, a control circuit and a drain voltage switch circuit, the controller is in communication connection with the gate voltage control circuit and is used for controlling the magnitude of the output voltage of the gate voltage control circuit; the grid voltage control circuit is used for controlling the grid voltage of the GaN power amplifier; the control circuit is used for determining that the grid voltage reaches the turn-off voltage under the condition that the enable signal is effective and the output voltage of the second output end of the grid voltage control circuit is greater than the reference voltage, so as to control the conduction of the drain voltage switching circuit; the input end of the drain voltage switch circuit is connected with the output end of the control circuit, and the output end of the drain voltage switch circuit is connected with the drain electrode of the GaN power amplifier and used for providing positive voltage for the drain electrode of the GaN power amplifier when the drain voltage switch circuit is switched on. According to the utility model, the power-on sequence of the grid electrode and the drain electrode of the GaN power amplifier can be accurately controlled, abnormal voltage and current are prevented from being generated, the complexity and the cost of a peripheral circuit are reduced, and the stability and the reliability of the whole circuit are improved.

Description

Technical Field

[0001] The utility model relates to the technical field of communications, and in particular to a power-on control circuit. Background Art

[0002] With the rapid development of communication technology, communication frequency bands have expanded from traditional 3G to 5G and even the future 6G, and the performance requirements for power amplifiers have become increasingly stringent. Traditional laterally diffused metal oxide semiconductor (LDMOS) power amplifiers can no longer meet the high-frequency and wide-bandwidth requirements. Therefore, power amplifiers based on gallium nitride (GaN) materials have emerged.

[0003] Despite their numerous advantages, GaN amplifiers have stringent power-up sequencing requirements. GaN amplifiers are depletion-mode devices, fully conducting at zero gate voltage. Negative gate voltage is required to operate at the proper bias current; otherwise, excessive current will directly damage the device. Therefore, the gate and drain power-up sequence must be strictly controlled to ensure proper operation and prevent irreversible damage. Utility Model Content

[0004] The utility model provides a power-on control circuit that can accurately control the power-on sequence of the gate and drain of a GaN power amplifier, preventing the generation of abnormal voltage and current, while reducing the complexity and cost of peripheral circuits and improving the stability and reliability of the overall circuit.

[0005] An embodiment of the utility model provides a power-on control circuit for controlling the power-on of a GaN power amplifier. The power-on control circuit includes: a controller, a gate voltage control circuit, a control circuit, and a leakage voltage switch circuit. The controller is communicatively connected to the gate voltage control circuit and is used to control the magnitude of the output voltage of the gate voltage control circuit. A first output end of the gate voltage control circuit is connected to the gate of the GaN power amplifier, and a second output end of the gate voltage control circuit is connected to a first input end of the control circuit and is used to control the gate voltage of the GaN power amplifier. A second input end of the control circuit is connected to a reference voltage, and a third input end of the control circuit is connected to an enable signal, for determining that the gate voltage reaches a turn-off voltage when the enable signal is valid and the output voltage of the second output end of the gate voltage control circuit is greater than the reference voltage, thereby controlling the leakage voltage switch circuit to be turned on. The input end of the leakage voltage switch circuit is connected to the output end of the control circuit, and the output end of the leakage voltage switch circuit is connected to the drain of the GaN power amplifier, for providing a positive voltage to the drain of the GaN power amplifier when turned on.

[0006] Optionally, the gate voltage control circuit includes a digital-to-analog converter and an inverting regulator; the output end of the digital-to-analog converter is connected to the input end of the inverting regulator, for converting the input digital signal into an analog voltage signal of corresponding proportion and outputting it; the output end of the inverting regulator is connected to the gate of the GaN power amplifier, for inverting the analog voltage signal and outputting it to the GaN power amplifier to provide a negative bias voltage for the gate of the GaN power amplifier.

[0007] Optionally, the digital-to-analog converter includes a digital-to-analog conversion chip, a first resistor, a second resistor, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor; the first resistor is connected between the clock line pin of the digital-to-analog conversion chip and the controller; the second resistor is connected between the data line pin of the digital-to-analog conversion chip and the controller; the first capacitor is connected between the output pin and the ground terminal of the digital-to-analog conversion chip, the second capacitor is connected between the reference voltage input pin and the ground terminal of the digital-to-analog conversion chip, the third capacitor is connected between the power pin and the ground terminal of the digital-to-analog conversion chip, and the fourth capacitor is connected between the logic power pin and the ground terminal of the digital-to-analog conversion chip; the power pin of the digital-to-analog conversion chip is connected to the first voltage, the logic power pin of the digital-to-analog conversion chip is connected to the second voltage, and the output pin of the digital-to-analog conversion chip serves as the output end of the digital-to-analog converter.

[0008] Optionally, the inverting regulator includes a voltage conversion chip, a fifth capacitor, a sixth capacitor and a seventh capacitor; the fifth capacitor is connected between the negative capacitor pin and the positive capacitor pin of the voltage conversion chip, the sixth capacitor is connected between the shutdown control pin and the ground terminal of the voltage conversion chip, and the seventh capacitor is connected between the negative voltage output pin and the ground terminal of the voltage conversion chip; the positive power input pin of the voltage conversion chip serves as the input terminal of the inverting regulator, the shutdown control pin of the voltage conversion chip is connected to the positive power input pin of the voltage conversion chip, and the negative voltage output pin of the voltage conversion chip serves as the output terminal of the inverting regulator.

[0009] Optionally, the control circuit includes a comparison module and a logic gate circuit; the first input terminal of the comparison module serves as the first input terminal of the control circuit, the second input terminal of the comparison module serves as the second input terminal of the control circuit, the output terminal of the comparison module is connected to the first input terminal of the logic gate circuit, the comparison module is used to output a first level signal when the output voltage of the second output terminal of the gate voltage control circuit is greater than the reference voltage, and to output a second level signal when the output voltage of the second output terminal of the gate voltage control circuit is less than the reference voltage, wherein the first level signal and the second level signal are signals with opposite high and low levels to each other; the second input terminal of the logic gate circuit serves as the third input terminal of the control circuit, and the output terminal of the logic gate circuit serves as the output terminal of the control circuit, and is used to control the leakage switch circuit to be turned on when the enable signal is valid and the comparison module outputs the first level signal, so as to provide a positive voltage to the drain of the GaN power amplifier.

[0010] Optionally, the comparison module includes a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth capacitor, a ninth capacitor and a comparator; the output end of the comparator serves as the output end of the comparison module; the first end of the third resistor serves as the first input end of the comparison module, and the second end of the third resistor is connected to the non-inverting input end of the comparator; the first end of the fourth resistor is connected to the second end of the third resistor, and the second end of the fourth resistor is grounded; the first end of the fifth resistor is connected to the third voltage, the second end of the fifth resistor is connected to the inverting input end of the comparator, and serves as the second input end of the comparison module; the first end of the sixth resistor is connected to the second end of the fifth resistor, and the second end of the sixth resistor is grounded; the first end of the seventh resistor is connected to the output end of the comparator, and the second end of the seventh resistor is connected to the positive power supply input end of the comparator; the first end of the eighth capacitor is connected to the second end of the third resistor, and the second end of the eighth capacitor is grounded; the first end of the ninth capacitor is connected to the third voltage, and the second end of the ninth capacitor is grounded.

[0011] Optionally, the logic gate circuit includes an AND gate, an eighth resistor, a ninth resistor and a tenth capacitor; the first input terminal of the AND gate serves as the first input terminal of the logic gate circuit, the second input terminal of the AND gate serves as the second input terminal of the logic gate circuit, the output terminal of the AND gate is connected to the first terminal of the ninth resistor, and the second terminal of the ninth resistor serves as the output terminal of the logic gate circuit; the eighth resistor is connected between the second input terminal of the AND gate and the ground terminal, the tenth capacitor is connected between the power supply terminal of the AND gate and the ground terminal, and the power supply terminal of the AND gate is connected to the third voltage.

[0012] Optionally, the leakage switch circuit includes a first transistor, a second transistor, a ninth resistor, a tenth resistor, an eleventh resistor and a twelfth resistor; the first end of the tenth resistor is connected to the gate of the first transistor, and the second end of the tenth resistor is grounded; the gate of the first transistor serves as the input end of the leakage switch circuit, the first electrode of the first transistor is grounded, and the second electrode of the first transistor is connected to the first end of the eleventh resistor; the second end of the eleventh resistor is respectively connected to the first end of the twelfth resistor and the gate of the second transistor, the second end of the twelfth resistor is connected to the first electrode of the second transistor and is connected to the fourth voltage, and the second electrode of the second transistor serves as the output end of the leakage switch circuit.

[0013] Optionally, the power-on control circuit also includes a power amplifier drain protection circuit, wherein the control end of the power amplifier drain protection circuit is connected to the output end of the control circuit, the first end of the power amplifier drain protection circuit is connected to the drain of the GaN power amplifier, and the second end of the power amplifier drain protection circuit is grounded, and is used to discharge the drain current of the GaN power amplifier when the enable signal is invalid.

[0014] Optionally, the power amplifier drain protection circuit includes a third transistor, a fourth transistor, a thirteenth resistor, a fourteenth resistor and a fifteenth resistor; the gate of the third transistor serves as the control end of the power amplifier drain protection circuit, the first electrode of the third transistor is grounded, and the second electrode of the third transistor is connected to the first end of the thirteenth resistor; the second end of the thirteenth resistor is connected to the first voltage, the first end of the fourteenth resistor is connected to the gate of the fourth transistor, and the second end of the fourteenth resistor is grounded; the first electrode of the fourth transistor is grounded, the second electrode of the fourth transistor is connected to the first end of the fifteenth resistor, and the second end of the fifteenth resistor serves as the first end of the power amplifier drain protection circuit.

[0015] The power-on control circuit provided by the embodiment of the present invention includes a controller, a gate voltage control circuit, a control circuit, and a leakage voltage switch circuit. The gate voltage of the GaN power amplifier can be controlled by the gate voltage control circuit. The control circuit compares the reference voltage with the second output voltage to determine whether the gate voltage has reached the cut-off voltage, thereby controlling the conduction state of the leakage voltage switch circuit. When the second output voltage rises to a value greater than the reference voltage, it is determined that the gate voltage has reached the cut-off voltage, and then the control circuit gradually turns on the leakage voltage switch circuit. In other words, the control circuit is configured to control the leakage voltage switch circuit based on the provision of the cut-off voltage so that the drain of the GaN power amplifier is turned on after the gate voltage reaches the cut-off voltage. In other words, the power-on control circuit provided by the embodiment of the present invention can accurately control the power-on sequence of the gate and drain of the GaN power amplifier to prevent the generation of abnormal voltage and current. In addition, the complexity and cost of the peripheral circuit are low, and the stability and reliability of the overall circuit are high.

[0016] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 This is a power-on control circuit provided by an embodiment of the utility model;

[0019] Figure 2 This is another power-on control circuit provided by an embodiment of the utility model;

[0020] Figure 3This is another power-on control circuit provided by an embodiment of the utility model;

[0021] Figure 4 This is another power-on control circuit provided by an embodiment of the utility model;

[0022] Figure 5 This is another power-on control circuit provided by an embodiment of the utility model;

[0023] Figure 6 This is another power-on control circuit provided by an embodiment of the utility model;

[0024] Figure 7 This is another power-on control circuit provided by an embodiment of the utility model;

[0025] Figure 8 This is another power-on control circuit provided by an embodiment of the utility model;

[0026] Figure 9 This is a schematic structural diagram of a GaN power amplifier provided by an embodiment of the present utility model;

[0027] Figure 10 This is another power-on control circuit provided by an embodiment of the utility model;

[0028] Figure 11 This is a flow chart of a control method for a power-on control circuit provided by an embodiment of the present utility model. DETAILED DESCRIPTION

[0029] In order to help those skilled in the art better understand the present invention, the following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0030] It should be noted that the terms "first," "second," and the like in the specification and claims of the present invention and the accompanying drawings are used to distinguish similar items and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments of the present invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions.

[0031] Figure 1 This is a power-on control circuit provided by an embodiment of the present utility model. Figure 1As shown, the power-on control circuit is used to control the power-on of the GaN power amplifier 20 . The power-on control circuit 1 includes: a controller 11 , a gate voltage control circuit 12 , a control circuit 13 and a leakage voltage switch circuit 14 .

[0032] The controller 11 is in communication with the gate voltage control circuit 12 and is used to control the magnitude of the output voltage of the gate voltage control circuit 12 .

[0033] A first output terminal of the gate voltage control circuit 12 is connected to the gate of the GaN power amplifier 20 , and a second output terminal of the gate voltage control circuit 12 is connected to a first input terminal of the control circuit 13 for controlling the gate voltage of the GaN power amplifier 20 .

[0034] The second input terminal of the control circuit 13 is connected to the reference voltage Vref, and the third input terminal of the control circuit 13 is connected to the enable signal PE, which is used to determine that the gate voltage reaches the turn-off voltage when the enable signal PE is valid and the output voltage of the second output terminal of the gate voltage control circuit 12 is greater than the reference voltage Vref, thereby controlling the leakage switch circuit 14 to be turned on.

[0035] The input end of the leakage switch circuit 14 is connected to the output end of the control circuit 13 , and the output end of the leakage switch circuit 14 is connected to the drain of the GaN power amplifier 20 , for providing a positive voltage to the drain of the GaN power amplifier 20 when turned on.

[0036] Specifically, the controller 11 may include a microcontroller. Optionally, the controller 11 may include a single chip microcomputer, a digital signal processor (DSP) or an ARM (Advanced RICS processor). Optionally, the controller 11 is further configured to output an enable signal PE.

[0037] The gate voltage control circuit 12 can be a circuit module used to control the gate voltage of the GaN power amplifier 20. It primarily performs the following key functions: first, it receives commands from the controller and adjusts its output voltage accordingly to control the operating state of the GaN power amplifier 20; second, it transmits the output signal to the control circuit 13, providing a basis for subsequent control of the leakage switch circuit 14. Furthermore, the output voltage at the first output terminal of the gate voltage control circuit 12 is defined as the first output voltage, and the output voltage at the second output terminal of the gate voltage control circuit 12 is defined as the second output voltage. The first output voltage and the second output voltage are voltages of opposite high and low levels.

[0038] Those skilled in the art will appreciate that various technical means exist to implement the above-mentioned control function of the control circuit 13. In some embodiments, the control circuit 13 can be further configured to, when the enable signal PE is valid, output a first level signal when the output voltage of the second output terminal of the gate voltage control circuit 12 is greater than the reference voltage Vref to control the leakage switch circuit 14 to be turned on, and output a second level signal when the output voltage of the second output terminal of the gate voltage control circuit 12 is less than the reference voltage Vref to control the leakage switch circuit 14 to be turned off. The control circuit 13 can include at least one of the following: a resistor divider circuit, a comparator circuit, and a Zener diode circuit. When the control circuit 13 includes a comparator circuit, the reference voltage Vref can be adjusted by programming code.

[0039] In some embodiments, during the power-up phase of the GaN power amplifier 20, the control circuit 13 compares the reference voltage Vref with the second output voltage to determine whether the gate voltage has reached the cutoff voltage, thereby controlling the conduction state of the leakage switch circuit 14. Furthermore, when the second output voltage rises above the reference voltage Vref, the gate voltage is determined to have reached the cutoff voltage, and the control circuit 13 gradually turns on the leakage switch circuit 14. This prevents large inrush currents. Inrush current refers to the instantaneous high current that may be generated at power-up due to the charging and discharging of components such as capacitors and inductors in the circuit. If not controlled, inrush current may damage components in the circuit and affect the stability and reliability of the system. By gradually turning on the leakage switch circuit 14, the current can be slowly increased, giving the components in the circuit sufficient time to adapt to the current change, thereby effectively preventing the generation of inrush currents. The cutoff voltage refers to the voltage value in the GaN power amplifier 20 that causes the device to transition from the on state to the off state. The specific value of the cutoff voltage varies depending on the GaN power transistor model and application scenario. For example, the cut-off voltage may be a negative voltage value.

[0040] When the second output voltage is less than the reference voltage Vref, it is determined that the gate voltage has not reached the turn-off voltage, and the control circuit 13 does not control the leakage switch circuit 14 to be turned on.

[0041] The leakage voltage switch circuit 14 includes a switch that is controlled on and off by an electrical signal, or a switch that is controlled on and off according to the characteristics of the component itself. The switch in the leakage voltage switch circuit 14 can be a unidirectional switch, such as a unidirectional switch composed of a bidirectional switch and a diode in series, or a bidirectional switch, such as a metal oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT) with an anti-parallel freewheeling diode.

[0042] Optionally, the leakage switch circuit 14 is configured to determine whether to provide a positive voltage to the drain of the GaN power amplifier 20 based on the provision of a shutdown voltage. When the gate voltage reaches the shutdown voltage, that is, when the second output voltage is greater than the reference voltage Vref, the leakage switch circuit 14 turns on, and the drain of the GaN power amplifier 20 receives a positive voltage, and begins operation. When the gate voltage does not reach the shutdown voltage, that is, when the second output voltage is less than the reference voltage Vref, the leakage switch circuit 14 turns off, cutting off the positive voltage to the drain, and the GaN power amplifier 20 stops operating.

[0043] Continue to refer Figure 1 The working principle of the power-on control circuit 1 provided in the embodiment of the present utility model is as follows:

[0044] After the system is powered on, the controller 11 begins operation. Based on the system's initial state and the preset power-on strategy, it issues control instructions to the gate voltage control circuit 12, adjusts the output voltage of the gate voltage control circuit 12, and issues an enable signal PE to the control circuit 13. Based on the instructions from the controller 11, the gate voltage control circuit 12 outputs a first output voltage to the gate of the GaN power amplifier 20 and simultaneously outputs a second output voltage to the control circuit 13.

[0045] The control circuit 13 compares the second output voltage with the reference voltage Vref. When the second output voltage rises above the reference voltage Vref, the leakage switch circuit 14 is turned on. The gate voltage is determined to have reached the cutoff voltage, and the control circuit 13 then controls the leakage switch circuit 14 to conduct. The drain of the GaN power amplifier 20 receives a positive voltage. The gate voltage is then slowly adjusted until the drain current reaches the target quiescent current value, and the RF signal is finally input. To protect the GaN power amplifier 20 from damage, the gate voltage adjustment of the GaN power amplifier 20 is stopped when the drain current of the GaN power amplifier 20 is approximately twice the target quiescent current value. When the second output voltage of the gate voltage control circuit 12 is less than the reference voltage Vref, the leakage switch circuit 14 remains off, the positive voltage on the drain of the GaN power amplifier 20 is cut off, and the GaN power amplifier 20 ceases operation. In other words, the control circuit 13 is configured to control the leakage switch circuit 14 based on the provision of the cutoff voltage, so that the drain of the GaN power amplifier 20 is turned on after the gate voltage reaches the cutoff voltage. In this way, the GaN power amplifier 20 is protected from being damaged during power-up.

[0046] In some embodiments, the maximum efficiency quiescent current I DQ The corresponding gate voltage VG = -2.73 V. That is, when the gate voltage is -2.73 V, the quiescent current in the power-on control circuit 1 is I DQ , and at this time the power-on control circuit 1 is in the state of maximum efficiency. This means that when designing and using the power-on control circuit 1, the gate voltage can be set to -2.73V to enable the power-on control circuit 1 to operate at a maximum efficiency of I under quiescent current. DQ Working at the maximum efficiency point can optimize circuit performance, reduce power consumption and improve energy efficiency in practical applications.

[0047] The power-on control circuit provided by the embodiment of the present invention includes a controller, a gate voltage control circuit, a control circuit and a leakage voltage switch circuit. The gate voltage of the GaN power amplifier can be controlled by the gate voltage control circuit. The control circuit compares the reference voltage with the second output voltage to determine whether the gate voltage has reached the cut-off voltage, thereby controlling the conduction state of the leakage voltage switch circuit. When the second output voltage rises to be greater than the reference voltage, it is determined that the gate voltage has reached the cut-off voltage, and then the control circuit gradually turns on the leakage voltage switch circuit. In other words, the control circuit is configured to control the leakage voltage switch circuit based on the provision of the cut-off voltage so that the drain of the GaN power amplifier 20 is turned on after the gate voltage reaches the cut-off voltage. In other words, the power-on control circuit provided by the embodiment of the present invention can accurately control the power-on sequence of the gate and drain of the GaN power amplifier to prevent the generation of abnormal voltage and current. In addition, the complexity and cost of the peripheral circuit are low, and the stability and reliability of the overall circuit are high.

[0048] Figure 2This is a structural diagram of another power-on control circuit provided by an embodiment of the present utility model. Figure 2 As shown, optionally, the gate voltage control circuit 12 includes a digital-to-analog converter 121 and an inverting regulator 122 .

[0049] The output end of the digital-to-analog converter 121 is connected to the input end of the inverting regulator 122 , and is used to convert the input digital signal into an analog voltage signal of corresponding proportion and output it.

[0050] The output terminal of the inverting regulator 122 is connected to the gate of the GaN power amplifier 20 for inverting and outputting the analog voltage signal to the GaN power amplifier 20 to provide a negative bias voltage for the gate of the GaN power amplifier 20 .

[0051] Specifically, the digital-to-analog converter 121 (DAC) is an electronic device that converts digital signals into analog voltage signals. The DAC 121 can adjust the dynamic range of the output analog signal. The dynamic range refers to the ratio of the maximum amplitude to the minimum amplitude of the signal. By adjusting the parameters such as the reference voltage or gain of the DAC, the dynamic range of the output analog signal can be changed to meet different application requirements. Optionally, the controller 11 can adjust the dynamic range of the output analog signal through I 2 The C signal controls the output voltage of the digital-to-analog converter 121 , thereby adjusting the gate voltage to meet the quiescent current requirement.

[0052] The inverting regulator 122 is a power conversion device that can convert an input DC voltage into a DC output voltage with opposite polarity. It is used to convert a positive voltage input into a negative voltage output to provide a stable power supply for the gate of the GaN power amplifier 20.

[0053] As a preferred implementation provided by the embodiment of the present utility model, Figure 3 This is a structural diagram of another power-on control circuit provided by an embodiment of the present utility model. Figure 3 As shown, optionally, the digital-to-analog converter 121 includes a digital-to-analog conversion chip U1, a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4.

[0054] The first resistor R1 is connected between the clock line pin SCL of the digital-to-analog conversion chip U1 and the controller 11 ; the second resistor R2 is connected between the data line pin SDA of the digital-to-analog conversion chip U1 and the controller 11 .

[0055] The first capacitor C1 is connected between the output pin VOUT of the digital-to-analog conversion chip U1 and the ground terminal, the second capacitor C2 is connected between the reference voltage input pin VREF of the digital-to-analog conversion chip U1 and the ground terminal, the third capacitor C3 is connected between the power pin VDD of the digital-to-analog conversion chip U1 and the ground terminal, and the fourth capacitor C4 is connected between the logic power pin VLOGIC of the digital-to-analog conversion chip U1 and the ground terminal.

[0056] The power pin VDD of the DAC chip U1 is connected to the first voltage VCC1 , the logic power pin VLOGIC of the DAC chip U1 is connected to the second voltage VCC2 , and the output pin VOUT of the DAC chip U1 serves as the output end of the DAC 121 .

[0057] Specifically, the first resistor R1 is used to adjust the transmission characteristics of the clock signal, such as current limiting or impedance matching, etc. The clock line is used to transmit the clock signal between the controller 11 and the digital-to-analog conversion chip U1 to synchronize data transmission and operation.

[0058] The second resistor R2 is used to adjust the transmission characteristics of the data line. The data line is used to transmit data signals, such as the value of a digital signal, between the controller 11 and the digital-to-analog conversion chip U1.

[0059] The first capacitor C1 is a filter capacitor, used to stabilize the analog voltage signal output by the DAC chip U1 and reduce noise and interference. The second capacitor C2 is a voltage-stabilizing capacitor. The third capacitor C3 is used for power supply filtering, providing a stable power supply for the DAC chip U1 and reducing the impact of power supply noise on the operation of the DAC chip U1. The fourth capacitor C4 is used for logic power supply filtering to ensure the stable operation of the logic circuit within the DAC chip U1.

[0060] Optionally, the digital-to-analog conversion chip U1 may further include a ground pin GND, an address selection pin A0, and a power saving mode control pin EP1. Optionally, the ground pin GND, the address selection pin A0, and the power saving mode control pin EP1 are all grounded.

[0061] Optionally, continue to refer to Figure 3 The inverting regulator 122 includes a voltage conversion chip U2, a fifth capacitor C5, a sixth capacitor C6 and a seventh capacitor C7.

[0062] The fifth capacitor C5 is connected between the capacitor negative pin CAP- and the capacitor positive pin CAP+ of the voltage conversion chip U2, the sixth capacitor C6 is connected between the shutdown control pin / SD of the voltage conversion chip U2 and the ground terminal, and the seventh capacitor C7 is connected between the negative voltage output pin OUT of the voltage conversion chip U2 and the ground terminal.

[0063] The positive power input pin V+ of the voltage conversion chip U2 serves as the input end of the inverting regulator 122, the shutdown control pin / SD of the voltage conversion chip U2 is connected to the positive power input pin V+ of the voltage conversion chip U2, and the negative voltage output pin OUT of the voltage conversion chip U2 serves as the output end of the inverting regulator 122.

[0064] Specifically, the fifth capacitor C5 is used to store and stabilize energy during the voltage conversion process, helping the voltage conversion chip U2 achieve stable voltage conversion. The sixth capacitor C6 filters or stabilizes the shutdown control signal to ensure the reliability of the shutdown control. The seventh capacitor C7 is used to filter the output negative voltage, reducing the ripple and noise of the output negative voltage, making the output more stable. Optionally, the ground pin GND1 of the voltage conversion chip U2 is grounded.

[0065] In some embodiments, the controller 11 can adjust the output voltage of the digital-to-analog conversion chip U1 so that the GaN power amplifier 20 operates at the optimal static operating point. Specifically, the output of the digital-to-analog conversion chip U1 is divided into two paths. One path is output to the inverting regulator 122, and the other path is output to the control circuit 13; the inverting regulator 122 receives the output of the digital-to-analog conversion chip U1 as input, and converts its positive voltage into a negative voltage, and provides it to the gate of the GaN power amplifier 20. The controller 11 can read the output current of the digital-to-analog conversion chip U1. Since the output of the digital-to-analog conversion chip U1 is connected to the inverting regulator 122, and the output of the inverting regulator 122 is connected to the gate of the GaN power amplifier 20, the output current of the digital-to-analog conversion chip U1 is actually the gate current of the GaN power amplifier 20. The controller 11 uses I 2 C signal communicates with the digital-to-analog conversion chip U1. By adjusting the output voltage of the digital-to-analog conversion chip U1, the controller 11 can control its output current so that the output current of the digital-to-analog conversion chip U1 is equal to the drain current when the GaN power amplifier 20 operates at the optimal static operating point. This ensures that the GaN power amplifier 20 operates at the optimal static operating point to achieve optimal performance and efficiency. In other words, the controller 11 can determine the gate current of the GaN power amplifier 20 by reading the output current of the digital-to-analog conversion chip U1, and compare the actual output gate current (ie, the current current) with the set drain current (ie, the target current) when the GaN power amplifier 20 operates at the optimal static operating point. If the current current is different from the target current, the controller will check the output current of the GaN power amplifier 20 through I 2The C signal can adjust the output voltage of the digital-to-analog converter chip U1, thereby allowing the GaN power amplifier 20 to operate at the optimal static operating point. For example, if the current current is less than the target current, the controller 11 can gradually increase the output voltage of the digital-to-analog converter chip U1 to increase the gate voltage, thereby increasing the drain current. If the current current is greater than the target current, the controller 11 can gradually decrease the output voltage of the digital-to-analog converter chip U1 to reduce the gate voltage, thereby reducing the drain current.

[0066] Figure 4 This is a structural diagram of another power-on control circuit provided by an embodiment of the present utility model. Figure 4 As shown, the control circuit 13 includes a comparison module 131 and a logic gate circuit 132 .

[0067] The first input terminal of the comparison module 131 serves as the first input terminal of the control circuit 13, the second input terminal of the comparison module 131 serves as the second input terminal of the control circuit 13, and the output terminal of the comparison module 131 is connected to the first input terminal of the logic gate circuit 132. The comparison module 131 is configured to output a first level signal when the output voltage of the second output terminal of the gate voltage control circuit 12 is greater than the reference voltage Vref, and to output a second level signal when the output voltage of the second output terminal of the gate voltage control circuit 12 is less than the reference voltage Vref, wherein the first level signal and the second level signal are signals of opposite high and low levels.

[0068] The second input terminal of the logic gate circuit 132 serves as the third input terminal of the control circuit 13, and the output terminal of the logic gate circuit 132 serves as the output terminal of the control circuit 13, which is used to control the leakage switch circuit 14 to be turned on when the enable signal PE is valid and the comparison module 131 outputs a first level signal, so as to provide a positive voltage to the drain of the GaN power amplifier 20.

[0069] Exemplarily, the first level signal is a high level, and the second level signal is a low level. When the enable signal PE is valid (e.g., high level valid) and the comparison module 131 outputs the first level signal, the logic gate circuit 132 outputs a high level signal, controlling the leakage switch circuit 14 to turn on. After the leakage switch circuit 14 is turned on, it provides a positive voltage to the drain of the GaN power amplifier 20, enabling the GaN power amplifier 20 to operate normally. If the enable signal PE is invalid, the comparison module 131 outputs the first level signal, the logic gate circuit 132 outputs a low level signal, and the leakage switch circuit 14 remains in the off state, the positive voltage to the drain of the GaN power amplifier 20 is cut off, and the GaN power amplifier 20 does not operate.

[0070] As a preferred implementation provided by the embodiment of the present utility model, Figure 5 This is a structural diagram of another power-on control circuit provided by an embodiment of the present utility model. Figure 5As shown, the comparison module 131 includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth capacitor C8, a ninth capacitor C9 and a comparator OP1.

[0071] The output terminal OUT1 of the comparator OP1 serves as the output terminal of the comparison module 131. The first end of the third resistor R3 serves as the first input terminal of the comparison module 131, and the second end of the third resistor R3 is connected to the non-inverting input terminal of the comparator OP1. The first end of the fourth resistor R4 is connected to the second end of the third resistor R3, and the second end of the fourth resistor R4 is grounded. The first end of the fifth resistor R5 is connected to the third voltage VCC3, and the second end of the fifth resistor R5 is connected to the inverting input terminal of the comparator OP1 and serves as the second input terminal of the comparison module 131. The first end of the sixth resistor R6 is connected to the second end of the fifth resistor R5, and the second end of the sixth resistor R6 is grounded. The first end of the seventh resistor R7 is connected to the output terminal of the comparator OP1, and the second end of the seventh resistor R7 is connected to the positive power supply input terminal V1+ of the comparator OP1. The first end of the eighth capacitor C8 is connected to the second end of the third resistor R3, and the second end of the eighth capacitor C8 is grounded. The first end of the ninth capacitor C9 is connected to the third voltage VCC3, and the second end of the ninth capacitor C9 is grounded. The negative power supply input terminal V1- of the comparator OP1 is grounded.

[0072] Specifically, the reference voltage Vref is the voltage of the third voltage VCC3 after being divided by the voltage divider circuit composed of the third resistor R3 and the fourth resistor R4. In other words, Vref = r4*VCC3 / (r3+r4). Where r3 is the resistance value of the third resistor R3, and r4 is the resistance value of the fourth resistor R4. The embodiment of the utility model does not specifically limit the magnitude of the third voltage VCC3 and the reference voltage Vref, and can be set according to actual conditions. For example, the third voltage VCC3 can be 3.3V and the reference voltage Vref can be 2.2V. The eighth capacitor C8 and the ninth capacitor C9 are filter capacitors.

[0073] Comparator OP1 outputs a corresponding level signal based on the voltage relationship between its non-inverting input and its inverting input. When the voltage at its non-inverting input is greater than the voltage at its inverting input, comparator OP1 outputs a first level signal. When the voltage at its non-inverting input is less than the voltage at its inverting input, comparator OP1 outputs a second level signal. For example, when the first output voltage of gate control circuit 12 is -2.73V, i.e., the second output voltage is 2.73V, the voltage at its non-inverting input is greater than the voltage at its inverting input, and comparator OP1 outputs a first level signal.

[0074] Optionally, continue to refer to Figure 5 The logic gate circuit 132 includes an AND gate U3, an eighth resistor R8, a ninth resistor R9, and a tenth capacitor C10.

[0075] The first input end of the AND gate U3 serves as the first input end of the logic gate circuit 132, the second input end of the AND gate U3 serves as the second input end of the logic gate circuit 132, the output end of the AND gate U3 is connected to the first end of the ninth resistor R9, and the second end of the ninth resistor R9 serves as the output end of the logic gate circuit 132.

[0076] The eighth resistor R8 is connected between the second input terminal of the AND gate U3 and the ground terminal. The tenth capacitor C10 is connected between the power supply terminal of the AND gate U3 and the ground terminal. The power supply terminal of the AND gate U3 is connected to the third voltage VCC3.

[0077] Continue to refer Figure 5 The working principle of the power-on control circuit 1 provided in the embodiment of the present utility model is as follows:

[0078] After the system is powered on, the controller 11 begins operation. Based on the system's initial state and the preset power-on strategy, it issues control instructions to the gate voltage control circuit 12, adjusts the output voltage of the gate voltage control circuit 12, and issues an enable signal PE to the control circuit 13. Following the instructions from the controller 11, the gate voltage control circuit 12 outputs a first output voltage to the gate of the GaN power amplifier 20 and simultaneously outputs a second output voltage to the comparator OP1.

[0079] Comparator OP1 compares the second output voltage with the reference voltage Vref. When the second output voltage rises above the reference voltage Vref, the leakage switch circuit 14 is turned on, and the gate voltage reaches the cutoff voltage. Comparator OP1 then outputs a first-level signal. Since both inputs of AND gate U3 are high-level signals, AND gate U3 outputs a high-level signal, gradually turning on leakage switch circuit 14. The drain of GaN power amplifier 20 receives a positive voltage. The gate voltage is then slowly adjusted to ensure that the drain current reaches the target quiescent current value, and the RF signal is finally input. When the second output voltage is less than the reference voltage Vref, comparator OP1 outputs a second-level signal. At this time, AND gate U3 receives a low-level signal at its first input and a high-level signal at its second input. AND gate U3 outputs a low-level signal, and leakage switch circuit 14 remains off. The positive voltage at the drain of GaN power amplifier 20 is cut off, and GaN power amplifier 20 does not operate.

[0080] Figure 6 This is a structural diagram of another power-on control circuit provided by an embodiment of the present utility model. Figure 6 As shown, optionally, the leakage voltage switch circuit 14 includes a first transistor T1, a second transistor T2, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11 and a twelfth resistor R12.

[0081] A first end of the tenth resistor R10 is connected to the gate of the first transistor T1, and a second end of the tenth resistor R10 is grounded. The gate of the first transistor T1 serves as the input of the leakage voltage switch circuit 14. The first electrode of the first transistor T1 is grounded, and the second electrode of the first transistor T1 is connected to the first end of the eleventh resistor R11. The second end of the eleventh resistor R11 is connected to the first end of the twelfth resistor R12 and the gate of the second transistor T2, respectively. The second end of the twelfth resistor R12 is connected to the first electrode of the second transistor T2 and is connected to the fourth voltage VCC4. The second electrode of the second transistor T2 serves as the output of the leakage voltage switch circuit 14.

[0082] Optionally, the first transistor T1 and the second transistor T2 have different channel types. Exemplarily, the first transistor T1 is an N-channel transistor, and the second transistor T2 is a P-channel transistor.

[0083] The embodiment of the present invention does not limit the specific value of the fourth voltage VCC4, and can be set according to actual needs. For example, the fourth voltage VCC4 can be 28V.

[0084] When the control circuit 13 outputs a first-level signal, the first transistor T1 and the second transistor T2 are turned on, providing a positive voltage to the drain of the GaN power amplifier 20. When the control circuit 13 outputs a second-level signal, the first transistor T1 and the second transistor T2 are turned off, cutting off the positive voltage to the drain of the GaN power amplifier 20 and disabling the GaN power amplifier 20.

[0085] Figure 7 This is a structural diagram of another power-on control circuit provided by an embodiment of the present utility model. Figure 7 As shown, optionally, the power-on control circuit 1 further includes a power amplifier drain protection circuit 15, wherein the control end of the power amplifier drain protection circuit 15 is connected to the output end of the control circuit, the first end of the power amplifier drain protection circuit 15 is connected to the drain of the GaN power amplifier 20, and the second end of the power amplifier drain protection circuit 15 is grounded, and is used to discharge the drain current of the GaN power amplifier 20 when the enable signal PE is invalid.

[0086] Specifically, when the enable signal PE is invalid, the power amplifier drain protection circuit 15 starts working, and its main function is to discharge the drain current of the GaN power amplifier 20. This is very important because in some cases, if the enable signal PE is invalid and there is still current on the drain of the GaN power amplifier 20, it may cause damage to the GaN power amplifier 20 or affect its performance. By discharging the drain current of the GaN power amplifier 20, it can be ensured that the drain of the GaN power amplifier 20 is in a safe potential state when the GaN power amplifier 20 is not needed to work. For example, when the power-on control circuit 1 fails or requires maintenance, the enable signal PE is turned off. At this time, the power amplifier drain protection circuit 15 can respond quickly and guide the drain current to the ground, preventing potential dangerous situations from occurring and protecting the safety of the GaN power amplifier 20 and the entire system.

[0087] Figure 8 This is a structural diagram of another power-on control circuit provided by an embodiment of the present utility model. Figure 8 As shown, the power amplifier drain protection circuit 15 includes a third transistor T3, a fourth transistor T4, a thirteenth resistor R13, a fourteenth resistor R14 and a fifteenth resistor R15.

[0088] The gate of the third transistor T3 serves as the control terminal of the power amplifier drain protection circuit 15. The first terminal of the third transistor T3 is grounded, and the second terminal of the third transistor T3 is connected to the first terminal of a thirteenth resistor R13. The second terminal of the thirteenth resistor R13 is connected to the first voltage VCC1. The first terminal of the fourteenth resistor R14 is connected to the gate of the fourth transistor T4, and the second terminal of the fourteenth resistor R14 is grounded. The first terminal of the fourth transistor T4 is grounded, and the second terminal of the fourth transistor T4 is connected to the first terminal of a fifteenth resistor R15. The second terminal of the fifteenth resistor R15 serves as the first terminal of the power amplifier drain protection circuit 15.

[0089] Optionally, the third transistor T3 and the fourth transistor T4 have the same channel type. Exemplarily, the third transistor T3 and the fourth transistor T4 are both N-channel transistors.

[0090] Continue to refer Figure 8 The operating principle of the power amplifier drain protection circuit 15 is as follows: when the enable signal PE is deasserted, the control circuit 13 outputs a second-level signal, the leakage switch circuit 14 is disconnected, and the drain of the GaN power amplifier 20 is powered off. At this point, the gate of the third transistor T3 is pulled low, turning off the third transistor T3. The first voltage VCC1 pulls up the gate of the fourth transistor T4 through the thirteenth resistor R13, turning on the fourth transistor T4. After the fourth transistor T4 is turned on, the drain current of the GaN power amplifier 20 can flow to ground through the fifteenth resistor R15 and the fourth transistor T4, thus dissipating the drain current.

[0091] Figure 9This is a schematic diagram of the structure of a GaN power amplifier provided by an embodiment of the present utility model. Figure 9 As shown, the GaN power amplifier 20 includes a magnetic bead Ln1, a sixteenth resistor R16, a seventeenth resistor R17, a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4, an eleventh capacitor C11 and a power amplifier chip U4.

[0092] The first end of the magnetic bead Ln1 serves as the gate G of the GaN power amplifier 20, and the second end of the magnetic bead Ln1 is respectively connected to the first end of the sixteenth resistor R16 and the first end of the seventeenth resistor R17, the second end of the sixteenth resistor R16 is connected to the first gate negative voltage power supply pin VGG1 of the power amplifier chip U4, and the second end of the seventeenth resistor is connected to the second gate negative voltage power supply pin VGG2 of the power amplifier chip U4.

[0093] The first end of the first inductor L1 serves as the drain D of the GaN power amplifier 20. The second end of the first inductor L1 is connected to the power supply pin VDD1 of the power amplifier chip U4. The first end of the second inductor L2 is connected to the first end of the first inductor L1. The second end of the second inductor L2 is connected to the first RF output pin RFOUT1 and the second RF output pin RFOUT2 of the power amplifier chip U4.

[0094] The first end of the third inductor L3 is connected to the second end of the second inductor L2, the second end of the third inductor L3 is connected to the first end of the fourth inductor L4, the second end of the fourth inductor L4 is connected to the first end of the eleventh capacitor C11, and the second end of the eleventh capacitor C11 serves as the output terminal PA-OUT of the GaN power amplifier 20 for outputting a radio frequency signal.

[0095] The first RF input pin RFIN1 and the second RF input pin RFIN2 of the power amplifier chip U4 serve as the RF input terminal PA-IN of the GaN power amplifier 20 for inputting RF signals. The other pins of the power amplifier chip U4 are all grounded. For example, the power amplifier chip U4 may be a CM1104B chip.

[0096] Figure 10 This is a structural diagram of another power-on control circuit provided by an embodiment of the present utility model. Figure 10 As shown, the power-on control circuit 1 includes: a controller 11 , a gate voltage control circuit 12 , a control circuit 13 and a leakage voltage switch circuit 14 .

[0097] Optionally, the gate voltage control circuit 12 includes a digital-to-analog converter 121 and an inverting regulator 122. Optionally, the digital-to-analog converter 121 includes a digital-to-analog conversion chip U1, a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. Optionally, the inverting regulator 122 includes a voltage conversion chip U2, a fifth capacitor C5, a sixth capacitor C6, and a seventh capacitor C7.

[0098] Optionally, the control circuit 13 includes a comparison module 131 and a logic gate circuit 132. Optionally, the comparison module 131 includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth capacitor C8, a ninth capacitor C9, and a comparator OP1. Optionally, the logic gate circuit 132 includes an AND gate U3, an eighth resistor R8, a ninth resistor R9, and a tenth capacitor C10.

[0099] Optionally, the leakage voltage switch circuit 14 includes a first transistor T1 , a second transistor T2 , a ninth resistor R9 , a tenth resistor R10 , an eleventh resistor R11 , and a twelfth resistor R12 .

[0100] Optionally, the power-on control circuit 1 further includes a power amplifier drain protection circuit 15. Optionally, the power amplifier drain protection circuit 15 includes a third transistor T3, a fourth transistor T4, a thirteenth resistor R13, a fourteenth resistor R14, and a fifteenth resistor R15.

[0101] Optionally, the GaN power amplifier 20 includes a magnetic bead Ln1, a sixteenth resistor R16, a seventeenth resistor R17, a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4, an eleventh capacitor C11 and a power amplifier chip U4.

[0102] Continue to refer Figure 10 The working principle of the power-on control circuit 1 provided in the embodiment of the present utility model is as follows:

[0103] After the system is powered on, controller 11 begins operation. Based on the system's initial state and the preset power-up strategy, it issues control instructions to DAC chip U1, adjusts its output voltage, and sends an enable signal PE to AND gate U3. Following the instructions from controller 11, DAC chip U1 outputs a second output voltage to comparator OP1. This second output voltage is then converted to a first output voltage by voltage converter chip U2.

[0104] Comparator OP1 compares the second output voltage with a reference voltage Vref. When the second output voltage is less than the reference voltage Vref, comparator OP1 outputs a second-level signal. At this point, AND gate U3 receives a low-level signal at its first input and a high-level signal at its second input. AND gate U3 outputs a low-level signal, turning off both transistors T1 and T2. This cuts off the positive voltage at the drain of GaN amplifier 20, and GaN amplifier 20 stops operating.

[0105] When the second output voltage rises above the reference voltage Vref, the gate voltage is determined to have reached the cutoff voltage, and comparator OP1 outputs a first-level signal. Since both inputs of AND gate U3 are high-level signals, AND gate U3 outputs a high-level signal, turning on both first transistor T1 and second transistor T2, providing a positive voltage to the drain of GaN power amplifier 20.

[0106] By reading the output current of the DAC chip U1, the controller 11 determines the gate current of the GaN amplifier 20. It then compares the actual output gate current (i.e., the current current) with the drain current (i.e., the target current) set when the GaN amplifier 20 is operating at its optimal quiescent point. If the current current differs from the target current, the controller adjusts the output voltage of the DAC chip U1 via an I2C signal, thereby maintaining the optimal quiescent point for the GaN amplifier 20 and finally inputting the RF signal.

[0107] When the enable signal PE is deasserted, the logic gate circuit 132 outputs a low-level signal, disconnecting the drain switch circuit 14 and de-energizing the drain D of the GaN power amplifier 20. At this point, the gate of the third transistor T3 is pulled low, turning off the third transistor T3. The first voltage VCC1 pulls up the gate of the fourth transistor T4 through the thirteenth resistor R13, turning on the fourth transistor T4. After the fourth transistor T4 is turned on, the drain current of the GaN power amplifier 20 can flow to ground through the fifteenth resistor R15 and the fourth transistor T4, thus dissipating the drain current.

[0108] Based on the same utility model concept, the utility model also provides a control method for a power-on control circuit. Figure 11 This is a flow chart of a control method for a power-on control circuit provided by an embodiment of the present utility model. The technical solution of the embodiment of the present utility model can be executed by each power-on control circuit provided by an embodiment of the present utility model. Figure 11 As shown, the control method provided by the embodiment of the present utility model specifically includes the following steps:

[0109] S101 , when an enable signal is valid and the output voltage of the second output terminal of the gate voltage control circuit is greater than a reference voltage, the control circuit determines that the gate voltage reaches a turn-off voltage, thereby controlling the leakage voltage switch circuit to be turned on.

[0110] S102 , when the leakage voltage switch circuit is turned on, it provides a positive voltage to the drain of the GaN power amplifier.

[0111] The similarities between the control method of the power-on control circuit provided in the embodiment of the present invention and the power-on control circuit can be referred to the corresponding explanation of the power-on control circuit, which will not be repeated here.

[0112] The above specific embodiments do not limit the scope of protection of this utility model. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model shall be included within the scope of protection of this utility model.

Claims

1. A power-on control circuit, characterized in that: Used to control the power-on of the GaN power amplifier, the power-on control circuit includes: a controller, a gate voltage control circuit, a control circuit and a leakage voltage switch circuit; The controller is in communication with the gate voltage control circuit and is used to control the magnitude of the output voltage of the gate voltage control circuit; The first output terminal of the gate voltage control circuit is connected to the gate of the GaN power amplifier, and the second output terminal of the gate voltage control circuit is connected to the first input terminal of the control circuit, for controlling the gate voltage of the GaN power amplifier; The second input terminal of the control circuit is connected to a reference voltage, and the third input terminal of the control circuit is connected to an enable signal, so as to determine that the gate voltage reaches the turn-off voltage when the enable signal is valid and the output voltage of the second output terminal of the gate voltage control circuit is greater than the reference voltage, thereby controlling the leakage voltage switch circuit to be turned on; The input end of the leakage voltage switch circuit is connected to the output end of the control circuit, and the output end of the leakage voltage switch circuit is connected to the drain of the GaN power amplifier, so as to provide a positive voltage to the drain of the GaN power amplifier when the circuit is turned on.

2. The power-on control circuit according to claim 1, characterized in that: The gate voltage control circuit includes a digital-to-analog converter and an inverting voltage regulator; The output end of the digital-to-analog converter is connected to the input end of the inverting regulator, and is used to convert the input digital signal into an analog voltage signal of corresponding proportion and output; The output end of the inverting regulator is connected to the gate of the GaN power amplifier, and is used to invert and output the analog voltage signal to the GaN power amplifier to provide a negative bias voltage for the gate of the GaN power amplifier.

3. The power-on control circuit according to claim 2, characterized in that: The digital-to-analog converter includes a digital-to-analog conversion chip, a first resistor, a second resistor, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor; The first resistor is connected between the clock line pin of the digital-to-analog conversion chip and the controller; the second resistor is connected between the data line pin of the digital-to-analog conversion chip and the controller; The first capacitor is connected between the output pin of the digital-to-analog conversion chip and the ground terminal, the second capacitor is connected between the reference voltage input pin of the digital-to-analog conversion chip and the ground terminal, the third capacitor is connected between the power pin of the digital-to-analog conversion chip and the ground terminal, and the fourth capacitor is connected between the logic power pin of the digital-to-analog conversion chip and the ground terminal; The power pin of the digital-to-analog conversion chip is connected to a first voltage, the logic power pin of the digital-to-analog conversion chip is connected to a second voltage, and the output pin of the digital-to-analog conversion chip serves as the output end of the digital-to-analog converter.

4. The power-on control circuit according to claim 2, characterized in that: The inverting voltage regulator includes a voltage conversion chip, a fifth capacitor, a sixth capacitor and a seventh capacitor; The fifth capacitor is connected between the capacitor negative pin and the capacitor positive pin of the voltage conversion chip, the sixth capacitor is connected between the shutdown control pin of the voltage conversion chip and the ground terminal, and the seventh capacitor is connected between the negative voltage output pin of the voltage conversion chip and the ground terminal; The positive power input pin of the voltage conversion chip serves as the input end of the inverting regulator, the shutdown control pin of the voltage conversion chip is connected to the positive power input pin of the voltage conversion chip, and the negative voltage output pin of the voltage conversion chip serves as the output end of the inverting regulator.

5. The power-on control circuit according to claim 1, characterized in that: The control circuit includes a comparison module and a logic gate circuit; The first input terminal of the comparison module serves as the first input terminal of the control circuit, the second input terminal of the comparison module serves as the second input terminal of the control circuit, the output terminal of the comparison module is connected to the first input terminal of the logic gate circuit, the comparison module is configured to output a first level signal when the output voltage of the second output terminal of the gate voltage control circuit is greater than the reference voltage, and output a second level signal when the output voltage of the second output terminal of the gate voltage control circuit is less than the reference voltage, wherein the first level signal and the second level signal are signals of opposite high and low levels to each other; The second input end of the logic gate circuit serves as the third input end of the control circuit, and the output end of the logic gate circuit serves as the output end of the control circuit, and is used to control the leakage voltage switch circuit to be turned on when the enable signal is valid and the comparison module outputs the first level signal, so as to provide a positive voltage to the drain of the GaN power amplifier.

6. The power-on control circuit according to claim 5, characterized in that: The comparison module includes a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth capacitor, a ninth capacitor and a comparator; The output end of the comparator serves as the output end of the comparison module; The first end of the third resistor serves as the first input end of the comparison module, and the second end of the third resistor is connected to the non-inverting input end of the comparator; The first end of the fourth resistor is connected to the second end of the third resistor, and the second end of the fourth resistor is grounded; The first end of the fifth resistor is connected to the third voltage, and the second end of the fifth resistor is connected to the inverting input end of the comparator and serves as the second input end of the comparison module; The first end of the sixth resistor is connected to the second end of the fifth resistor, and the second end of the sixth resistor is grounded; A first end of the seventh resistor is connected to the output end of the comparator, and a second end of the seventh resistor is connected to the positive power input end of the comparator; A first end of the eighth capacitor is connected to the second end of the third resistor, and a second end of the eighth capacitor is grounded; A first end of the ninth capacitor is connected to the third voltage, and a second end of the ninth capacitor is grounded.

7. The power-on control circuit according to claim 5, characterized in that: The logic gate circuit includes an AND gate, an eighth resistor, a ninth resistor and a tenth capacitor; The first input end of the AND gate serves as the first input end of the logic gate circuit, the second input end of the AND gate serves as the second input end of the logic gate circuit, the output end of the AND gate is connected to the first end of the ninth resistor, and the second end of the ninth resistor serves as the output end of the logic gate circuit; The eighth resistor is connected between the second input terminal of the AND gate and the ground terminal, the tenth capacitor is connected between the power supply terminal of the AND gate and the ground terminal, and the power supply terminal of the AND gate is connected to a third voltage.

8. The power-on control circuit according to claim 1, wherein: The leakage voltage switch circuit includes a first transistor, a second transistor, a ninth resistor, a tenth resistor, an eleventh resistor and a twelfth resistor; A first end of the tenth resistor is connected to the gate of the first transistor, and a second end of the tenth resistor is grounded; The gate of the first transistor serves as an input terminal of the leakage voltage switch circuit, the first electrode of the first transistor is grounded, and the second electrode of the first transistor is connected to the first end of the eleventh resistor; The second end of the eleventh resistor is respectively connected to the first end of the twelfth resistor and the gate of the second transistor, the second end of the twelfth resistor is connected to the first electrode of the second transistor and is connected to the fourth voltage, and the second electrode of the second transistor serves as the output end of the leakage switch circuit.

9. The power-on control circuit according to claim 1, characterized in that: It also includes a power amplifier drain protection circuit, wherein the control end of the power amplifier drain protection circuit is connected to the output end of the control circuit, the first end of the power amplifier drain protection circuit is connected to the drain of the GaN power amplifier, and the second end of the power amplifier drain protection circuit is grounded, and is used to discharge the drain current of the GaN power amplifier when the enable signal is invalid.

10. The power-on control circuit according to claim 9, characterized in that: The power amplifier drain protection circuit includes a third transistor, a fourth transistor, a thirteenth resistor, a fourteenth resistor and a fifteenth resistor; The gate of the third transistor serves as the control terminal of the power amplifier drain protection circuit, the first electrode of the third transistor is grounded, and the second electrode of the third transistor is connected to the first end of the thirteenth resistor; The second end of the thirteenth resistor is connected to the first voltage, the first end of the fourteenth resistor is connected to the gate of the fourth transistor, and the second end of the fourteenth resistor is grounded; The first electrode of the fourth transistor is grounded, the second electrode of the fourth transistor is connected to the first end of the fifteenth resistor, and the second end of the fifteenth resistor serves as the first end of the power amplifier drain protection circuit.

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