MCU-based polymorphic IO interface circuit

Abstract

The utility model provides a multi-state IO interface circuit based on an MCU. The multi-state IO interface circuit comprises an input unit and an output unit which are connected with each other. Wherein the input unit is composed of a voltage division circuit and a filter circuit, one end of the voltage division circuit is connected with an IO pin of the MCU, the filter circuit is connected with an AD pin of the MCU, and the AD pin is configured to collect input signals; the output unit is composed of a first switch tube, a third switch tube, an overcurrent protection circuit and a driving circuit, one end of the overcurrent protection circuit is connected with the IO pin, the first switch tube and the third switch tube, the other end of the overcurrent protection circuit is connected with an ERR pin of the MCU, the first switch tube is connected with the driving circuit, the driving circuit is connected with a DOH pin of the MCU, and the third switch tube is connected with a DOL pin of the MCU. The circuit provided by the utility model is simple in structure and low in circuit construction cost, and can realize acquisition or control of various peripheral signals without configuring various interface modules.

Description

Technical Field

[0001] The utility model belongs to the technical field of interface circuits, and in particular relates to a polymorphic IO interface circuit based on an MCU. Background Art

[0002] Existing IO interface circuits have a single function, and are mostly fixed NPN or PNP input or output structures. Furthermore, Japanese sensors currently generally use NPN type outputs, which are low-level outputs; European sensors generally use PNP type outputs, which are high-level outputs.

[0003] In actual projects, there may be situations where both output forms need to be used. In this case, two interface acquisition circuits need to be equipped. The same situation also exists in the external devices controlled by the output part. Different output circuit structures need to be configured for NPN and PNP types, which increases the project materials and complicates the system. Utility Model Content

[0004] In view of this, the present invention aims to propose a polymorphic IO interface circuit based on MCU to solve the problem that the existing IO interface circuit has a single function, which leads to an increase in project materials and a complex system.

[0005] In order to achieve the above-mentioned purpose, the technical solution of the utility model is achieved as follows:

[0006] The utility model provides a polymorphic IO interface circuit based on MCU, comprising an input unit and an output unit connected to each other;

[0007] The input unit is composed of a voltage divider circuit and a filter circuit, one end of the voltage divider circuit is connected to the IO pin of the MCU, the IO pin is configured to receive an external input signal, and the filter circuit is connected to the AD pin of the MCU, the AD pin is configured to collect the input signal;

[0008] The output unit is composed of a first switching tube, a third switching tube, an overcurrent protection circuit and a drive circuit. One end of the overcurrent protection circuit is connected to the IO pin, the first switching tube and the third switching tube respectively, and the other end is connected to the ERR pin of the MCU. The first switching tube is connected to the power supply end and to the drive circuit. The drive circuit is connected to the DO_H pin of the MCU. The drive circuit is used to drive the first switching tube. The third switching tube is connected to the DO_L pin of the MCU.

[0009] Furthermore, the voltage divider circuit includes a third resistor, an eighth resistor, and an eleventh resistor;

[0010] One end of the third resistor and one end of the eighth resistor are both connected to the IO pin;

[0011] The other end of the third resistor is connected to a 24V power supply, and the other end of the eighth resistor is grounded through the eleventh resistor.

[0012] Furthermore, the filtering circuit includes a ninth resistor and a first capacitor;

[0013] One end of the ninth resistor is connected to the line between the eighth resistor and the eleventh resistor, and the other end is connected to the AD pin;

[0014] One end of the first capacitor is connected to the line between the ninth resistor and the AD pin, and the other end is grounded.

[0015] Furthermore, a protection circuit is included, wherein the protection circuit includes a second diode and a third diode;

[0016] The cathode of the second diode is connected to the IO pin, and the anode of the second diode is grounded;

[0017] A cathode of the third diode is connected to a line between the eighth resistor and the eleventh resistor, and an anode of the third diode is grounded.

[0018] Furthermore, the cathode of the third diode is also connected to the TEST pin of the MCU through a sixteenth resistor.

[0019] Furthermore, the overcurrent protection circuit includes a photocoupler, and a first resettable fuse and a second resettable fuse connected in parallel;

[0020] One end of the first resettable fuse and the second resettable fuse is connected to the IO pin, the first resettable fuse is connected to the first pin of the photocoupler through a fourth resistor, and the second resettable fuse is connected to the second pin of the photocoupler;

[0021] The third pin of the photoelectric coupler is grounded, and the fourth pin of the photoelectric coupler is respectively connected to the ERR pin and to a 5V power supply via a sixth resistor.

[0022] Furthermore, the third end of the first switch tube is connected to a 24V power supply, and the second end of the first switch tube is connected to a line between the first resettable fuse and the fourth resistor;

[0023] The driving circuit includes a second switching transistor, wherein a first end of the second switching transistor is connected to a first end of the first switching transistor via a second resistor, a second end of the second switching transistor is connected to the DO_H pin via a fifth resistor and to ground via a seventh resistor, and a third end of the second switching transistor is grounded;

[0024] It also includes a first diode and a first resistor connected in parallel, the anode of the first diode and one end of the first resistor are connected to the line between the third switching tube and the second resistor, and the cathode of the first diode and the other end of the first resistor are both connected to a 24V power supply.

[0025] Furthermore, the first end of the third switch tube is connected to the DO_L pin through a tenth resistor and to ground through a twelfth resistor, the second end of the third switch tube is grounded, and the third end of the third switch tube is connected to the line between the second resettable fuse and the optocoupler.

[0026] Furthermore, the first switch tube is an NMOS tube, and the third switch tube is a PMOS tube.

[0027] Furthermore, the second switching tube is an NPN transistor.

[0028] Compared with the prior art, the MCU-based polymorphic IO interface circuit described in the present invention has the following beneficial effects:

[0029] The utility model discloses an MCU-based polymorphic IO interface circuit, which integrates NPN and PNP input acquisition circuits and output circuits, and adds overvoltage and overload protection and circuit self-test functions, which greatly facilitates the use of engineering projects. At the same time, the circuit structure is simple, the circuit construction cost is low, and the acquisition or control of various peripheral signals can be achieved without configuring multiple interface modules. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings, which constitute part of the present invention, are intended to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are intended to explain the present invention and do not constitute an improper limitation of the present invention. In the accompanying drawings:

[0031] Figure 1 This is a circuit diagram of a polymorphic IO interface based on MCU according to an embodiment of the present utility model. DETAILED DESCRIPTION

[0032] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features therein can be combined with each other.

[0033] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0034] See also Figure 1 As shown, this embodiment provides a polymorphic IO interface circuit based on an MCU, including an input unit and an output unit connected to each other;

[0035] The input unit is composed of a voltage divider circuit and a filter circuit. One end of the voltage divider circuit is connected to the IO pin of the MCU, and the IO pin is configured to receive an external input signal. The filter circuit is connected to the AD pin of the MCU, and the AD pin is configured to collect the input signal.

[0036] The output unit consists of a first switching tube, a third switching tube, an overcurrent protection circuit and a drive circuit. One end of the overcurrent protection circuit is connected to the IO pin, the first switching tube and the third switching tube respectively, and the other end is connected to the ERR pin of the MCU. The first switching tube is connected to the power supply end and to the drive circuit. The drive circuit is connected to the DO_H pin of the MCU. The drive circuit is used to drive the first switching tube. The third switching tube is connected to the DO_L pin of the MCU.

[0037] Specifically, in this embodiment, for the input unit, the functions are described as follows:

[0038] Analog acquisition: The signal is input from the IO pin, divided by the voltage divider circuit and filtered by the filter circuit, and then input to the AD pin of the MCU for acquisition;

[0039] Switch quantity acquisition: The signal is input from the IO pin, divided by the voltage divider circuit and filtered by the filter circuit, and then input to the AD pin of the MCU for acquisition. According to the range of the acquired voltage, the three states of high, low and floating can be identified.

[0040] As for the output unit, it can execute three-state output of switch quantity (high, low, floating). The specific functions are described as follows:

[0041] Output high level: the first switch tube Q1 is turned on, the third switch tube Q3 is turned off, and the IO pin outputs a high potential;

[0042] Output low level: the first switch tube Q1 is turned off, the third switch tube Q3 is turned on, and the IO pin outputs a low potential;

[0043] Output off: The first switch tube Q1 and the third switch tube Q3 are both turned off, and the IO pin output is in a floating state.

[0044] Overcurrent detection: When the load is short-circuited or overloaded, the overcurrent protection circuit can detect the overload state from the ERR pin;

[0045] Output fault: When the output is high or low, the actual output potential can be detected from the AD interface of the input unit circuit to realize output fault detection.

[0046] The interface circuit can be freely switched between input mode and output mode according to actual usage requirements. When used as input, the output unit DO_H pin and DO_L pin are both controlled by the MCU to a low level, the switch tubes Q1 and Q3 are cut off, and the output unit is in a suspended state. Then, in this state, the state of the port IO pin can be collected through the input unit, that is, the externally connected sensor signal is collected through the IO pin.

[0047] When used as output, the DO_H pin and DO_L pin are controlled by the MCU as needed (it should be noted that the control of the MCU is realized by an external PLC or other control system connected to the MCU, that is, the control of the MCU is realized by an external PLC, which will not be elaborated here) to a high level or a low level, thereby controlling whether the switch tubes Q1 and Q3 are turned on. At the same time, the input unit also collects the output status to determine whether the output is normal.

[0048] The IO interface circuit described in this embodiment integrates NPN and PNP input acquisition circuits and output circuits, and adds overvoltage and overload protection and circuit self-test functions, which greatly facilitates the use of engineering projects. At the same time, the circuit structure is simple, the circuit construction cost is low, and it can realize the acquisition or control of various peripheral signals without configuring multiple interface modules.

[0049] In some embodiments, the input unit is composed of a voltage divider circuit, a filter circuit, and a protection circuit, specifically, diodes D2 and D3, resistors R3, R8, R11, R9, R16, and a capacitor C1;

[0050] The voltage divider circuit includes a third resistor R3, an eighth resistor R8, and an eleventh resistor R11. One end of each of the third resistor R3 and the eighth resistor R8 is connected to the IO pin, the other end of the third resistor R3 is connected to a 24V power supply, and the other end of the eighth resistor R8 is grounded via the eleventh resistor R11.

[0051] The filter circuit includes a ninth resistor R9 and a first capacitor C1, wherein one end of the ninth resistor R9 is connected to the line between the eighth resistor R8 and the eleventh resistor R11, and the other end is connected to the AD pin. One end of the first capacitor C1 is connected to the line between the ninth resistor R9 and the AD pin, and the other end is grounded.

[0052] The protection circuit includes a second diode D2 and a third diode D3, wherein the cathode of the second diode D2 is connected to the IO pin, the anode of the second diode D2 is grounded, the cathode of the third diode D3 is connected to the line between the eighth resistor R8 and the eleventh resistor R11, and the anode of the third diode D3 is grounded;

[0053] The cathode of the third diode D3 is also connected to the TEST pin of the MCU via the sixteenth resistor R16.

[0054] Specifically, in this embodiment, the voltage divider circuit composed of resistors R3, R8, and R11 plays a voltage dividing role, reducing the high voltage of the external input and attenuating it to reach the range that the MCU can collect; the filter circuit composed of resistors R9 and C1 filters the input signal to reduce the influence of interference signals; the protection circuit composed of diodes D2 and D3 plays a protective role in absorbing pulse spikes.

[0055] It should be noted that resistor R16 is a loop detection output current limiting resistor. With the help of the TEST pin, the loop can be self-checked to determine whether there is any output fault.

[0056] In some embodiments, the overcurrent protection circuit includes a photocoupler U1, and a first resettable fuse F1 and a second resettable fuse F2 connected in parallel;

[0057] One end of the first resettable fuse F1 and the second resettable fuse F2 are connected to the IO pin, the first resettable fuse F1 is connected to the first pin of the photocoupler U1 through the fourth resistor R4, and the second resettable fuse F2 is connected to the second pin of the photocoupler U1;

[0058] The third pin of the photocoupler U1 is grounded, and the fourth pin of the photocoupler U1 is respectively connected to the ERR pin and to a 5V power supply via a sixth resistor R6.

[0059] Specifically, in this embodiment, the output overcurrent protection is composed of resettable fuses F1 and F2, resistors R4 and R6, and a photocoupler U1. When the load is short-circuited or overloaded, the resistance of the resettable fuse F1 or F2 increases, and the photocoupler U1 is turned on. The overload state can be detected from the ERR port, thereby realizing overcurrent detection of the circuit.

[0060] In some embodiments, the first switch tube Q1 is an NMOS tube, the drain terminal of the first switch tube Q1 is connected to a 24V power supply, and the source terminal of the first switch tube Q1 is connected to the line between the first resettable fuse F1 and the fourth resistor R4;

[0061] The drive circuit includes a second switching tube Q2, which is an NPN transistor. The collector terminal of the second switching tube Q2 is connected to the gate terminal of the first switching tube Q1 via a second resistor R2. The base terminal of the second switching tube Q2 is connected to the DO_H pin via a fifth resistor R5 and to ground via a seventh resistor R7. The emitter terminal of the second switching tube Q2 is grounded.

[0062] It also includes a first diode D1 and a first resistor R1 connected in parallel, the anode of the first diode D1 and one end of the first resistor R1 are connected to the line between the third switch tube Q3 and the second resistor R2, and the cathode of the first diode D1 and the other end of the first resistor R1 are both connected to a 24V power supply.

[0063] Specifically, in this embodiment, a driving circuit for the MOS transistor Q1 is formed by a diode D1, resistors R1, R2, R5, and R7, and a transistor Q2. Since the MOS transistor Q1 is connected to a 24V power supply and is at a high level, the driving circuit formed by the transistor Q2 controls the on / off state of the MOS transistor Q1. The high-potential output of the output unit is achieved by the on / off state of the MOS transistor Q1.

[0064] In some embodiments, the third switch tube Q3 is a PMOS tube, the gate terminal of the third switch tube Q3 is connected to the DO_L pin through the tenth resistor R10 and is grounded through the twelfth resistor R12, the source terminal of the third switch tube Q3 is grounded, and the drain terminal of the third switch tube Q3 is connected to the line between the second self-resettable fuse F2 and the optocoupler U1.

[0065] Specifically, in this embodiment, it relies on the switch tube Q3, the resistor R10 and the resistor R12, wherein the resistor R10 is used to maintain the potential at the initial power-on stage, and the resistor R12 is used to drive the current limit. The MCU controls the conduction and cutoff of the MOS tube Q3 to achieve a low-voltage output.

[0066] The IO interface circuit described in this embodiment integrates analog quantity acquisition, three-state acquisition of switch quantity (high, low, and floating), input self-detection function, three-state output of switch quantity (high, low, and floating), and output overcurrent protection and detection function, and can realize the acquisition or control of various peripheral signals.

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention, and they should all be included in the scope of the claims and description of the present invention.

[0068] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A polymorphic IO interface circuit based on an MCU, characterized in that: including connected input units and output units; The input unit is composed of a voltage divider circuit and a filter circuit, one end of the voltage divider circuit is connected to the IO pin of the MCU, the IO pin is configured to receive an external input signal, and the filter circuit is connected to the AD pin of the MCU, the AD pin is configured to collect the input signal; The output unit is composed of a first switching tube, a third switching tube, an overcurrent protection circuit and a drive circuit. One end of the overcurrent protection circuit is connected to the IO pin, the first switching tube and the third switching tube respectively, and the other end is connected to the ERR pin of the MCU. The first switching tube is connected to the power supply end and to the drive circuit. The drive circuit is connected to the DO_H pin of the MCU. The drive circuit is used to drive the first switching tube. The third switching tube is connected to the DO_L pin of the MCU.

2. The MCU-based polymorphic IO interface circuit according to claim 1, wherein: The voltage divider circuit includes a third resistor, an eighth resistor, and an eleventh resistor; One end of the third resistor and one end of the eighth resistor are both connected to the IO pin; The other end of the third resistor is connected to a 24V power supply, and the other end of the eighth resistor is grounded through the eleventh resistor.

3. The MCU-based polymorphic IO interface circuit according to claim 2, wherein: The filtering circuit includes a ninth resistor and a first capacitor; One end of the ninth resistor is connected to the line between the eighth resistor and the eleventh resistor, and the other end is connected to the AD pin; One end of the first capacitor is connected to the line between the ninth resistor and the AD pin, and the other end is grounded.

4. The MCU-based polymorphic IO interface circuit according to claim 2, wherein: Also included is a protection circuit, the protection circuit including a second diode and a third diode; The cathode of the second diode is connected to the IO pin, and the anode of the second diode is grounded; A cathode of the third diode is connected to a line between the eighth resistor and the eleventh resistor, and an anode of the third diode is grounded.

5. The MCU-based polymorphic IO interface circuit according to claim 4, characterized in that: The cathode of the third diode is also connected to the TEST pin of the MCU through a sixteenth resistor.

6. The MCU-based polymorphic IO interface circuit according to claim 1, wherein: The overcurrent protection circuit includes a photoelectric coupler, and a first resettable fuse and a second resettable fuse connected in parallel; One end of the first resettable fuse and the second resettable fuse is connected to the IO pin, the first resettable fuse is connected to the first pin of the photocoupler through a fourth resistor, and the second resettable fuse is connected to the second pin of the photocoupler; The third pin of the photoelectric coupler is grounded, and the fourth pin of the photoelectric coupler is respectively connected to the ERR pin and to a 5V power supply via a sixth resistor.

7. The MCU-based polymorphic IO interface circuit according to claim 6, characterized in that: The third end of the first switch tube is connected to a 24V power supply, and the second end of the first switch tube is connected to the line between the first resettable fuse and the fourth resistor; The driving circuit includes a second switching transistor, wherein a first end of the second switching transistor is connected to a first end of the first switching transistor via a second resistor, a second end of the second switching transistor is connected to the DO_H pin via a fifth resistor and to ground via a seventh resistor, and a third end of the second switching transistor is grounded; It also includes a first diode and a first resistor connected in parallel, the anode of the first diode and one end of the first resistor are connected to the line between the third switching tube and the second resistor, and the cathode of the first diode and the other end of the first resistor are both connected to a 24V power supply.

8. The MCU-based polymorphic IO interface circuit according to claim 7, characterized in that: The first end of the third switch tube is connected to the DO_L pin through a tenth resistor and to ground through a twelfth resistor, the second end of the third switch tube is grounded, and the third end of the third switch tube is connected to the line between the second resettable fuse and the optocoupler.

9. The MCU-based polymorphic IO interface circuit according to claim 8, characterized in that: The first switch tube is an NMOS tube, and the third switch tube is a PMOS tube.

10. The MCU-based polymorphic IO interface circuit according to claim 7, characterized in that: The second switch tube is an NPN transistor.

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