Integrated circuit chip and electronic component structure

Abstract

The utility model provides an integrated circuit chip and an electronic component structure. The integrated circuit chip comprises a component area, an interconnection structure arranged on the component area, and a sealing ring surrounding the component area and the interconnection structure. The device region includes a transistor having a gate structure. The seal ring includes a metal structure. The gate structure is thermally coupled with the metal structure through the diode. The integrated circuit chip can dissipate heat through the sealing ring. Therefore, the heat of the element can be effectively dissipated, and the performance of the element can be better.

Description

Technical Field

[0001] The utility model relates to an integrated circuit chip and an electronic component structure, in particular to an integrated circuit chip and an electronic component structure which can dissipate heat through a sealing ring. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous one. Over the course of IC evolution, functional density (i.e., the number of interconnected elements per chip area) has generally increased, while geometry size (i.e., the smallest component (or circuit) that can be created using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. However, this scaling down also increases the complexity of processing and manufacturing ICs.

[0003] For semiconductor devices fabricated on a bulk semiconductor substrate, the bulk semiconductor substrate acts as a heat sink, dissipating heat generated by the semiconductor components. In some technologies, the semiconductor substrate is thinned or significantly removed, making it impossible for the semiconductor components to dissipate heat through the substrate. This necessitates an alternative thermal path or heat sink. When heat from a semiconductor component cannot be effectively dissipated, its performance may be affected. Utility Model Content

[0004] An embodiment of the present invention provides an integrated circuit (IC) chip. The IC chip includes a component region, an interconnect structure disposed above the component region, and a seal ring surrounding the component region and the interconnect structure. The component region includes a transistor having a gate structure. The seal ring includes a metal structure. The gate structure is thermally coupled to the metal structure through a diode.

[0005] An embodiment of the present invention provides an electronic device structure. The device structure includes a backside dielectric layer; a transistor including a first well region disposed on the backside dielectric layer, a plurality of nanostructures disposed one above the other on the first well region, and a gate structure surrounding each nanostructure; a diode including a second well region disposed on the backside dielectric layer, a stack of multiple silicon layers and multiple silicon germanium layers interlaced above the second well region, a first doped region and a second doped region separated by a depletion region in the stack, and a floating gate structure on the depletion region; and a sealing ring metal structure spaced a distance from the transistor. The gate structure is electrically coupled to the first doped region. The second doped region is electrically coupled to the sealing ring metal structure.

[0006] Embodiments of the present application provide an electronic component structure. The component structure includes a transistor including a plurality of nanostructures and a gate structure wrapped around each of the plurality of nanostructures; a diode including a stack having a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers and a first doped region and a second doped region in the stack; and a seal ring metal structure spaced apart from the transistor by a distance. The gate structure is electrically coupled to the first doped region. The second doped region is electrically coupled to the seal ring metal structure.

[0007] Based on the above, since the integrated circuit (IC) chip or the electronic component structure can dissipate heat through the seal ring. Therefore, heat can be effectively dissipated, and the performance of the integrated circuit (IC) chip or the electronic component structure can be better.

[0008] In order to make the above features and advantages of the present application more obvious and easy to understand, the following embodiments are specifically described, and the detailed description is as follows in combination with the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 To show the top view of the substrate and the top view of the integrated circuit chip (IC) on the substrate according to one or more aspects of the present disclosure.

[0010] Figure 2 To show the cross-sectional view of the IC chip in Figure 1 according to one or more aspects of the present disclosure.

[0011] Figure 3 To schematically show the cross-sectional view of the heat conduction path between the component region and the seal ring surrounding the component region according to one or more aspects of the present disclosure.

[0012] Figure 4 and Figure 5 To show the partial cross-sectional view of the diode connected with the gate structure of the transistor and the metal structure in the seal ring according to one or more aspects of the present disclosure.

[0013] Figure 6 To schematically show the top view of the IC chip having the heat conduction path from the component region to the metal structure of the seal ring according to one or more aspects of the present disclosure.

[0014] REFERENCE NUMERALS

[0015] 10: semiconductor wafer;

[0016] 100: integrated circuit chip, IC chip (integrated circuit (IC) chip);

[0017] 102: device region;

[0018] 104: seal ring;

[0019] 104B: backside seal ring wall;

[0020] 104D: through-substrate contact structure;

[0021] 104F: frontside seal ring wall;

[0022] 106: scribe line;

[0023] 110: chuck;

[0024] 120: carrier wafer;

[0025] 130: bonding dielectric layer;

[0026] 140: frontside interconnect structure;

[0027] 150: front-end-of-line (FEOL) layer;

[0028] 152: backside dielectric layer;

[0029] 160: backside interconnect structure;

[0030] 200: transistor;

[0031] 202: doped substrate portion;

[0032] 204: isolation structure;

[0033] 206: second semiconductor layer;

[0034] 207: stack;

[0035] 208: first semiconductor layer;

[0036] 2080: channel member;

[0037] 210: source / drain features;

[0038] 212: inner spacer feature;

[0039] 214: gate structure;

[0040] 216: top gate spacer;

[0041] 220: contact etch stop layer (CESL);

[0042] 222: first interlayer dielectric (ILD) layer;

[0043] 224: first source / drain contact;

[0044] 226: second source / drain contact;

[0045] 228: etch stop layer (ESL);

[0046] 230: second interlayer dielectric (ILD) layer;

[0047] 232: third interlayer dielectric (ILD) layer;

[0048] 234: gate contact via;

[0049] 300: lateral diode;

[0050] 310: first doped region;

[0051] 310E: first epitaxial feature;

[0052] 311: depletion region;

[0053] 312: second doped region;

[0054] 312E: second epitaxial feature;

[0055] 314: dummy gate structure;

[0056] 316: top gate spacer;

[0057] 324: first contact;

[0058] 326: second contact;

[0059] 334: first contact via;

[0060] 336: second contact via;

[0061] 346: second metal line;

[0062] 348: connection via;

[0063] 360: third metal line;

[0064] 2000: standard cell region;

[0065] 3000: diode region;

[0066] 4000: memory region;

[0067] S: spacing;

[0068] X, Y, Z: direction. DETAILED DESCRIPTION

[0069] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. The following disclosure describes specific examples of each component and its arrangement to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if an embodiment of the present invention describes that a first characteristic component is formed on or above a second characteristic component, it means that it may include an embodiment in which the first characteristic component and the second characteristic component are in direct contact, and may also include an embodiment in which an additional characteristic component is formed between the first characteristic component and the second characteristic component, so that the first characteristic component and the second characteristic component may not be in direct contact. In addition, embodiments of the present invention may reuse marks and / or text in each example. This repetition is for the purpose of brevity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0070] Spatially relative terms, such as "below," "lower," "above," "over," and the like, may be used herein for descriptive convenience to describe one element or feature in relation to another element or feature, as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. The element may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein interpreted accordingly.

[0071] In addition, when a number or a range of numbers is described using the terms "about," "approximately," or the like, the term is intended to encompass numbers within a reasonable range that take into account variations inherent in manufacturing as understood by one of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing features having the properties associated with the number, the number or range of numbers encompasses a reasonable range that includes the described number, such as within + / - 10% of the described number. For example, a material layer having a thickness of "approximately 5 nm" may encompass a range of sizes from 4.25 nm to 5.75 nm, where the manufacturing tolerances associated with depositing the material layer are known to one of ordinary skill in the art to be + / - 15%. Furthermore, this disclosure may repeat reference numbers and / or letters in various examples. This repetition is for simplicity and clarity and does not, in itself, dictate the relationship between the various embodiments and / or configurations discussed. For the avoidance of doubt, the X, Y, and Z directions in the figures of this disclosure are perpendicular to each other. Throughout this disclosure, identical reference numbers represent identical features unless otherwise specified.

[0072] For semiconductor components fabricated on a bulk semiconductor substrate, the bulk semiconductor substrate can act as a heat sink to remove heat generated by the semiconductor components. In some technologies, the semiconductor substrate is thinned or largely removed, preventing the semiconductor components from dissipating heat through the semiconductor substrate, necessitating an alternative thermal path or heat sink. When heat from the semiconductor components cannot be effectively dissipated, the performance of the semiconductor components may be affected. For example, front-end-of-line (FEOL) components are interconnected via front-side and back-side interconnect structures. The semiconductor substrate used to fabricate the FEOL components may be thinned from over 750 microns to less than 1 micron to form back-side contacts that are electrically coupled to the FEOL components. The thinned semiconductor substrate may not be continuous, as there may be several dielectric isolation structures, such as shallow trench isolation (STI) features, that isolate adjacent FEOL components. In addition to these isolation structures, the front-side and back-side interconnect structures also include dielectric materials. The thermal conductivity of the dielectric materials in the isolation features and the dielectric materials in the interconnect structures is at least two orders of magnitude lower than that of the semiconductor substrate. Since FEOL components are surrounded by these poorly thermally conductive materials, it is challenging to satisfactorily dissipate the heat generated during operation of the FEOL components.

[0073] Figure 1 1 shows a schematic top view of an integrated circuit (IC) chip 100 fabricated on a semiconductor wafer 10. Figure 1 As shown, the IC chip 100 may be rectangular. The IC chip 100 includes a component area 102, which includes FEOL components and back-end-of-line (BEOL) components, such as interconnect structures. To prevent the component area 102 from being damaged by mist ingress or stress generated during the singulation process of the IC chip 100, the IC chip 100 includes a sealing ring 104 that completely surrounds the component area 102. The boundary of the IC chip 100 is defined by a dicing street 106, along which the IC chip 100 can be cut or singulated from the semiconductor wafer 10. The sealing ring 104 is located between the component area 102 and the dicing street 106. As described above, the function of the sealing ring 104 is to prevent the stress generated when cutting along the dicing street 106 from damaging the component area 102.

[0074] Figure 2 Provided Figure 1A partial cross-sectional view of the seal ring 104 and the element region 102 is shown in FIG. 1. First, attention is focused on the element region 102. The element region 102 includes an FEOL layer 150 that includes a transistor 200. The transistor 200 can be a planar element or a multi-gate element. A planar element refers to an element that has a gate structure in contact with one side of a channel region. As integrated circuit (IC) technology advances to smaller technology nodes, multi-gate elements have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current (off-current), and reducing short channel effects (SCEs). Multi-gate elements generally refer to elements that have a gate structure, or portions thereof, disposed on more than one side of a channel region. FinFETs and gate-all-around (GAA) transistors (both of which are also referred to as non-planar transistors) are examples of multi-gate elements that have become important and promising candidates for high performance and low leakage applications. FinFETs have a raised channel, and more than one side of this raised channel is wrapped by a gate (e.g., the gate wraps the top and sidewalls of a "fin" of semiconductor material that extends from a substrate). This configuration provides better control of the channel and substantially reduces SCEs compared to planar transistors (in particular, by reducing subthreshold leakage (i.e., the coupling between the source and drain of a FinFET in the "off' state)). GAA transistors have a gate structure that can partially or completely wrap around a channel region to provide access to the channel region on two or more sides. Due to this configuration, GAA transistors can also be referred to as surround gate transistors (SGTs) or multiple bridge channel (MBC) transistors. The channel region of a GAA transistor can be formed from nanowires, nanosheets, other nanostructures, and / or other suitable structures. These shapes of the channel region also give GAA transistors different names. For example, a GAA transistor with a nanosheet channel region can be referred to as a nanosheet transistor. In the illustrated embodiment, the transistor 200 is a GAA transistor. Heat dissipation from the gate structure can also be impeded due to the gate structure passing through a narrow space.

[0075] As the transistor 200 in the FEOL layer 150 continues to shrink in size, a single interconnect structure on one side of the FEOL layer 150 can not be able to adequately route signals. As shown in FIG. 1, the FEOL layer 150 includes a first interconnect structure 202 and a second interconnect structure 204. The first interconnect structure 202 is disposed on a first side of the FEOL layer 150, and the second interconnect structure 204 is disposed on a second side of the FEOL layer 150. The first and second interconnect structures 202 and 204 are coupled to the transistor 200. The first and second interconnect structures 202 and 204 can be coupled to the transistor 200 through contacts 206 and 208, respectively. The contacts 206 and 208 can be formed from tungsten, copper, or other suitable materials. The contacts 206 and 208 can be formed by a damascene process, a gate-last process, or other suitable processes. The contacts 206 and 208 can be formed by a gate-first process, a gate-last process, or other suitable processes. The contacts 206 and 208 can be formed by a gate-first process, a gate-last process, or other suitable processes. Figure 2As shown, the device region 102 includes a front side interconnect structure 140 and a back side interconnect structure 160. In some embodiments, the front side interconnect structure 140 can include nine to fourteen metallization layers, while the back side interconnect structure 160 can include three to six metallization layers. Each metallization layer includes conductive lines and contact vias embedded in intermetal dielectric (IMD) layers. The IMD layers can include, for example, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicate oxide, borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), silicon oxycarbide, and / or other suitable dielectric materials. The conductive lines and contact vias can include copper (Cu), titanium nitride (TiN), tungsten (W), or ruthenium (Ru). The interconnect structures functionally connect semiconductor devices, such as the transistors 200 in the IC chip 100. In some embodiments not explicitly shown in the figures, the front side interconnect structure 140 and / or the back side interconnect structure 160 can include active devices and passive devices. Examples of these active and passive devices can include, for example, metal-insulator-metal (MIM) capacitors, radio frequency (RF) antennas, deep trench capacitors, memory devices, or transistors.

[0076] In some embodiments, after forming the structure of the FEOL layer 150 on the substrate, for example Figure 1 As shown in the semiconductor wafer 10 in FIG. 1, the front side interconnect structure 140 is formed on the transistors 200. A bonding dielectric layer 130 is deposited on the front side interconnect structure 140. In some cases, the bonding dielectric layer 130 can include silicon oxide. Through the bonding dielectric layer 130, the front side interconnect structure 140, along with the FEOL layer 150 and the semiconductor wafer 10, is flipped and bonded to a handle wafer 120, which can include semiconductor material, sapphire, quartz, or glass. The handle wafer 120 is attached to the carrier disk 110 by electromagnetic force or vacuum suction. Before the back side interconnect structure 160 can be formed, the semiconductor wafer 10 is ground and polished to reduce its thickness from about 750 microns to about 800 microns to about 10 nanometers to about 100 nanometers. After the thickness is reduced, back side contacts are formed and the back side interconnect structure 160 is formed to connect to the transistors 200 through the back side contacts. The remaining semiconductor wafer 10 can be considered as part of the FEOL layer 150 in FIG. 1. In some techniques, the semiconductor wafer 10 can act as a heat sink because the semiconductor material has good thermal conductivity and its volume is several orders of magnitude larger than the transistors 200. However, as shown in FIG. 1, the semiconductor wafer 10 is removed after the back side interconnect structure 160 is formed. Figure 2 Figure 2 ​As shown, when the element region 102 includes the front-side interconnect structure 140 and the back-side interconnect structure 160, more than 99.9% of the semiconductor wafer 10 can be removed. The volume of the semiconductor wafer 10 is also greatly reduced. In addition, heat conduction from the FEOL layer 150 is impeded by several dielectric layers that can contain silicon oxide. Because the thermal conductivity of silicon oxide is more than two orders of magnitude smaller than that of silicon, heat dissipation from the transistors 200 in the element region 102 can be challenging.

[0077] The encapsulation ring 104 not only exists in the FEOL layer 150, but also in the front-side interconnect structure 140 and the back-side interconnect structure 160. As shown, Figure 2 As shown, the encapsulation ring 104 includes a through-substrate contact structure 104D in the FEOL layer 150, a front-side encapsulation ring wall 104F in the front-side interconnect structure 140, and a back-side encapsulation ring wall 104B in the back-side interconnect structure 160. The through-substrate contact structure 104D can include multiple stacks, including a back-side contact via, an epitaxial feature on the back-side contact via, an epitaxial contact feature on the epitaxial feature, and a contact via on the epitaxial contact feature. Except for the epitaxial feature, the back-side contact via, the epitaxial contact feature, and the contact via can contain rhodium (Ru), copper (Cu), nickel (Ni), cobalt (Co), titanium nitride (TiN), or tungsten (W). The front-side encapsulation ring wall 104F includes a metallization layer that is vertically aligned with the contact via. Like the front-side encapsulation ring wall 104F, the back-side encapsulation ring wall 104B also includes a metallization layer that is vertically aligned with the contact via. Although Figure 2 While a single front-side encapsulation ring wall and a single back-side encapsulation ring wall are shown, both the front-side encapsulation ring wall 104F and the back-side encapsulation ring wall 104B can contain multiple ring walls. In some embodiments, the front-side encapsulation ring wall 104F and the back-side encapsulation ring wall 104B can contain copper (Cu), nickel (Ni), cobalt (Co), or titanium nitride (TiN).

[0078] The present disclosure relates to the structure of the encapsulation ring 104 that dissipates the heat generated by the element region 102. While the purpose of the encapsulation ring 104 is to prevent fog from entering and to prevent pressure from damaging the element region, the encapsulation ring 104 contains a fairly large metal structure. As shown, Figure 2 As shown, the front-side encapsulation ring wall 104F is electrically coupled to the back-side encapsulation ring wall 104B through the through-substrate contact structure 104D to form an electrically conductive enclosure of the element region 102. Because the thermal conductivity is proportional to the electrical conductivity in all materials, the electrically conductive encapsulation ring 104 can also act as a good thermal conductor.

[0079] Figure 3According to one or more aspects of the present disclosure, a heat dissipation structure is described. It has been observed that when transistor 200 is a GAA device, heat is most likely to accumulate in the vertically stacked gate structure surrounding the channel member. Furthermore, the gate structure is most susceptible to excessive heat, which can cause threshold voltage shifts. For these reasons, a gate contact via connected to the gate structure is an effective way to dissipate unwanted heat. Through the coupling of a first metal line to the gate contact via, the first contact via, and the first contact, the gate contact via is thermally and electrically coupled to the first doped region of lateral diode 300. The second doped region of lateral diode 300 is thermally and electrically coupled to seal ring 104 via the second contact, the second contact via, the second metal line, the connecting via, and the third metal line 360. Third metal line 360 ​​extends laterally across a spacing S between device region 102 and seal ring 104. Spacing S is used for buffering and is selected to allow for wave-like heat conduction. When spacing S is too small, heat waves propagating from device region 102 to seal ring 104 may bounce back too quickly, resulting in inefficient heat dissipation from device region 102. In some embodiments, the first doped region is doped with an n-type dopant and the second doped region is doped with a p-type dopant. The lateral diode 300 functionally acts as a filter. The lateral diode 300 allows heat to pass through to the seal ring 104, but prevents the seal ring 104 from electrically coupling with the gate structure. As will be explained further below, the gate structures of the plurality of transistors 200 are thermally coupled to the seal ring 104. Without the lateral diode 300, the gate structures of all of these transistors 200 would be shorted together and have the same potential. To better illustrate the structure and connections, Figure 3 The dotted part of the Figure 4 Shown in.

[0080] Now refer to Figure 4 . The transistor 200 may be a transistor in a standard cell that includes multiple transistors. In the embodiment shown, the transistor 200 has a GAA structure. A plurality of channel members 2080 are stacked vertically on the doped substrate portion 202. The plurality of channel members 2080 and the doped substrate portion 202 extend along the X direction between the two source / drain features 210. The gate structure 214 surrounds each channel member 2080 and contacts the top surface of the doped substrate portion 202. The gate structure 214 is separated from the two source / drain features 210 by a plurality of inner spacer features 212. The plurality of inner spacer features 212 are staggered between the plurality of channel members 2080 along the Z direction. The first source / drain contact 224 and the second source / drain contact 226 are respectively disposed on the two source / drain features 210 and electrically connected thereto. The top of the gate structure 214 is linearly aligned with the top gate spacer 216. As shown Figure 4As shown, the gate structure 214 is laterally separated from the first source / drain contact 224 and the second source / drain contact 226 by a top gate spacer 216. The first source / drain contact 224 and the second source / drain contact 226 are connected to the source / drain feature 210 through a contact etch stop layer (CESL) 220 and a first interlayer dielectric layer (ILD) 222. In some embodiments, the first source / drain contact 224 and the second source / drain contact 226 are connected to the source / drain feature 210 through a second interlayer dielectric layer (ILD) 223. In some embodiments, the first source / drain contact 224 and the second source / drain contact 226 are connected to the source / drain feature 210 through a third interlayer dielectric layer (ILD) 224. Figure 4 In the embodiment shown, the transistor 200 is disposed on the backside dielectric layer 152. The backside dielectric layer 152 can include silicon oxide or silicon nitride.

[0081] In certain embodiments, the plurality of channel members 2080 includes silicon (Si). The plurality of channel members 2080 is disposed on a doped substrate portion 202 formed from a bulk semiconductor substrate. In certain embodiments, the bulk semiconductor substrate can be a silicon (Si) substrate. In other embodiments, the bulk semiconductor substrate includes an elemental semiconductor, such as germanium (Ge); a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); an alloy semiconductor, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP); or a combination thereof. In certain embodiments, the bulk semiconductor substrate includes one or more Group III-V materials, one or more Group II-VI materials, or a combination thereof. In certain cases, the bulk semiconductor substrate is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GeOI) substrate. In certain embodiments, the bulk semiconductor substrate can be a diamond substrate or a sapphire substrate. The doped substrate portion 202 can include an n-type dopant, such as phosphorus (P) or arsenic (As), or a p-type dopant, such as boron (B). When doped with an n-type dopant, the doped substrate portion 202 can be referred to as an n-well. When doped with a p-type dopant, the doped substrate portion 202 can be referred to as a p-well. The doped substrate portion 202 has a different conductivity than the transistor 200 disposed thereon. When the transistor 200 is an n-type transistor, the doped substrate portion 202 is a p-well. When the transistor 200 is a p-type transistor, the doped substrate portion 202 is an n-well.

[0082] The gate structure 214 includes a gate dielectric layer and a gate electrode layer on the gate dielectric layer. In certain embodiments, the gate dielectric layer includes an interface layer to contact the channel member 2080 and a high-k gate dielectric layer on the interface layer. As described herein, a high-k dielectric material includes a dielectric material having a high dielectric constant, e.g., greater than the dielectric constant of thermal oxide silicon (~3.9). The interface layer can include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-k gate dielectric layer can include hafnium oxide. Alternatively, the high-k gate dielectric layer can include other high-k dielectric materials such as titanium dioxide (Ti02), hafnium zirconium oxide (HfZrO), tantalum pentoxide (Ta205), hafnium silicon oxide (HfSi04), zirconium dioxide (Zr02), zirconium silicon oxide (ZrSi02), lanthanum trioxide (La203), aluminum trioxide (Al203), zirconium dioxide (ZrO), yttrium trioxide (Y203), strontium titanate (SrTi03) (STO), barium titanate (BaTi03) (BTO), barium zirconate (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), barium strontium titanate ((Ba,Sr)Ti03) (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The high-k gate dielectric layer can be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods.

[0083] The gate electrode layer can include a single layer or a multi-layer structure such as various combinations of metal layers (work function metal layers) selected to have a particular work function to enhance element performance, underlayer, wetting layer, adhesion layer, metal alloy, or metal silicide. For example, the gate electrode layer can include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metal materials, or combinations thereof. In various embodiments, the gate electrode layer can be formed using atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), e-beam evaporation, or other suitable processes.

[0084] The source / drain feature 210 can include silicon (Si) doped with n-type dopants, such as phosphorus (P) or arsenic (As), or silicon germanium (SiGe) doped with p-type dopants, such as boron (B) or boron difluoride (BF2). In the depicted embodiment, Figure 4 The transistor 200 in FIG. 1 is an n-type transistor, and the source / drain feature 210 includes silicon (Si) and n-type dopants. The inner spacer feature 212 separates the gate structure 214 from the source / drain feature 210, and can include silicon nitride, silicon oxycarbonitride, silicon oxynitride, or silicon oxycarbide. The top gate spacer 216 defines a gate trench in a gate replacement process, and can include silicon nitride, silicon oxycarbonitride, silicon oxynitride, or silicon oxycarbide. The first source / drain contact 224 and the second source / drain contact 226 can include a barrier layer, a silicide layer, and a metal fill layer disposed on the silicide layer. The barrier layer can include titanium nitride or tantalum nitride, and is used to prevent electromigration in the metal fill layer. The silicide layer can include titanium silicide, tantalum silicide, cobalt silicide, nickel silicide, or tungsten silicide. The silicide layer is disposed on an interface between the metal fill layer and the source / drain feature 210 to reduce contact resistance. The metal fill layer can include ruthenium (Ru), copper (Cu), nickel (Ni), cobalt (Co), or tungsten (W). The contact etch stop layer (CESL) 220 can include silicon nitride or silicon oxynitride. The first ILD layer 222 can include silicon oxide.

[0085] Figure 4 A lateral diode 300 is also shown configured on the backside dielectric layer 152. The lateral diode 300 includes an active region that includes a vertical stack 207 of a first semiconductor layer 208 and a second semiconductor layer 206, with the latter interleaved with the former. The stack 207 is configured on the doped substrate portion 202. In certain embodiments, the first semiconductor layer 208 includes silicon (Si) and the second semiconductor layer 206 includes silicon germanium (SiGe). The lateral diode 300 also includes a dummy gate structure 314 configured between two portions of a top gate spacer 316. Unlike the gate structure 214 of the transistor 200, the dummy gate structure 314 is configured on a top surface of the stack without encircling any of the first semiconductor layer 208, as the first semiconductor layer 208 in the lateral diode 300 is never released to form a suspended channel member. Further, unlike the gate structure 214, the dummy gate structure 314 is not electrically connected to any conductive structure, and remains electrically floating. Figure 4The lateral diode 300 in FIG. 1 includes a first doped region 310 and a second doped region 312, which extend perpendicularly and partially into the stack 207 but are spaced apart from each other in the X direction. The first doped region 310 and the second doped region 312 contain different types of dopants and have different conductivity types. In the illustrated embodiment, the first doped region 310 is doped with an n-type dopant, such as phosphorus (P) or arsenic (As), and is an n-type doped region. The second doped region 312 is doped with a p-type dopant, such as boron (B), and is a p-type doped region. In the illustrated embodiment, the n-type first doped region 310 and the p-type second doped region 312 form a pn junction diode. The n-type first doped region 310 acts as a cathode, and the p-type second doped region 312 acts as an anode. The region below the dummy gate structure 314, disposed between the n-type first doped region 310 and the p-type second doped region 312 in the X direction, serves as a depletion region 311 of the lateral diode 300.

[0086] The lateral diode 300 also includes a first contact 324 disposed in and electrically connected to the first doped region 310, and a second contact 326 disposed in and electrically connected to the second doped region 312. The first contact 324 and the second contact 326 may include a barrier layer, a silicide layer, and a metal filling layer disposed on the silicide layer. The barrier layer may include titanium nitride or tantalum nitride and is used to prevent electromigration in the metal filling layer. The silicide layer may include titanium silicide, tantalum silicide, cobalt silicide, nickel silicide, or tungsten silicide. The silicide layer is disposed at the interface between the metal filling layer and the first doped region 310 or the second doped region 312 to reduce contact resistance. The metal filling layer may include ruthenium (Ru), copper (Cu), nickel (Ni), cobalt (Co), or tungsten (W). As Figure 4 As shown, the dummy gate structure 314 is laterally separated from the first and second contacts 324 and 326 by a top gate spacer 316. In some embodiments, the top gate spacer 216 of the transistor 200 and the top gate spacer 316 of the lateral diode 300 may have similar dimensions and composition. The first and second contacts 324 and 326 extend through the contact etch stop layer (CESL) 220 and the first interlayer dielectric (ILD) 222 to connect to the first and second doped regions 310 and 312, respectively. The transistor 200 and the lateral diode 300 are separated along the X direction by an isolation structure 204, which may be a shallow trench isolation (STI) feature. The isolation structure 204 may include silicon oxide, tetraethoxysilane (TEOS) oxide, undoped silicate glass, doped silicon oxide, borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), silicon oxycarbide, and / or other suitable dielectric materials.

[0087] ReferenceFigure 4 Due to a planarization process, such as a chemical mechanical polishing (CMP) process, top surfaces of the first source / drain contact 224, the gate structure 214, the top gate spacer 216, the second source / drain contact 226, the first contact 324, the dummy gate structure 314, the top gate spacer 316, the second contact 326, the CESL 220, and the first ILD layer 222 are substantially coplanar. An etch stop layer (ESL) 228 is disposed on top surfaces of the first source / drain contact 224, the gate structure 214, the top gate spacer 216, the second source / drain contact 226, the first contact 324, the dummy gate structure 314, the top gate spacer 316, the second contact 326, the CESL 220, and the first ILD layer 222. A second ILD layer 230 is disposed on the ESL 228. In some embodiments, the ESL 228 may include silicon nitride or silicon oxynitride. The second ILD layer 230 may have the same composition as the first ILD layer 222. A gate contact via 234 penetrates the second ILD layer 230 and the ESL 228 to contact the gate structure 214. A first contact via 334 penetrates the second ILD layer 230 and the ESL 228 to contact the first contact 324. A second contact via 336 penetrates the second ILD layer 230 and the ESL 228 to contact the second contact 326. The gate contact via 234, the first contact via 334, and the second contact via 336 may include a barrier layer and a metal fill layer disposed on the barrier layer. The barrier layer may include titanium nitride or tantalum nitride and is used to prevent electromigration in the metal fill layer. The metal fill layer may include ruthenium (Ru), copper (Cu), nickel (Ni), cobalt (Co), or tungsten (W).

[0088] Still refer to Figure 4 The third ILD layer 232 is disposed above the second ILD layer 230. The third ILD layer 232 may share the same composition as the first ILD layer 222. Figure 4In the explicitly shown embodiment, another etch stop layer can be disposed between the second ILD layer 230 and the third ILD layer 232. The first metal line 236 and the second metal line 346 are disposed in the third ILD layer 232. The first metal line 236 is in direct contact with the top surface of the gate contact via 234 and the first contact via 334, thereby electrically connecting them. The second metal line 346 is in direct contact with the top surface of the second contact via 336. In some embodiments, the second metal line 346 can be island-like. In some other embodiments, the second metal line 346 can extend along the Y direction to connect to multiple contact vias, just like the second contact via, which connects to a doped region similar to the second doped region 312. The connection via 348 is disposed above and in contact with the second metal line 346. The first metal line 236, the second metal line 346, and the connection via 348 can include a barrier layer and a metal fill layer on the barrier layer. The barrier layer can include titanium nitride or tantalum nitride, and functions to prevent electromigration in the metal fill layer. The metal fill layer can include copper (Cu), nickel (Ni), cobalt (Co), or tungsten (W). The third metal line 360 is disposed above the third ILD layer 232 and in contact with the top surface of the connection via 348. The first metal line 236, the second metal line 346, the third metal line 360, and the connection via 348 can include a barrier layer and a metal fill layer on the barrier layer. The barrier layer can include titanium nitride or tantalum nitride, and functions to prevent electromigration in the metal fill layer. The metal fill layer can include copper (Cu), nickel (Ni), cobalt (Co), or tungsten (W). In one embodiment, the metal fill layer in the first metal line 236, the second metal line 346, the third metal line 360, and the connection via 348 includes copper (Cu).

[0089] The conductive features in the metallization layers in the interconnect structure, such as the front-side interconnect structure 140, in the metallization layers farther away from the FEOL structure are larger in size than the conductive features in the metallization layers closer to the FEOL structure. Figure 4 In the explicitly shown embodiment, the third metal line 360 is farther away from the transistor 200 than the first metal line 236 and the second metal line 346. That is, the cross-sectional area of the third metal line 360 is much larger than the first metal line 236 or the second metal line 346. The larger cross-sectional area of the third metal line 360 allows better heat conduction from the device region 102. As shown in FIG. 1, the third metal line 360 is in contact with the connection via 348, which is in contact with the second metal line 346, which is in contact with the first metal line 236, which is in contact with the gate contact via 234, which is in contact with the gate electrode 214, which is in contact with the substrate 202. Thus, the third metal line 360 is in contact with the substrate 202 through the connection via 348, the second metal line 346, the first metal line 236, the gate contact via 234, the gate electrode 214, and the substrate 202. Figure 3 and Figure 4As shown, the third metal line 360 spans a pitch S to connect to the front side enclosure wall 104F of the enclosure 104. In certain embodiments, the pitch S is between 100 microns and about 200 microns. This range is not trivial. When the pitch S is less than 100 microns, thermal waves bouncing back from the enclosure 104 can interfere with thermal waves going out from the device region 102. When the pitch S is greater than 200 microns, the size of the IC chip can be unnecessarily enlarged. In some other embodiments not explicitly shown in the figures, further connection vias can be disposed above the third metal line 360 and used to connect to further metal lines above the third metal line 360. These further metal lines can also span the pitch S to connect to different regions of the enclosure 104.

[0090] In Figure 4 In the illustrated embodiment, both the first doped region 310 and the second doped region 312 are formed by ion implantation. As Figure 4 As shown, the first doped region 310 and the second doped region 312 can not extend all the way to the doped substrate portion 202. In some cases, they can not even extend to the bottommost second semiconductor layer 206. By forming the first doped region 310 and the second doped region 312 using ion implantation, the p-n junction transition can be more abrupt, and the performance of the lateral diode 300 can be improved. In Figure 5 In some alternative embodiments illustrated, the first doped region 310 is replaced by a first epitaxial feature 310E, and the second doped region 312 is replaced by a second epitaxial feature 312E. The first epitaxial feature 310E and the second epitaxial feature 312E are not formed by ion implantation. Instead, a recess is formed along the top gate spacer 316 to extend to the stack 207, and a separate epitaxial deposition process is performed to form the first epitaxial feature 310E and the second epitaxial feature 312E. In the illustrated embodiment, the first epitaxial feature 310E includes silicon (Si) and an n-type dopant, such as phosphorus (P) or arsenic (As); and the second epitaxial feature 312E includes silicon germanium (SiGe) and a p-type dopant, such as boron (B).

[0091] Reference is now made to Figure 4 and Figure 5 The gate contact via 234 can draw heat away from the gate structure 214 of the transistor 200. The heat of the gate contact via 234 can then be conducted to the first metal line 236, the first contact via 334, the first contact 324, the first doped region 310 (or the first epitaxial feature 310E in Figure 5 ), the depletion region 311 under the dummy gate structure 314, the second doped region 312 (or the second epitaxial feature 312E in Figure 5second contact 326, second contact via 336, second metal line 346, connection via 348, third metal line 360, and finally to the seal ring 104. As described above, while heat can propagate through conduction in the lateral diode 300, the lateral diode 300 prevents electrical coupling between the gate structure 214 and the seal ring 104. The first doped region 310, the second doped region 312, and the depletion region 311 are formed of a semiconductor material, such as silicon or silicon germanium. As described above, they have a thermal conductivity that is approximately two orders of magnitude greater than a dielectric material, such as silicon dioxide. They are part of the thermal conduction path for thermally coupling the gate structure 214 to the front seal ring wall 104F of the seal ring 104.

[0092] In very large scale integrated (VLSI) circuit design, multiple transistors can be combined together to form standard cells that perform different circuit functions. Figure 6 An example configuration is shown that effectively conducts heat from the element region 102 to the seal ring 104 that surrounds the element region 102. The elements in the element region 102 can have a diode region 3000, a standard cell region 2000, and a memory region 4000, where the standard cell region 2000 is between the diode region 3000 and the memory region 4000. In some embodiments, the diode region 3000 can include a lateral diode 300 similar to the lateral diode 300 shown in FIG. 3. The standard cell region 2000 can include a plurality of standard cells that include transistors 200 that are functionally connected together. The memory region 4000 can include memory cells or macros. In some embodiments, the memory region 4000 includes static random access memory (SRAM) cells. Figure 4 and Figure 5 The standard cell region 2000 can include a plurality of standard cells that include transistors 200 that are functionally connected together. The memory region 4000 can include memory cells or macros. In some embodiments, the memory region 4000 includes static random access memory (SRAM) cells.

[0093] In one illustrative aspect, the disclosure pertains to an integrated circuit (IC) chip. The IC chip includes an element region, an interconnect structure disposed above the element region, and a seal ring surrounding the element region and the interconnect structure. The element region includes a transistor having a gate structure. The seal ring includes a metal structure. The gate structure is thermally coupled to the metal structure through a diode.

[0094] In certain embodiments, the distance between the transistor and the seal ring is between about 100 microns and about 200 microns. In certain embodiments, the transistor further includes a plurality of channel members extending between the source feature and the drain feature. The gate structure surrounds each of the channel members. The gate structure is separated from the source feature and the drain feature by a plurality of inner spacer features. In certain embodiments, the diode includes a well region, a stack disposed above the well region and including a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers, a first doped region and a second doped region in the stack, a first contact electrically coupled with the first doped region, and a second contact electrically coupled with the second doped region. In certain cases, the well region includes silicon and a p-type dopant. In certain embodiments, the gate structure is electrically coupled with the first doped region, and the metal structure is electrically coupled with the second doped region. In certain embodiments, the first doped region includes a first type of dopant, and the second doped region includes a second type of dopant different from the first type of dopant. In certain embodiments, the first type of dopant is an n-type dopant, and the second type of dopant is a p-type dopant. In certain embodiments, the IC chip further includes a gate contact via disposed on the gate structure, a first contact via disposed on the first contact, a second contact via disposed on the second contact, a first metal line disposed on the gate contact via and the first contact via, a second metal line disposed on the second contact via, a connection via disposed on the second metal line, and a third metal line disposed on the connection via. The third metal line is physically coupled with the metal structure of the seal ring.

[0095] In another example aspect, the disclosure relates to an element structure. The element structure includes a backside dielectric layer; a transistor including a first well region disposed on the backside dielectric layer, a plurality of nanostructures disposed one on top of another on the first well region, and a gate structure wrapped around each of the nanostructures; a diode including a second well region disposed on the backside dielectric layer, a stack above the second well region and including a plurality of silicon layers interleaved with a plurality of silicon germanium layers, a first doped region and a second doped region in the stack and separated by a depletion region, and a floating gate structure on the depletion region; and a seal ring metal structure spaced a distance from the transistor. The gate structure is electrically coupled with the first doped region. The second doped region is electrically coupled with the seal ring metal structure.

[0096] In some embodiments, the first well region and the second well region include p-type dopants. In some embodiments, the first doped region includes n-type dopants and the second doped region includes p-type dopants. In some cases, the distance is between about 100 microns and about 200 microns. In some embodiments, the gate structure is electrically coupled to the first doped region through a gate contact via on the gate structure, a first contact on the first doped region, a first contact via on the first contact, and a first metal line on the gate contact via and the first contact via. In some embodiments, the second doped region is electrically coupled to the seal ring metal structure through a second contact on the second doped region, a second contact via on the second contact, a second metal line on the second contact via, a connection via on the second metal line, and a third metal line on the connection via. In some embodiments, the floating gate structure is electrically floating.

[0097] In another exemplary aspect, the disclosure is directed to a device structure. The device structure includes a transistor including a plurality of nanostructures and a gate structure wrapped around each of the plurality of nanostructures; a diode including a stack having a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers and a first doped region and a second doped region in the stack; and a seal ring metal structure spaced apart from the transistor by a distance. The gate structure is electrically coupled to the first doped region. The second doped region is electrically coupled to the seal ring metal structure.

[0098] In some embodiments, the plurality of nanostructures includes silicon, the plurality of first semiconductor layers includes silicon, and the plurality of second semiconductor layers includes silicon germanium. In some embodiments, the first doped region includes n-type dopants and the second doped region includes p-type dopants. In some cases, the distance is between about 100 microns and about 200 microns.

[0099] The foregoing summary is not intended to define every implementation that is considered the disclosure. Definitions can be found in the disclosure incorporated herein by reference in their entirety. Other aspects and advantages of the disclosure will become more readily apparent to those having ordinary skill in the art upon review of the following detailed description.

Claims

1. An integrated circuit chip, characterized in that: include: Component area; an interconnection structure, disposed above the component area; as well as a sealing ring surrounding the component area and the interconnection structure, wherein the element region includes a transistor having a gate structure, The sealing ring comprises a metal structure, The gate structure is thermally coupled to the metal structure through a diode.

2. The integrated circuit chip according to claim 1, wherein: The distance between the transistor and the sealing ring is between 100 microns and 200 microns.

3. The integrated circuit chip according to claim 1, wherein: wherein the transistor further comprises a plurality of channel members extending between the source feature and the drain feature, wherein the gate structure surrounds each of the plurality of channel members, The gate structure is separated from the source feature and the drain feature by a plurality of inner spacer features.

4. The integrated circuit chip according to claim 1, wherein: The diode comprises: Well area; A stack, disposed above the well region, and comprising a plurality of first semiconductor layers alternating with a plurality of second semiconductor layers; a first doped region and a second doped region disposed in the stack; a first contact electrically coupled to the first doped region; and A second contact is electrically coupled to the second doped region.

5. The integrated circuit chip according to claim 4, wherein: The gate structure is electrically coupled to the first doping region, and the metal structure is electrically coupled to the second doping region.

6. An electronic component structure, characterized in that: include: a backside dielectric layer; Transistors, including: A first well region is disposed on the back dielectric layer; a plurality of nanostructures disposed one above the other above the first well; and a gate structure wrapping around each of the plurality of nanostructures; Diodes, including: A second well region is provided on the back dielectric layer. A stack, disposed above the second well region, and comprising a plurality of silicon layers alternating with a plurality of silicon germanium layers; a first doped region and a second doped region located in the stack and separated by a depletion region; and a floating gate structure disposed above the depletion region; and The sealing ring metal structure is spaced a distance from the transistor. wherein the gate structure is electrically coupled to the first doped region, The second doped region is electrically coupled to the sealing ring metal structure.

7. The electronic component structure according to claim 6, characterized in that The gate structure is electrically coupled to the first doped region through a gate contact through hole disposed on the gate structure, a first contact disposed on the first doped region, a first contact through hole disposed on the first contact, and a first metal line disposed on the gate contact through hole and the first contact through hole.

8. The electronic component structure according to claim 7, wherein: The second doped region is electrically coupled to the seal ring metal structure through a second contact disposed on the second doped region, a second contact through hole disposed on the second contact, a second metal line disposed on the second contact through hole, a connecting through hole disposed on the second metal line, and a third metal line disposed on the connecting through hole.

9. The electronic component structure according to claim 6, wherein: The floating gate structure is electrically floating.

10. An electronic component structure, characterized in that: include: Transistors, including: a plurality of nanostructures; and a gate structure wrapping around each of the plurality of nanostructures; Diodes, including: a stack comprising a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers; and A first doped region and a second doped region are disposed in the stack; and The sealing ring metal structure is spaced a distance from the transistor. wherein the gate structure is electrically coupled to the first doped region, The second doped region is electrically coupled to the sealing ring metal structure.

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