Bias chip embedded circuit board

Abstract

The utility model relates to the technical field of automobile parts, and provides a bias-type chip embedded circuit board, which comprises a core board. The chip packaging unit is embedded in the core plate, the chip packaging unit comprises a conductive substrate and a chip unit embedded in the conductive substrate, the chip unit is arranged on one side of the conductive substrate in a bias mode, and an electrode leading-out area of the chip unit is reserved on the other side of the conductive substrate; the prepreg and the conductive layer are stacked on the core plate; and the outgoing line is led out from the front surface of the chip packaging unit and is arranged in the prepreg and the conductive layer. According to the utility model, the chip unit is biased at one side of the conductive substrate, and an electrode leading-out area of the chip unit is reserved at the other side of the conductive substrate, so that when the biased chip embedded circuit board is formed, leading-out wires of all electrodes of the chip unit can be led out from the front surface of the chip packaging unit, and wiring is facilitated.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of automobile parts, and concretely relates to a bias type chip embedded circuit board. BACKGROUND

[0002] In the automobile parts such as inverter, the chip packaging structure used more is the chip embedded packaging structure, that is, embedding the chip in the busbar. Among them, the chip structure used, the gate and the source are located on the front, and the drain is usually located on the back, and the drain needs to be realized through the busbar.

[0003] And the current design, embedding the chip in the busbar, the remaining area on the front of the busbar is not much, and it is not convenient to lead out the drain, and the drain of the chip needs to be led out from the back of the busbar. In the automobile parts such as inverter, the drain of a chip needs to be connected with the source of another chip, and the source is led out from the front and the drain is led out from the back, which causes inconvenience in wiring.

[0004] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the utility model, and therefore can include information that does not constitute prior art known to those skilled in the art. CONTENT OF THE UTILITY MODEL

[0005] Therefore, the utility model provides a bias type chip embedded circuit board, which offsets the chip unit on one side of the conductive substrate and leaves the electrode lead-out area of the chip unit on the other side of the conductive substrate, so that when the bias type chip embedded circuit board is formed, the lead-out wires of each electrode of the chip unit can be led out from the front of the chip packaging unit, which is convenient for wiring.

[0006] According to one aspect of the utility model, a bias type chip embedded circuit board is provided, comprising: a core plate; a chip packaging unit embedded in the core plate, the chip packaging unit comprising a conductive substrate and a chip unit embedded in the conductive substrate, wherein the chip unit is offset on one side of the conductive substrate, and the other side of the conductive substrate leaves the electrode lead-out area of the chip unit; a semi-cured sheet and a conductive layer stacked on the core plate; a lead-out wire led out from the front of the chip packaging unit and arranged in the semi-cured sheet and the conductive layer.

[0007] In some embodiments, the gate lead-out area, the source lead-out area and the drain lead-out area of the chip unit are all distributed on the front of the chip packaging unit; the lead-out wire comprises a gate lead-out wire connected with the gate lead-out area, a source lead-out wire connected with the source lead-out area and a drain lead-out wire connected with the drain lead-out area.

[0008] In some embodiments, the gate and the source of the chip unit are located on the front surface of the chip unit, and the drain of the chip unit is located on the back surface of the chip unit; the electrode lead-out area reserved on the conductive substrate is the drain lead-out area, and the gate lead-out area and the source lead-out area are located on the chip unit.

[0009] In some embodiments, the effective area of the drain lead-out area is adapted to the effective area of the source lead-out area.

[0010] In some embodiments, the source lead-out line and the drain lead-out line are arranged in a grid shape.

[0011] In some embodiments, the bias type chip embedded circuit board further comprises: a pad arranged on the conductive layer and electrically connected with the lead-out line.

[0012] In some embodiments, the entire upper surface of the bias type chip embedded circuit board forms a driving circuit arrangement area.

[0013] In some embodiments, the chip packaging unit is a power module of an inverter; a plurality of chip units are embedded in the core plate, wherein the drain lead-out line of the chip unit of the upper bridge arm is connected with the positive electrode of the power supply, the source lead-out line of the chip unit of the lower bridge arm is connected with the negative electrode of the power supply, the source lead-out line of the chip unit of the upper bridge arm is connected with the drain lead-out line of the chip unit of the lower bridge arm and connected with the winding of the motor, and the gate lead-out line of the chip unit of the upper bridge arm and the drain lead-out line of the chip unit of the lower bridge arm are connected with the driving circuit arranged on the upper surface of the embedded circuit board.

[0014] The beneficial effects of the present application compared with the prior art at least include:

[0015] The chip unit is biased on one side of the conductive substrate, and the electrode lead-out area of the chip unit is reserved on the other side of the conductive substrate, so that when the bias type chip embedded circuit board is formed, the lead-out lines of the electrodes of the chip unit can be led out from the front surface of the chip packaging unit, facilitating the arrangement of the lead-out lines and the wiring between the lead-out lines.

[0016] In addition, the chip packaging unit is embedded in the core plate of the circuit board and laminated on the bottom of the circuit board, which can use the semi-cured sheet and conductive layer of the circuit board as the insulating layer and the conductor layer of the lead-out line arrangement, and reserve a driving circuit arrangement area on the upper surface of the circuit board, thereby providing space for the arrangement of the driving circuit, so that the bias type chip embedded circuit board formed has a compact overall structure, stable performance, and a significant reduction in material cost.

[0017] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments conforming to the present invention and, together with the description, serve to explain the principles of the present invention. It is obvious that the drawings described below are merely some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0019] Figure 1 This diagram shows a cross-sectional view of the bias-type chip embedded circuit board in an embodiment of the present invention.

[0020] Figure 2 A three-dimensional structural schematic diagram of the chip packaging unit in an embodiment of this utility model is shown;

[0021] Figure 3 This diagram shows an exploded view of the chip packaging unit in an embodiment of the present invention. Detailed Implementation

[0022] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to those described herein. Rather, these embodiments are provided to make the present invention more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0023] The accompanying drawings are merely illustrative of the present invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore, repeated descriptions of them will be omitted.

[0024] The terms "first," "second," and similar words used in the specific description do not indicate any order, quantity, or importance, but are merely used to distinguish different components. The terms "upper," "lower," "front," "back," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. The term "multiple" means two or more, unless otherwise explicitly specified. Furthermore, in the description of the present invention, when it is said that a device is "connected" to another device, this includes not only direct connection but also indirect connection through other elements.

[0025] It should be noted that, unless otherwise specified, the embodiments of this utility model and the features in different embodiments can be combined with each other.

[0026] Figure 1 schematically show a sectional structure of the offset chip embedded circuit board, Figure 2 schematically show a three-dimensional structure of the chip packaging unit, Figure 3 schematically show an exploded structure of the chip packaging unit in the embodiment of the utility model, and Figures 1 to 3 schematically show, the offset chip embedded circuit board provided by the embodiment of the utility model, comprising:

[0027] a core plate 10;

[0028] a chip packaging unit 20 embedded in the core plate 10, the chip packaging unit 20 comprising a conductive substrate 21 and a chip unit 22 embedded in the conductive substrate 21, wherein the chip unit 22 is offset on one side of the conductive substrate 21, and the other side of the conductive substrate 21 is reserved for an electrode leading-out area 22' of the chip unit 22;

[0029] a prepreg 30 and a conductive layer 40 stacked on the core plate 10;

[0030] a leading-out wire 50 leading out from the front of the chip packaging unit 20 and arranged in the prepreg 30 and the conductive layer 40.

[0031] The core plate (Core) 10 is the basic material of the circuit board, comprising a middle layer of plate material with a certain hardness and thickness and double-sided copper foil cladding. The prepreg (Prepreg) 30 is a kind of semi-solid material, which plays a role of adhesion and insulation. The conductive layer 40 is a metal layer such as copper layer.

[0032] The utility model offsets the chip unit 22 on one side of the conductive substrate 21, and reserves the other side of the conductive substrate 21 for the electrode leading-out area 22' of the chip unit 22, so that when the offset chip embedded circuit board is formed, the leading-out wire 50 of each electrode of the chip unit 22 can be led out from the front of the chip packaging unit 20, facilitating the arrangement of the leading-out wire 50 and the wiring between the leading-out wires 50.

[0033] In addition, the utility model embeds the chip packaging unit 20 in the core plate 10 of the circuit board and laminates it at the bottom of the circuit board, can use the structures such as prepreg 30 and conductive layer 40 of the circuit board as the insulating layer and the wire layer for the arrangement of the leading-out wire 50, and reserves a driving circuit arrangement area on the upper surface of the circuit board, which provides space for the arrangement of the driving circuit, makes the overall structure of the formed offset chip embedded circuit board compact, stable in performance, and greatly reduces the cost of consumables.

[0034] In some embodiments, the gate lead-out area 22a, the source lead-out area 22b and the drain lead-out area 22c of the chip unit 22 are all distributed on the front surface of the chip packaging unit 20; the lead-out lines 50 include a gate lead-out line (not specifically shown in the figure) connected to the gate lead-out area 22a, a source lead-out line 50b connected to the source lead-out area 22b and a drain lead-out line 50c connected to the drain lead-out area 22c.

[0035] In this way, the wiring of the electrodes of the chip unit 22 is facilitated, and all the lead-out lines 50 are led out from the front surface of the chip packaging unit 20, which on the one hand simplifies the wiring process without the need to be wound from the back surface, and on the other hand, after the chip packaging unit 20 is embedded in the core board 10, the prepreg 30 and the conductive layer 40 are also stacked on the core board 10, and the arrangement of the lead-out lines 50 can utilize the prepreg 30 and the conductive layer 40 of the circuit board as the insulating layer and the conductive layer, without the need to additionally provide a functional film layer, thereby improving the compactness of the bias-type chip embedded circuit board, improving the cost-effectiveness, and avoiding the problems caused by the downward flow of the drain current, reducing the parasitic magnetic resistance and improving the EMC performance.

[0036] In some embodiments, the gate and the source of the chip unit 22 are located on the front surface of the chip unit 22, and the drain of the chip unit 22 is located on the back surface of the chip unit 22; the electrode lead-out area 22' reserved on the conductive substrate 21 is the drain lead-out area 22c, and the gate lead-out area 22a and the source lead-out area 22b are located on the chip unit 22.

[0037] In the present embodiment, the drain of the chip unit 22 is located on the back surface of the chip unit 22; in order to facilitate the lead-out of the drain, the drain lead-out area 22c is reserved on the conductive substrate 21. In other embodiments, according to different chip designs, the positions of the gate / source / drain of the chip unit 22 can be different; in the case that the area of the gate / source / drain of the chip unit 22 is too small to be conveniently led out, or the gate / source / drain is distributed on the front and back surfaces of the chip unit 22 and is not convenient for wiring, etc., the scheme of the present application can be used, i.e., the chip unit 22 is biased on one side of the conductive substrate 21, and the electrode lead-out area 22' of the chip unit 22 is reserved on the other side of the conductive substrate 21, so that the lead-out lines 50 of the electrodes of the chip unit 22 can all be led out from the front surface of the chip packaging unit 20 when the circuit board is manufactured, facilitating the arrangement of the lead-out lines 50 and the wiring between the lead-out lines 50.

[0038] In some embodiments, the effective area of the drain lead-out area 22c is adapted to the effective area of the source lead-out area 22b.

[0039] The effective area refers to an area that can be used for wiring, for example, an area excluding the edge portion. The effective areas are adapted to each other, and can be equal or approximately equal. The effective area of the drain lead-out region 22c is adapted to the effective area of the source lead-out region 22b, facilitating wiring between the source and the drain of the chip unit 22.

[0040] In some embodiments, the source lead-out line 50b and the drain lead-out line 50c are arranged in a grid shape.

[0041] The grid-shaped source lead-out line 50b and the drain lead-out line 50c can carry a large current, and can improve circuit load sharing, relieve thermal expansion, and improve stability in application scenarios such as inverters.

[0042] In some embodiments, the bias type chip embedded circuit board further comprises a pad 60 disposed on the conductive layer 40 and electrically connected to the lead-out line 50. Through the pad 60, the lead-out line 50 is electrically connected to the driving circuit arranged on the upper surface of the bias type chip embedded circuit board.

[0043] In some embodiments, the entire upper surface of the bias type chip embedded circuit board forms a driving circuit arrangement area. Specifically, a film layer structure such as a shielding layer / insulating buffer layer can be arranged on the pad 60, and then the driving circuit is arranged and electrically connected to the pad 60. The chip packaging unit 20 is embedded in the circuit board, leaving a driving circuit arrangement area on the upper surface of the circuit board, providing space for the arrangement of the driving circuit, making the overall structure of the bias type chip embedded circuit board compact and stable in performance.

[0044] In some embodiments, the chip packaging unit 20 is a power module of an inverter; a plurality of chip units 22 are embedded in the core board 10, wherein the drain lead-out line 50c of the chip unit 22 of the upper bridge arm is connected to the positive electrode of the power supply, the source lead-out line 50b of the chip unit 22 of the lower bridge arm is connected to the negative electrode of the power supply, the source lead-out line 50b of the chip unit 22 of the upper bridge arm is connected to the drain lead-out line 50c of the chip unit 22 of the lower bridge arm and connected to the winding of the motor, and the gate lead-out line of the chip unit 22 of the upper bridge arm and the drain lead-out line of the chip unit of the lower bridge arm are connected to the driving circuit arranged on the upper surface of the bias type chip embedded circuit board.

[0045] Further, as shown in Figures 1 to 3 The manufacturing process of the bias type chip embedded circuit board provided by the above-mentioned embodiments of the present application includes:

[0046] A slot hole 100 is formed in the core board 10.

[0047] The chip packaging unit 20 is embedded in the slot hole, wherein the chip packaging unit 20 comprises a conductive substrate 21 and a chip unit 22 embedded in the conductive substrate 21, and the chip unit 22 is offset on one side of the conductive substrate 21, and the other side of the conductive substrate 21 is reserved as an electrode leading-out area 22' of the chip packaging unit 20.

[0048] The chip unit 22 is offset on one side of the conductive substrate 21, and the other side of the conductive substrate 21 is reserved as the electrode leading-out area 22' of the chip unit 22, so that when the offset-type chip embedded circuit board is formed, the leading-out wires 50 of each electrode of the chip unit 22 can be led out from the front surface of the chip packaging unit 20, facilitating the arrangement of the leading-out wires 50 and the wiring between the leading-out wires 50.

[0049] The conductive layer 40 and the prepreg 30 are stacked on the core plate 10, and the conductive layer 40 and the prepreg 30 are perforated to form a via hole penetrating through the conductive layer 40 and the prepreg 30 and connecting the leading-out areas of the electrodes of the chip unit 22.

[0050] The via hole can be realized by laser perforation.

[0051] The via hole is filled with a conductive material to form the leading-out wires 50 led out from the front surface of the chip packaging unit 20 and arranged in the prepreg 30 and the conductive layer 40.

[0052] The chip packaging unit 20 is embedded in the core plate 10 of the circuit board and laminated at the bottom of the circuit board, the prepreg 30 and the conductive layer 40 of the circuit board and other structures can be used as an insulating layer and a conductive layer for the arrangement of the leading-out wires 50, and a driving circuit arrangement area is reserved on the upper surface of the circuit board to provide space for the arrangement of the driving circuit, so that the overall structure of the formed offset-type chip embedded circuit board is compact, stable in performance, and the cost of consumables is greatly reduced.

[0053] Further, in some embodiments, the prepreg 30 and the conductive layer 40 comprise a plurality of groups stacked alternately; the conductive layer 40 and the prepreg 30 are stacked on the core plate 10, and the conductive layer 40 and the prepreg 30 are perforated, comprising:

[0054] The conductive layer 40 and the prepreg 30 of the first group are stacked on the core plate 10, and the conductive layer 40 and the prepreg 30 of the first group are perforated to form a first via hole penetrating through the conductive layer 40 and the prepreg 30 of the first group and connecting the leading-out areas of the electrodes of the chip unit 22;

[0055] The second group of prepreg 30 and conductive layer 40 are stacked on the core board 10, and the second group of conductive layer 40 and prepreg 30 are punched to form a second via hole penetrating the second group of conductive layer 40 and prepreg 30 and communicating with the lead-out area of each electrode of the chip unit 22 through the first via hole.

[0056] In addition, the manufacturing process can further include arranging a pad 60 electrically connected with the lead-out wire 50 on the conductive layer 40, arranging a driving circuit on the upper surface of the offset chip embedded circuit board, etc., which can refer to the above description of each offset chip embedded circuit board embodiment, and will not be repeated here.

[0057] The above is a further detailed description of the present application in combination with specific preferred embodiments, and cannot be considered as limiting the specific implementation of the present application to these descriptions. For ordinary skilled persons in the technical field to which the present application belongs, some simple deductions or substitutions can be made without departing from the concept of the present application, and all of them shall be considered as falling within the protection scope of the present application.

Claims

1. A biased chip-in-board circuit board, characterized by, The chip embedding type circuit board comprises: a core plate; a chip packaging unit embedded in the core plate, the chip packaging unit comprising a conductive substrate and a chip unit embedded in the conductive substrate, wherein the chip unit is offset on one side of the conductive substrate, and the other side of the conductive substrate is reserved for an electrode leading-out area of the chip unit; a prepreg and a conductive layer laminated on the core plate; a leading-out wire leading out from the front surface of the chip packaging unit and arranged in the prepreg and the conductive layer.

2. The biased chip-in-board circuit board of claim 1, wherein, The gate leading-out area, the source leading-out area and the drain leading-out area of the chip unit are all distributed on the front surface of the chip packaging unit. The leading-out wire comprises a gate leading-out wire connected to the gate leading-out area, a source leading-out wire connected to the source leading-out area and a drain leading-out wire connected to the drain leading-out area.

3. The biased chip-in-board circuit board of claim 2, wherein, The gate and the source of the chip unit are located on the front surface of the chip unit, and the drain of the chip unit is located on the back surface of the chip unit. The electrode leading-out area reserved on the conductive substrate is the drain leading-out area, and the gate leading-out area and the source leading-out area are located on the chip unit.

4. The biased chip-in-board circuit board of claim 3, wherein, The effective area of the drain leading-out area is adapted to the effective area of the source leading-out area.

5. The biased chip-in-board circuit board of claim 2, wherein, The source leading-out wire and the drain leading-out wire are both arranged in a grid shape.

6. The biased chip-in-board circuit board of claim 1, wherein, Further comprising: a solder pad arranged on the conductive layer and electrically connected to the leading-out wire.

7. The biased chip-in-board circuit board of claim 1, wherein, The entire upper surface of the chip embedding type circuit board forms a driving circuit arrangement area.

8. The bias chip-in-board circuit board of any one of claims 1-7, wherein, The chip packaging unit is a power module of an inverter. A plurality of chip units are embedded in the core plate, wherein the drain leading-out wire of the chip unit of the upper bridge arm is connected to a positive electrode of a power supply, the source leading-out wire of the chip unit of the lower bridge arm is connected to a negative electrode of the power supply, the source leading-out wire of the chip unit of the upper bridge arm is connected to the drain leading-out wire of the chip unit of the lower bridge arm and connected to a winding of a motor, and the gate leading-out wire of the chip unit of the upper bridge arm and the drain leading-out wire of the chip unit of the lower bridge arm are connected to a driving circuit arranged on the upper surface of the embedded circuit board.

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