Package assembly

Abstract

The embodiment of the utility model relates to a semiconductor packaging piece, which comprises a photon structure, an encapsulation layer and a laser write-in waveguide structure. The photonic structure is disposed on the interposer structure. The encapsulation layer is located at a side edge of the photonic structure. A laser write waveguide structure is embedded in the glass substrate and disposed adjacent to the photonic structure, wherein the laser write waveguide structure has a plurality of curved waveguide paths.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a package assembly. BACKGROUND

[0002] In recent years, the semiconductor industry has experienced rapid growth. This growth stems from continuous advances in semiconductor integrated circuitry, which are used in a variety of electronic devices. In order to keep abreast of consumer demand for smaller electronic devices, semiconductor manufacturers are continually seeking to increase the integration density of semiconductor devices. Increasing integration density, in turn, has resulted in efforts to reduce the size and increase the performance of integrated circuitry. Although existing integrated circuit packages or package assemblies are generally suitable for their intended purposes, they have not been entirely satisfactory in all respects. SUMMARY

[0003] According to some embodiments of the present application, a package assembly includes a photonic structure, an encapsulation layer, and a laser-written waveguide structure. The photonic structure is disposed on an interposer structure. The encapsulation layer is disposed on a side of the photonic structure. The laser-written waveguide structure is embedded in a glass substrate and disposed adjacent to the photonic structure, wherein the laser-written waveguide structure has a plurality of curved waveguide paths.

[0004] According to some embodiments of the present application, a package assembly includes a photonic structure, a laser-written waveguide structure, and a fiber array unit. The photonic structure is disposed on an interposer structure. The laser-written waveguide structure is embedded in a glass substrate and disposed adjacent to the photonic structure, wherein the laser-written waveguide structure has a plurality of waveguide paths. The fiber array unit is disposed laterally adjacent to the laser-written waveguide structure, wherein the fiber array unit includes a plurality of optical fibers corresponding to the plurality of waveguide paths. In some embodiments, the plurality of waveguide paths have different profiles as viewed in a cross-sectional view. BRIEF DESCRIPTION OF DRAWINGS

[0005] The application embodiments will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It is to be noted, however, that the application embodiments are not limited to the specific embodiments disclosed, but include any and all embodiments which come within the scope of the claims. In addition, it should be noted that, wherever possible, any component of any embodiment can be used in any other embodiment in the application.

[0006] Figures 1 to 5 is a schematic cross-sectional view of a method of forming a package assembly according to some embodiments;

[0007] Figure 6 、 Figure 7 and Figure 9 is a schematic partial perspective view of a package assembly according to some embodiments;

[0008] Figure 8 and Figure 10 is a schematic partial cross-sectional view of a package assembly according to some embodiments; is a schematic cross-sectional view of a method of forming a package assembly according to some embodiments;

[0009] Figures 11 to 16 is a schematic cross-sectional view of a method of forming a package assembly according to some embodiments;

[0010] Figures 17 to 18 is a schematic partial cross-sectional view of a package assembly according to some embodiments;

[0011] Figure 19 shows a method of forming a package assembly according to some embodiments;

[0012] Figure 20 shows a method of forming a package assembly according to some embodiments. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the provided subject matter. For purposes of explanation, specific examples of components and arrangements are described herein. Of course, various embodiments can have additional components or different configurations and arrangements, and some embodiments can be devoid of certain components or configurations described herein. In some instances, well-known structures, techniques, materials, or components have not been described in detail in order to avoid obscuring the intended subject matter. It is important to note that the various embodiments presented herein are not necessarily mutually exclusive, as some embodiments can be adapted to incorporate features of other embodiments to form new embodiments. Additionally, the various embodiments can be used in combination or in parallel to form further embodiments. It will be apparent to one of ordinary skill in the art that embodiments of the present disclosure and / or equivalents thereof can include additional components or steps, can combine certain components or steps, and / or can leave out certain components or steps, without departing from the scope of the present disclosure.

[0014] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the provided subject matter. For purposes of explanation, specific examples of components and arrangements are described herein. Of course, various embodiments can have additional components or different configurations and arrangements, and some embodiments can be devoid of certain components or configurations described herein. In some instances, well-known structures, techniques, materials, or components have not been described in detail in order to avoid obscuring the intended subject matter. It is important to note that the various embodiments presented herein are not necessarily mutually exclusive, as some embodiments can be adapted to incorporate features of other embodiments to form new embodiments. Additionally, the various embodiments can be used in combination or in parallel to form further embodiments. It will be apparent to one of ordinary skill in the art that embodiments of the present disclosure and / or equivalents thereof can include additional components or steps, can combine certain components or steps, and / or can leave out certain components or steps, without departing from the scope of the present disclosure.

[0015] Furthermore, spatially relative terms, such as "under", "below", "lower", "over", "upper", "atop", "on", "down", and "up", can be used herein for ease of reading only. Unless otherwise specified, a spatially relative term refers to the orientation of one component with respect to another component as illustrated in the drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation, for example, orientation of the device relative to gravity- or a horizontal plane, as well as the different orientations of the device in structurally different versions of the device. Thus, the spatially relative terms can be interpreted differently depending on the specific context of use or operation.

[0016] Embodiments described herein disclose a package assembly such as an optoelectronic integrated circuit (IC) package. With the three-dimensional (3D) laser-written waveguide structure of the present disclosure, the misalignment problem between a fiber array unit (FAU) and a photonic structure can be easily solved, and the coupling tolerance between the FAU and the photonic structure can be greatly improved. With the optical interconnect provided by the photonic structure, higher communication performance and more compact packaging can be easily achieved.

[0017] Figures 1 to 5 is a schematic cross-sectional view of a method of forming a package assembly according to some embodiments. It should be understood that the present disclosure is not limited to the method described below. Additional operations can be provided before, during, and / or after the method, and some operations described below can be replaced or eliminated, in additional embodiments of the method. Although the method is described below as a series of operations, it should be understood that the method can include additional operations, and / or the operations can be performed in a different order. Figures 1 to 5 is described in relation to a method, it should be understood that Figures 1 to 5 The structures disclosed in are not limited to such a method, but can exist independently of the method as a structure.

[0018] Referring to Figure 1 At least one semiconductor package PK is attached to a wafer tape T. In some embodiments, the semiconductor package PK includes an interposer structure 100, and an integrated circuit structure 200 and a photonic structure 300 bonded to the interposer structure 100. The integrated circuit structure 200 can include a system device, and the photonic structure 300 can include a photonic device, as will be described in more detail below. However, embodiments of the present disclosure are not limited thereto. In other embodiments, the semiconductor package PK also includes an additional integrated circuit structure bonded to the interposer structure 100 and in addition to the integrated circuit structure 200. The additional integrated circuit structure can include, for example, a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a memory device such as a high bandwidth memory (HBM) cube, or the like.

[0019] In some embodiments, the interposer structure 100 includes a substrate 102 and a substrate via 104 that extends through the substrate 102. The substrate 102 can include an elemental semiconductor of silicon, germanium, and / or a compound semiconductor of silicon germanium, silicon carbide, gallium arsenide, indium arsenide, gallium nitride, or indium phosphide. The substrate via 104 can include a metal such as copper and is insulated from the substrate 102 by an insulating liner. In some embodiments, the interposer structure 100 further includes a conductive structure disposed between the substrate 102 and the integrated circuit structure 200 or the photonic structure 300 and electrically connected to the substrate via 104. The conductive structure can include a conductive feature embedded by a dielectric layer.

[0020] In some embodiments, the interposer structure 100 further includes a metal pad 106 and a metal pad 108 on opposite sides that are configured to be electrically connected to an overlying and underlying electronic device, semiconductor device, or integrated circuit structure, respectively. In some embodiments, bumps B1 and B2 are also formed on and electrically connected to the metal pad 106 and the metal pad 108, respectively. For different overlying electrical structures, the bumps B1 can be divided into bumps B11 and B12. The bumps B1 and B2 include solder bumps, and / or can include metal pillars (e.g., copper pillars), solder caps formed on the metal pillars, etc. In some examples, the bumps B1 are referred to as “micro bumps.” In some examples, the bumps B2 are referred to as “controlled collapse chip connection (C4) bumps.” The size of the bumps B2 can be different from (e.g., larger than) the size of the bumps B1.

[0021] In some embodiments, the interposer structure 100 is an active interposer that contains at least one functional device or integrated circuit device included in the conductive structure or substrate. In some examples, such an active interposer is referred to as a “device- containing interposer.” In some embodiments, the functional device includes an active device, a passive device, or a combination thereof. The functional device includes, for example, but is not limited to, a transistor, a capacitor, a resistor, a diode, a photodiode, a fuse device, and / or other similar devices. In other embodiments, the interposer structure 100 is a passive interposer that does not have a functional device or integrated circuit device. In some examples, such a passive interposer is referred to as a “device-free interposer.”

[0022] Still referring to Figure 1The integrated circuit structure 200 is coupled to the intermediate structure 100. The integrated circuit structure 200 may include system devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), central processing unit (CPU) chips, graphics processing unit (GPU) chips, multi-core general-purpose dedicated processors (xPUs), artificial intelligence (AI) engine chips, transceiver (TRX) chips, etc. In some embodiments, the integrated circuit structure 200 (e.g., a system device) includes a substrate 201 and a device layer 203. The substrate 201 may include elemental semiconductors of silicon and germanium and / or compound semiconductors of silicon-germanium, silicon carbide, gallium arsenide, indium arsenide, gallium nitride, or indium phosphide. The substrate 201 may be doped as needed. The device layer 203 may include transistors, such as fin field-effect transistors (FinFETs), nanostructured FETs (nanoFETs) (e.g., nanosheet transistors, nanowire transistors, or gate-around transistors), planar FETs, similar or combinations thereof. The device layer 203 may also include interconnect structures electrically connected to the transistors.

[0023] In some embodiments, the integrated circuit structure 200 (e.g., a system device) further includes a metal pad 204 configured to be electrically connected to an underlying electronic device, semiconductor device, or integrated circuit structure. Specifically, the integrated circuit structure 200 (e.g., a system device) is bonded to the interposer structure 100 via the metal pad 204, bump B11, and metal pad 106. The bump B11 may be formed on the metal pad 204, metal pad 106, or both.

[0024] Still referencing Figure 1 The photonic structure 300 is bonded to the intermediate structure 100. In some embodiments, the photonic structure 300 includes a photonic grain 302o, an electronic grain 302e, and a support grain 310 from bottom to top. In some examples, the photonic structure 300 may be referred to as a silicon photonic (SiPh) structure.

[0025] In some embodiments, the photonic die 302o includes a photonic integrated circuit (PIC) 303. The PIC 303 includes optical waveguides (e.g., silicon (Si) waveguides), modulators, detectors, grating couplers, filters, other optical components, or combinations thereof. In some embodiments, the photonic die 302o also includes at least one reflector Rl, at least one optical component 305, and a conductive feature 307 embedded in at least one dielectric layer 306. The reflector Rl is configured to reflect a light beam to a desired direction or a desired optical component. The optical component 305 is optically coupled to the PIC 303. In some embodiments, the optical component 305 includes an edge coupler (EC) and an optical waveguide, and the edge coupler is located between the reflector Rl and the optical waveguide. The optical waveguide included in the optical component 305 includes a silicon nitride (SiN) waveguide, a silicon carbide (SiC) waveguide, a silicon carbon nitride (SiCN) waveguide, etc. The optical waveguide material in the dielectric layer 306 is different from the optical waveguide material inside the PIC 303. The silicon nitride waveguide in the optical component 305 has a lower signal propagation loss than the silicon waveguide in the PIC 303, and is used to transmit optical signals over a relatively long distance. The conductive feature 307 of the photonic structure 300 is configured to be electrically connected to the underlying interposer structure 100. The reflector Rl and the conductive feature 307 can include a metal (e.g., copper) and can be formed by an electroplating process or a sputtering process. The dielectric layer 306 can include silicon oxide, silicon nitride, silicon oxynitride, etc., or combinations thereof, and can be formed by a deposition process.

[0026] In some embodiments, a method of forming the photonic die 302o can include providing a silicon-on-insulator (SOI) substrate, forming the PIC 303 on / in an active side (e.g., a front side) of a silicon layer of the SOI substrate, removing an oxide layer and a semiconductor layer of the SOI substrate, and forming the at least one optical component 305, the at least one reflector Rl, and the conductive feature 307 embedded in the at least one dielectric layer 306 on a non-active side (e.g., a back side) of the silicon layer.

[0027] In some embodiments, the electronic die 302e includes an electric integrated circuit (EIC). The PIC of the photonic die 302o is integrated with the EIC of the electronic die 302e to achieve higher communication performance and a more compact package. In some embodiments, the electronic die 302e is bonded to the photonic die 302o by hybrid bonding including die-to-die bonding and metal-to-metal bonding.

[0028] In some embodiments, the size (e.g., width) of the electronic die 302e is smaller than the size (e.g., width) of the photonic die 302o, and an insulating material 304 is provided on the sides of the electronic die 302e to fill the space and reinforce the structure. The insulating material 304 can include a dielectric material, a polymer material, or a combination thereof. The dielectric material can include silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination thereof, and can be formed by a deposition process. The polymer material can include polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a molding compound (e.g., an epoxy), and can be formed by a deposition process or a molding process.

[0029] In some embodiments, the support die 310 is a semiconductor die, such as a silicon die. The support die 310 can include an elemental semiconductor of silicon, germanium, and / or a compound semiconductor of silicon germanium, silicon carbide, gallium arsenide, indium arsenide, gallium nitride, or indium phosphide.

[0030] In some embodiments, the support die 310 includes at least one optical lens 311 and at least one optical lens 312 on opposite sides thereof. The optical lens 311 and the optical lens 312 can be aligned with each other. The optical lens 311 and the optical lens 312 can be embedded in the support die 310 and face each other. The optical lens 311 and the optical lens 312 are configured to converge a light beam on a desired cross-section, or focus a light beam in a desired direction. In some embodiments, each of the optical lens 311 and the optical lens 312 can have an optical recessed feature. In some embodiments, each of the optical lens 311 and the optical lens 312 has a substantially vertical sidewall and a convex bottom. The shape of the optical lens 311 can be symmetrical to the shape of the optical lens 312, and can be designed to have a desired curvature for focusing a light beam to an underlying optical component.

[0031] In some embodiments, a method of forming each of the optical lens 311 and the optical lens 312 includes performing an etching process or a laser process to form a recessed feature, and filling the recessed feature with an optical material or a transparent material. The optical material has a transmission percentage of about 80-99% (e.g., 85-95% or 88-92%). In some embodiments, the optical material includes an optical liquid silicone rubber, polymethyl methacrylate (PMMA), an optical epoxy, or the like, or a combination thereof. In some embodiments, the optical material includes a high numerical aperture (NA) material with a NA of about 0.2 to 0.5. In some embodiments, a dispensing, injection, and / or spraying process is used, followed by a planarization process to form the optical material.

[0032] In some embodiments, the support die 310 is bonded to the electronic die 302e by fusion bonding such as dielectric-to-dielectric bonding or polymer-to-polymer bonding. Specifically, the support die 310 is bonded to the electronic die 302e via a dielectric bonding layer 314, a dielectric bonding layer 309. The dielectric bonding layer 314 and the dielectric bonding layer 309 each include a dielectric layer such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or the like or a combination thereof. The dielectric layer can be replaced by a polymer layer or an insulating layer as desired.

[0033] In some embodiments, the photonic structure 300 (e.g., photonic device) further includes a metal pad 308 configured to be electrically connected to an underlying electronic component, semiconductor device, or integrated circuit structure. Specifically, the photonic structure 300 (e.g., photonic device) is bonded to the interposer structure 100 via the metal pad 308, the bump B12, and the metal pad 106. The bump B12 can be formed on the metal pad 308, the metal pad 106, or both.

[0034] Still referring to Figure 1 After the integrated circuit structure 200 and the photonic structure 300 are bonded to the interposer structure 100, an underfill layer UF1 is formed to fill the space between the interposer structure 100 and each of the integrated circuit structure 200 and the photonic structure 300, and around the bump B1 including the bumps B11 and B12. In some embodiments, the underfill layer UF1 includes a molding compound such as an epoxy, and is formed using a dispensing, injection, and / or spray coating process. The underfill layer UF1 between two adjacent structures can have a curved surface and a concave surface. In some examples, the underfill layer UF1 can be omitted.

[0035] Thereafter, an encapsulation layer E1 is formed over the interposer structure 100 and laterally around the integrated circuit structure 200 and the photonic structure 300. In some embodiments, the encapsulation layer E1 includes a molding, a molding underfill, a resin, or the like. In some embodiments, the encapsulation layer E1 includes a polymer material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like or a combination thereof. The encapsulation layer E1 can be formed by a molding process followed by a curing process.

[0036] In some embodiments, a wafer dicing process is performed to separate adjacent semiconductor packages PK from each other. Each semiconductor package PK can have a substantially vertical sidewall. In some embodiments, the semiconductor package PK includes the interposer structure 100, the integrated circuit structure 200 and the photonic structure 300 bonded to the interposer structure 100, and the encapsulation layer E1 laterally encapsulating the sidewalls of the integrated circuit structure 200 and the photonic structure 300.

[0037] Referring to Figure 1 andFigure 2 The wafer tape T is removed, a board substrate 700 is formed under the interposer structure 100 and electrically connected to the interposer structure 100. In some embodiments, the board substrate 700 is bonded to the interposer structure 100 by bumps B2.

[0038] In some embodiments, the board substrate 700 includes a core layer and two build-up layers on opposite sides of the core layer. In some embodiments, the board substrate 700 includes a wiring pattern 702 that penetrates the core layer and the build-up layers for providing electrical wiring between different devices and electronic components. The wiring pattern 702 includes lines, vias, pads, and / or connectors. In some examples, the board substrate 700 is referred to as a "printed circuit board (PCB)". In other embodiments, the core layer of the board substrate 700 can be omitted as needed, and such a board substrate 700 is referred to as a "coreless board substrate".

[0039] Thereafter, an underfill layer UF2 is formed to fill the space between the interposer structure 100 and the board substrate 700 and surround the bumps B2. In some embodiments, the underfill layer UF2 includes a molding compound such as epoxy, and is formed using a dispensing, injection, and / or spraying process.

[0040] In some embodiments, a support structure 800 is provided and bonded to the photonic structure 300 side edges of the semiconductor package PK on the board substrate 700. The support structure 800 is configured to support the overlying glass substrate, thus stiffening the final structure. In some embodiments, the support structure 800 is a wall structure on one side of the photonic structure 300, or a ring structure around the photonic structure 300. In this case, the support structure 800 includes a heat dissipation material, such as a metal. The support structure 800 is attached to the board substrate 700 by an adhesive layer 801. In some embodiments, the support structure 800 has a buffer layer 802 on its top. The buffer layer 802 can be an adhesive layer or a thermal interface material (TIM). However, the present embodiments are not limited thereto. In other embodiments, the support structure 800 can be a silicon dummy die for eliminating coefficient of thermal expansion (CTE) mismatch and thus reducing package warpage issues.

[0041] Then, bumps B3 are formed under the board substrate 700 and are electrically connected to the board substrate 700. In some embodiments, the bumps B3 are electrically connected to the wiring pattern 702 of the board substrate 700. In some embodiments, the bumps B3 include solder bumps, and / or can include metal pillars (e.g., copper pillars), solder caps formed on the metal pillars, etc. In some examples, the bumps B3 are referred to as “ball grid array (BGA) balls”. The size of the bumps B3 can be different from (e.g., larger than) the size of the bumps B2.

[0042] Referring to Figure 2 and Figure 6 the glass substrate 400 is assembled to a fiber array unit (FAU) 500. In some embodiments, as shown in FIG. 5, the glass substrate 400 has two guide holes GH, the FAU 500 has two guide pins GP, and the glass substrate 400 is assembled to the FAU 500 with the guide pins GP aligned with and inserted into the guide holes GH. The glass substrate 400 is not laser-written with a pattern at this stage. In some embodiments, the glass substrate 400 has a width of about 5 mm to 7 mm, a length of about 15 mm to 20 mm, and a height of about 1 mm to 3 mm. Other values and ranges can also apply depending on customer requirements. Figure 6 In some embodiments, the glass substrate 400 includes a glass base 401 and has at least one optical coupler 412 and at least one reflector R2 embedded in at least one dielectric layer 410 under the glass base 401. The optical coupler 412 is configured to condition a light beam emitted from a light source. In some embodiments, the optical coupler 412 is an evanescent coupler (EVC). The reflector R2 is configured to reflect the light beam to a desired direction or a desired optical component. The reflector R2 can include metal (e.g., copper) and can be formed by an electroplating process or a sputtering process. The dielectric layer 410 can include silicon oxide, silicon nitride, silicon oxynitride, etc., or a combination thereof, and can be formed by a deposition process.

[0043] Still referring to

[0044] and Figure 2 , the FAU 500 includes optical fibers 506 arranged in an array. In some embodiments, each optical fiber 506 includes a glass core 502 and a glass cladding 504 surrounding the glass core 502. In some embodiments, a portion of the optical fibers 506 are embedded in a ferrule 508, and a remaining portion of the optical fibers 506 are embedded in a fiber ribbon 510. Figure 6 ​

[0045] Referring to Figure 3 The glass substrate 400 with the fiber array unit 500 is bonded to the photonic structure 300. Specifically, the reflector R2 of the glass substrate 400 faces the lower optical lens 312 of the photonic structure 300, and optical glue GL is dispensed into the space between the glass substrate 400 and the photonic structure 300, and then a curing process is performed. The optical glue GL contains a curable adhesive material and has high light transmittance and high adhesion. The optical glue GL can have a convex surface and extend from the sidewall of the glass body 401. In some embodiments, the dielectric layer 410 of the glass substrate 400 is in physical contact with the optical glue GL and abuts against the buffer layer 802 on the support structure 800.

[0046] Referring to Figure 4 and Figure 7 A laser writing process LP is performed on the glass substrate 400 to form laser written waveguide structures 406 inside the glass substrate 400. In some examples, the laser writing process LP can be referred to as a three-dimensional (3D) laser writing process. In some embodiments, the laser writing process LP is performed by a laser writing module including at least one laser light source and a plurality of mirrors. In some embodiments, when an engineer inputs a program to the laser writing module using a computer, the positions of the plurality of mirrors can be adjusted to appropriate positions according to the program. At least one laser beam emitted from the laser light source is reflected by the adjusted mirrors and thus writes the glass substrate to form a desired waveguide path. Specifically, the X and Y positions of the waveguide path can be controlled by adjusting the mirrors. Meanwhile, a platform for supporting the glass substrate can be adjusted vertically to adjust the Z position of the waveguide path. In some embodiments, a plurality of waveguide paths are sequentially written in the glass substrate, but the present disclosure is not limited thereto. In other embodiments, a plurality of waveguide paths are simultaneously written in the glass substrate. In some embodiments, the laser writing process LP also forms at least one laser lens 402 between the fiber array unit 500 and the laser written waveguide structures 406. The laser lens 402 is configured to concentrate a light beam in a desired cross-section or focus the light beam in a desired direction. Specifically, a plurality of laser lenses 402 are respectively disposed between and in contact with a plurality of waveguide paths 406P and a plurality of optical fibers 506, as shown in Figure 7 In some examples, the plurality of laser lenses 402 can be omitted, and the plurality of waveguide paths 406P are respectively in contact with the plurality of optical fibers 506. Since the waveguide structures 406 of the present disclosure are formed by a laser writing process, the waveguide paths 406P are written to have a curved path to better match the optical fibers 506 and the optical couplers 412 at both ends of each waveguide path 406P. Specifically, as shown in Figure 8As shown in the cross-sectional view, each curved waveguide path 406P has two horizontal sub-paths P1 and P3 to better match the corresponding optical evanescent coupler (EVC) 412 and optical fiber 506, and a curved and smooth middle sub-path P2 connecting the two horizontal sub-paths P1 and P3. The connection points between each horizontal sub-path and middle sub-path are rounded. The horizontal sub-path P1 overlaps with the optical evanescent coupler (EVC) 412 for better optical coupling. As shown in Figure 7 The plurality of laser-written waveguide paths 406P correspond to the plurality of laser lenses 402 and thus the plurality of optical fibers 506, respectively.

[0047] In Figure 7 some embodiments, one row of laser lenses 402, one row of waveguide paths 406P, and one row of optical fibers 506 are provided for illustration. Figure 8 A schematic cross-sectional view is shown in Figure 7 However, the embodiments of the present application are not limited thereto. In some embodiments, two or more rows of laser lenses 402, two or more rows of waveguide paths 406P, and two or more rows of optical fibers 506 can be designed as needed, as shown in Figure 9 Figure 10 A schematic cross-sectional view is shown in Figure 9

[0048] Referring to Figure 5 , after the laser writing process LP, an adaptor case 600 is provided to fix the glass substrate 400 and the FAU 500 together. Thus, the packaging assembly 10 of the present application is completed. In some embodiments, a cover can be provided above the glass substrate 400 for protecting the underlying components and reinforcing the entire packaging assembly 10, and optical glue is dispensed into the space between the cover and the glass substrate 400, followed by a curing process. The cover can be a heat dissipation cover or a glass cover.

[0049] In some embodiments, as shown in Figure 5 the light beam L propagates through the optical fiber 506, travels through the laser lens 402 and the laser-written waveguide structure 406, and is optically coupled to the optical coupler 412, is redirected by the reflector R2, and then is optically coupled to the PIC 303 in sequence through the optical lens 312, the optical lens 311, the reflector R1, the edge coupler, and the silicon nitride waveguide of the optical assembly 305.

[0050] ​​In the above embodiments, the laser writing process is performed after the glass substrate is bonded to the top surface of the photonic crystal die to form the waveguide structure. However, embodiments of the present application are not limited thereto. In other embodiments, the laser writing process can be performed on the glass substrate first to form the waveguide structure, and then the glass substrate with the waveguide structure written thereon is bonded to the photonic structure. In this case, the glass substrate with the waveguide structure written thereon is adjusted to the proper position before the glass substrate is bonded to the photonic structure. In this case, after the bonding process, optical glue is dispensed between the glass substrate and the photonic structure, and then a buffer layer is provided between the support structure and the glass substrate to stabilize the glass substrate, thereby stabilizing the entire package assembly.

[0051] With the three-dimensional (3D) laser-written waveguide structure of the present application, the misalignment problem between the fiber array unit (FAU) and the optical evanescent coupler (EVC) of the photonic structure can be easily solved, and the coupling tolerance between the fiber array unit (FAU) and the optical evanescent coupler (EVC) can be greatly reduced. Specifically, when the fiber array unit (FAU) and the optical evanescent coupler (EVC) are misaligned, the waveguide paths of the waveguide structure of the present application can be written to the proper position by the laser writing process, thereby better matching the optical evanescent coupler (EVC) and the optical fiber located at both ends of each waveguide path, thereby solving the misalignment problem.

[0052] In the above embodiments, the glass substrate with the laser-written waveguide is vertically stacked on top of the photonic structure. However, embodiments of the present application are not limited thereto. In other embodiments, the glass substrate with the laser-written waveguide can be laterally disposed on the side of the photonic structure as needed.

[0053] Figures 11 to 16 is a schematic cross-sectional view of a method of forming a package assembly according to some embodiments. It should be understood that embodiments of the present application are not limited to the method described below. Additional operations can be provided before, during, and / or after this method, and some operations described below can be replaced or eliminated, although Figures 11 to 16 is described in relation to a method, it should be understood that Figures 11 to 16 The structures disclosed in

[0054] Throughout this document, identical or similar reference numerals and / or letters can be used to refer to identical or similar components, members, structures and / or elements in various examples of the present application, and therefore Figures 11 to 11 the materials, configurations and / or methods of forming the components in Figure 16 may refer to the descriptions in the above embodiments.

[0055] Reference is made to Figure 11At least one semiconductor package PK1 is attached to a wafer strip T. In some embodiments, the semiconductor package PK1 includes an interposer structure 100, and an integrated circuit structure 200 and a photonic structure 301 bonded to the interposer structure 100.

[0056] In some embodiments, the integrated circuit structure 200 may include a system device, and the photonic structure 301 may include a photonic device, as will be described in detail below. However, the embodiments of the present invention are not limited thereto. In other embodiments, the semiconductor package PK1 further includes an additional integrated circuit structure bonded to the interposer structure 100 and other than the integrated circuit structure 200. The additional integrated circuit structure may include a memory device such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), or a chip stack such as a high bandwidth memory (HBM) cube.

[0057] In some embodiments, the intermediary structure 100 includes a substrate 102 and a substrate via 104 penetrating the substrate 102. In some embodiments, the intermediary structure 100 also includes metal pads 106 and 108 located on opposite sides, configured to be electrically connected to an upper and lower electronic device, semiconductor device, or integrated circuit structure, respectively. In some embodiments, bumps B1 and B2 are also formed on and electrically connected to metal pads 106 and 108, respectively. For different overlay electronic structures, bump B1 may be divided into bump B11 and bump B12. The size of bump B2 may be different from (e.g., larger than) the size of bump B1. In some embodiments, the intermediary structure 100 is an active intermediary. In other embodiments, the intermediary structure 100 is a passive intermediary.

[0058] like Figure 11 As shown, the integrated circuit structure 200 is bonded to the interposer structure 100. In some embodiments, the integrated circuit structure 200 (e.g., a system device) includes a substrate 201 and a device layer 203. The device layer 203 may also include interconnect structures electrically connected to transistors. In some embodiments, the integrated circuit structure 200 (e.g., a system device) is bonded to the interposer structure 100 via a metal pad 204, a bump B11, and a metal pad 106. The bump B11 may be formed on the metal pad 204, the metal pad 106, or both.

[0059] Still referencing Figure 11 The photonic structure 301 is bonded to the intermediate structure 100. In some embodiments, the photonic structure 301 includes a photonic grain 302o, an electronic grain 302e, and a support grain 310 from bottom to top. In some examples, the photonic structure 301 may be referred to as a silicon photonic (SiPh) structure.

[0060] In some embodiments, the photonic die 302o includes a photonic integrated circuit (PIC) 303. The PIC 303 includes optical waveguides (e.g., silicon (Si) waveguides), modulators, detectors, grating couplers, edge couplers, filters, other optical components, or combinations thereof. In some embodiments, the photonic die 302o also includes conductive features 307 embedded in the at least one dielectric layer 306. The conductive features 307 of the photonic structure 301 are electrically connected to the underlying interposer structure 100.

[0061] In some embodiments, a method of forming the photonic die 302o can include providing a silicon-on-insulator (SOI) substrate, forming the PIC 303 on / in an active side (e.g., front side) of a silicon layer of the SOI substrate, removing an oxide layer and a semiconductor layer of the SOI substrate, and forming the conductive features 307 embedded in the at least one dielectric layer 306 on a non-active side (e.g., backside) of the silicon layer.

[0062] In some embodiments, the electronic die 302e includes an electronic integrated circuit (EIC). The PIC of the photonic die 302o is integrated with the EIC of the electronic die 302e to achieve higher communication performance and more compact packaging. In some embodiments, the electronic die 302e is bonded to the photonic die 302o by hybrid bonding including dielectric-to-dielectric bonding and metal-to-metal bonding.

[0063] In some embodiments, the electronic die 302e has a smaller size (e.g., width) than the photonic die 302o, and an insulating material 304 is provided on the side edges of the electronic die 302e to fill the space and reinforce the structure.

[0064] In some embodiments, the support die 310 is a semiconductor die, such as a silicon die. In some embodiments, the support die 310 is bonded to the electronic die 302e via a dielectric bonding layer 314 and the dielectric bonding layer 309.

[0065] In some embodiments, the photonic structure 301 (e.g., photonic device) is bonded to the interposer structure 100 through the metal pad 308, the bump B12, and the metal pad 106. The bump B12 can be formed on the metal pad 308, the metal pad 106, or both.

[0066] Still referring to Figure 11 After the integrated circuit structure 200 and the photonic structure 301 are bonded to the interposer structure 100, an underfill layer UF1 is formed to fill the space between the interposer structure 100 and each of the integrated circuit structure 200 and the photonic structure 301, and around the bump B1 including the bumps B11 and B12.

[0067] Thereafter, an encapsulation layer E1 is formed over the interposer structure 100 and laterally surrounds the integrated circuit structure 200 and the photonic structure 301.

[0068] In some embodiments, a wafer dicing process is performed to separate the adjacent semiconductor packages PK1 from each other. Each semiconductor package PK1 can have substantially vertical sidewalls. In some embodiments, the semiconductor package PK1 includes the interposer structure 100, the integrated circuit structure 200 and the photonic structure 301 bonded to the interposer structure 100, and the encapsulation layer E1 laterally encapsulating sidewalls of the integrated circuit structure 200 while exposing sidewalls of the photonic structure 301. In some embodiments, the exposed sidewalls of the photonic structure 301 are flush with the sidewalls of the underlying underfill layer UF1 and the sidewalls of the interposer structure 100. The exposed sidewalls of the photonic structure 301 are used for optical coupling to a subsequently formed laser-written waveguide structure, which will be described in detail below.

[0069] Referring to Figure 11 and Figure 12 , the wafer tape T is removed, forming a board substrate 700 underneath and electrically connected to the interposer structure 100. In some embodiments, the board substrate 700 is bonded to the interposer structure 100 through the bumps B2.

[0070] In some embodiments, the board substrate 700 includes a core layer and two build-up layers on opposite sides of the core layer. In some embodiments, the board substrate 700 includes a wiring pattern 702 that penetrates the core layer and the build-up layers, for providing electrical wiring between different devices and electronic components. In some examples, the board substrate 700 is referred to as a “printed circuit board (PCB)”. In other embodiments, the core layer of the board substrate 700 can be omitted as needed, and such a board substrate 700 is referred to as a “coreless board substrate”.

[0071] Thereafter, an underfill layer UF2 is formed to fill the space between the interposer structure 100 and the board substrate 700, and to surround the bumps B2.

[0072] In some embodiments, a support structure 800 is provided and bonded to the board substrate 700 on the side of the photonic structure 301 of the semiconductor package PK1. The support structure 800 is configured to support the overlying glass substrate, thus stiffening the final structure. In some embodiments, the support structure 800 is a wall structure on a single side of the photonic structure 301, or a ring structure surrounding the photonic structure 301. In such cases, the support structure 800 comprises a heat spreading material, such as a metal. The support structure 800 is attached to the board substrate 700 by an adhesive layer 801. In some embodiments, the support structure 800 has a buffer layer 802 on its top. The buffer layer 802 can be an adhesive layer or a thermal interface material (TIM). However, embodiments of the present application are not limited thereto. In other embodiments, the support structure 800 can be a silicon dummy die, used to eliminate coefficient of thermal expansion (CTE) mismatch and thus reduce package warpage issues.

[0073] Then, bumps B3 are formed under the board substrate 700, and the bumps B3 are electrically connected to the board substrate 700. In some embodiments, the bumps B3 are electrically connected to the wiring pattern 702 of the board substrate 700. The size of the bumps B3 can be different from (e.g., larger than) the size of the bumps B2.

[0074] Referring to Figure 12 and Figure 6 the glass substrate 400 is assembled to a fiber array unit (FAU) 500. In some embodiments, as shown in Figure 6 , the glass substrate 400 has two guide holes GH, the FAU 500 has two guide pins GP, and the glass substrate 400 is assembled to the FAU 500 with the guide pins GP aligned with and inserted into the guide holes GH. The glass substrate 400 is not laser-written with a pattern at this stage.

[0075] Still referring to Figure 12 and Figure 6 , the FAU 500 includes optical fibers 506 arranged in an array. In some embodiments, each optical fiber 506 includes a glass core 502 and a glass cladding layer 504 surrounding the glass core 502. In some embodiments, portions of the optical fibers 506 are embedded in ferrules 508, and remaining portions of the optical fibers 506 are embedded in a fiber ribbon 510.

[0076] Referring to Figure 13The glass substrate 400 with the fiber array unit 500 is bonded to the photonic structure 301. Specifically, the glass substrate 400 faces the exposed sidewalls of the photonic structure 301, and optical glue GL1 is applied in the space between the glass substrate 400 and the photonic structure 301, and then a curing process is performed. The optical glue GL1 contains a curable adhesive material and has high light transmittance and high adhesion. The optical glue GL1 can have a convex surface and extend from the sidewalls of the glass substrate 400. In some embodiments, the glass substrate 400 abuts against the buffer layer 802 on the support structure 800.

[0077] Referring to Figure 14 and Figure 7 A laser writing process LP is performed on the glass substrate 400 to form laser-written waveguide structures 406 inside the glass substrate 400. In some examples, the laser writing process LP can be referred to as a three-dimensional (3D) laser writing process. In some embodiments, the laser writing process LP also forms at least one laser lens 402 between the fiber array unit 500 and the laser-written waveguide structures 406. The laser lens 402 is configured to concentrate a light beam in a desired cross-section or focus the light beam in a desired direction. Specifically, a plurality of laser lenses 402 are respectively arranged between and in contact with a plurality of waveguide paths 406P and a plurality of optical fibers 506, as shown in Figure 7 In some examples, the plurality of laser lenses 402 can be omitted, and the plurality of waveguide paths 406P are respectively in contact with the plurality of optical fibers 506. Since the waveguide structures 406 of the present application are formed by a laser writing process, the waveguide paths 406P are written to have curved paths to better match the optical fibers 506 and edge couplers (ECs) of the PIC 303 at both ends of each waveguide path 406P. Specifically, as shown in the cross-sectional view of Figure 17 Each curved waveguide path 406P has two horizontal sub-paths P1 and P3 to better match the edge couplers (ECs) and corresponding optical fibers 506 of the PIC 303, and a curved and smooth intermediate sub-path P2 connecting the two horizontal sub-paths P1 and P3. The connection points between each horizontal sub-path and the intermediate sub-path are smoothly rounded. The horizontal sub-paths are laterally aligned with the edge couplers of the PIC 303 for better optical coupling. As shown in Figure 7 The plurality of laser-written waveguide paths 406P respectively correspond to the plurality of laser lenses 402 and thus to the plurality of optical fibers 506.

[0078] In Figure 7 embodiments, a row of laser lenses 402, a row of waveguide paths 406P, and a row of optical fibers 506 are provided for illustration. Figure 17 is shown Figure 7A schematic cross-sectional view is shown. However, the embodiments of this utility model are not limited thereto. In some embodiments, two or more rows of laser lenses 402, two or more rows of waveguide paths 406P, and two or more rows of optical fibers 506 can be designed as needed, such as... Figure 9 As shown. Figure 18 It shows Figure 9 A schematic partial cross-sectional view. In some embodiments, such as Figure 18 As shown in the cross-sectional view, waveguide path 406P has a different profile.

[0079] refer to Figure 15 Following the laser writing process LP, an adapter box 600 is provided to secure the glass substrate 400 and the FAU 500 together. In some embodiments, a cover 900 may be provided above the glass substrate 400 and the photonic structure 301 to protect and secure the underlying glass substrate 400 and photonic structure 301, and to dispense optical adhesive GL2 into the space between the cover 900 and each photonic structure. The glass substrate 400 and the photonic structure 301 are then cured. The cover 900 may be a heat dissipation cover or a glass cover. The optical adhesive GL2 comprises a curable adhesive material and has high light transmittance and high adhesion. The optical adhesive GL2 may have a convex surface and extend from the sidewall of the cover 900. Optical adhesive GL1 and optical adhesive GL2 are collectively referred to as optical adhesive GL. In some embodiments, optical adhesive GL2 and optical adhesive GL1 may comprise the same material, thus there is no interface between optical adhesive GL2 and optical adhesive GL1. In other embodiments, optical adhesive GL2 and optical adhesive GL1 may comprise different materials, thus there is an interface between optical adhesive GL2 and optical adhesive GL1. This completes the packaging assembly 20 of the present invention.

[0080] Figure 16 The packaging assembly 30 and Figure 15 Similar to the encapsulation assembly 20, the encapsulation assembly 30 also includes a spacer wall 902 and optical adhesive between the cover 900 and the photonic structure 301. GL is allocated to the spacer wall 902 and the space between each of the cover 900, the glass substrate 400, and the photonic structure 301. The spacer wall 902 may be a heat-dissipating spacer wall or a glass spacer wall.

[0081] In some embodiments, such as Figure 15 and 16 As shown, the beam L propagates through the optical fiber 506, travels through the laser lens 402 and the laser-written waveguide structure 406, and is optically coupled to the edge coupler (EC) of the PIC303.

[0082] In the above embodiments, after the glass substrate is bonded to the sidewalls of the photonic crystal grains, a laser writing process is performed to form the waveguide structure. However, embodiments of the present application are not limited thereto. In other embodiments, the glass substrate can be subjected to a laser writing process to form the waveguide structure, and then the glass substrate with the waveguide structure written thereon is bonded to the photonic structure. In this case, the glass substrate with the waveguide structure written thereon is adjusted to the appropriate position before the glass substrate is bonded to the photonic structure. In this case, after the bonding process, an optical adhesive is dispensed between the glass substrate and the photonic structure, and then a buffer layer is provided between the support structure and the glass substrate to stabilize the glass substrate, thereby stabilizing the entire package assembly.

[0083] With the three-dimensional (3D) laser-written waveguide structure of the present application, the misalignment problem between the fiber array unit (FAU) and the edge coupler of the photonic structure can be easily solved, and the coupling tolerance between the FAU and the edge coupler can be greatly improved. Specifically, when the fiber array unit (FAU) and the edge coupler are misaligned, the waveguide paths of the waveguide structure of the present application can be written to the appropriate position by the laser writing process, thereby better matching the optical fibers at both ends of each waveguide path and the edge coupler. Thus, the misalignment problem is solved.

[0084] Figure 19 A method of forming a package assembly according to some embodiments is shown. Although this method is illustrated and / or described as a series of acts or events, it will be appreciated that the method is not limited by the illustrated ordering or acts. Thus, in some embodiments, the acts can occur in an order other than that shown, and / or concurrently, and / or with other acts or events not shown. In some embodiments, some illustrated acts or events can be combined, and / or some illustrated acts or events can be split into separate acts or events. In some embodiments, some illustrated acts or events can be omitted, and / or other unillustrated acts or events can be included.

[0085] At act S180, at least one integrated circuit structure is bonded to the interposer structure. Figure 1 and Figure 11 A cross-sectional view corresponding to some embodiments of act S180 is shown.

[0086] At act S182, a photonic structure is bonded to the interposer structure, the photonic structure being lateral to the at least one integrated circuit structure. Figures 1 to 2 and Figures 11 to 12A cross-sectional view of some embodiments corresponding to act S182 is shown. In some embodiments, an optical coupler (e.g., an evanescent coupler) is formed between the photonic structure and the glass substrate, a first reflector is formed adjacent to the optical integrated circuit in the photonic structure, a second reflector is formed between the photonic structure and the glass substrate, and the second reflector is adjacent to the optical coupler, where the second reflector and the first reflector are used to reflect and reposition light beams received from the optical coupler toward the optical integrated circuit, as shown. Figure 2 In other embodiments, an optical coupler (e.g., an edge coupler) is formed inside the optical integrated circuit, as shown. Figure 12

[0087] At act S183, a support structure is provided on a side of the photonic structure. Figure 2 and Figure 12 A cross-sectional view of some embodiments corresponding to act S183 is shown. Act S183 can be optional and can be omitted in some examples.

[0088] At act S184, the glass substrate is assembled to the fiber array unit. Figure 2 , Figure 6 and Figure 12 A cross-sectional view and a perspective view of some embodiments corresponding to act S184 are shown.

[0089] At act S186, the glass substrate with the fiber array unit is bonded to the photonic structure. Figure 3 and Figure 13 A cross-sectional view of some embodiments corresponding to act S186 is shown.

[0090] At step S188, a laser writing process is performed on the glass substrate to form a laser written waveguide structure inside the glass substrate. Figure 4 , Figures 7 to 10 and Figure 14 A cross-sectional view and a perspective view of some embodiments corresponding to act S188 are shown. The laser written waveguide structure is optically coupled to the fiber array unit and the photonic structure. In some embodiments, the laser writing process also forms at least one laser lens between the fiber array unit and the laser written waveguide structure, as shown. Figure 4 , Figures 7 to 10 , Figure 14 In some embodiments, the laser written waveguide structure has multiple curved waveguide paths, as shown. Figure 8 and Figure 10

[0091] At act S189, a cap is bonded to the glass substrate. Figure 15 and Figure 16 ​​Cross-sectional views are shown corresponding to some embodiments of act S189. In some embodiments, the cap is bonded to the photonic structure and the glass substrate, as shown in Figure 15 and Figure 16 In some embodiments, a spacer is further formed between the cap and the photonic structure, as shown in Figure 16 Act S189 can be optional and in some examples can be omitted, as shown in Figure 5

[0092] In the above formation sequence, the glass substrate is bonded to the photonic structure (act S186) before the laser writing process is performed (act S188). However, embodiments of the present application are not limited thereto. In other embodiments, the glass substrate is bonded to the photonic structure (act S186) after the laser writing process is performed (act S188). In this case, an act S187 of adjusting the position of the glass substrate can be implemented between act S188 and act S186.

[0093] Figure 20 A method of forming a package assembly is shown according to some embodiments. Although the method is illustrated and / or described as a series of acts or events, it will be understood that the method is not limited by the illustrated ordering of acts or events. Thus, some acts can occur in different orders than shown, and / or some acts can occur concurrently with other acts. Also, some illustrated acts or events can be combined with other acts or events. In some embodiments, some illustrated acts or events can be omitted, and other non-illustrated acts or events can be included. In some embodiments, the acts or events can be performed by one or more elements of a system.

[0094] At step S190, a package structure is provided, the package structure including an interposer structure and an overlying photonic structure. Figure 1 Cross-sectional views are shown corresponding to some embodiments of act S190.

[0095] At act S192, a support structure is provided on sides of the package structure. Figure 2 Cross-sectional views are shown corresponding to some embodiments of act S192.

[0096] At act S194, a glass substrate with an optical coupler is placed on the photonic structure, with the optical coupler interposed between the glass substrate and the photonic structure. Figure 3 Cross-sectional views are shown corresponding to some embodiments of act S194.

[0097] At act S196, optical glue is dispensed into a space between the glass substrate and the photonic structure. Figure 3 ​Cross-sectional views corresponding to some embodiments of act S196 are shown. In some embodiments, a buffer layer is provided between the support structure and the glass substrate prior to act S196. In other embodiments, a buffer layer is provided between the support structure and the glass substrate after act S196.

[0098] Step S198, a laser writing process is performed on the glass substrate to form a laser written waveguide structure inside the glass substrate. Figure 4 and Figures 7 to 10 Cross-sectional views and perspective views corresponding to some embodiments of act S198 are shown. In some embodiments, the laser writing process further forms at least one laser lens between the fiber array unit and the laser written waveguide structure. Wherein the laser written waveguide structure has a plurality of curved waveguide paths.

[0099] In act S199, a cap is bonded to the glass substrate. Act S199 can be optional and can be omitted in some examples, as Figure 5 shown.

[0100] The packaged assembly of the present disclosure is described below with reference to Figures 5 to 10 and Figures 15 to 18 .

[0101] In some embodiments, the packaged assembly 10 / 20 / 30 includes a photonic structure 300 / 301, an encapsulation layer El, and a laser written waveguide structure 406. The photonic structure 300 / 301 is disposed on the interposer structure 100. The encapsulation layer El is disposed on the side of the photonic structure 300 / 301. The laser written waveguide structure 406 is embedded in the glass substrate 400 and disposed adjacent to the photonic structure 300 / 301, wherein the laser written waveguide structure 406 has a plurality of curved waveguide paths 406P.

[0102] In some embodiments, the packaged assembly 10 / 20 / 30 further includes a plurality of laser lenses 402 embedded in the glass substrate 400 and in contact with the laser written waveguide structure 406.

[0103] In some embodiments, the laser written waveguide structure 406 is bonded to the top surface of the photonic structure 300, as Figure 5 shown. In some embodiments, the laser written waveguide structure 406 is optically coupled to the PIC 303 through an evanescent coupler (EVC) 412. The evanescent coupler (EVC) 412 overlaps with the laser written waveguide structure 406 in cross-section.

[0104] In some embodiments, the laser written waveguide structure 406 is bonded to the sidewall of the photonic structure 301, as Figure 15 and Figure 16In some embodiments, the laser-written waveguide structure 406 is optically coupled to an edge coupler of the PIC 303. The edge coupler of the PIC 303 is laterally aligned with the laser-written waveguide structure 406.

[0105] In summary, the three-dimensional (3D) laser-written waveguide structure of the present application can easily solve the misalignment problem between the fiber array unit (FAU) and the photonic structure, and the coupling tolerance between the FAU and the photonic structure. The photonic structure can be greatly improved. The optical interconnection provided by the photonic structure can easily achieve higher communication performance and more compact packaging.

[0106] Many variations of the above examples are contemplated by the present application. It should be understood that different embodiments can have different advantages, and not all embodiments need necessarily have particular advantages.

[0107] According to some embodiments of the present application, the packaging assembly includes the following operations. Bonding at least one integrated circuit structure to an interposer structure. Bonding a photonic structure to the interposer structure and the photonic structure is laterally positioned to a side of the at least one integrated circuit structure. Assembling a glass substrate to a fiber array unit. Bonding the glass substrate with the fiber array unit to the photonic structure. Performing a laser writing process on the glass substrate to form a laser-written waveguide structure inside the glass substrate, wherein the laser-written waveguide structure is optically coupled to the fiber array unit and the photonic structure.

[0108] According to some embodiments of the present application, a method of forming a packaging assembly includes the following operations. Providing a packaging structure. The packaging structure includes an interposer structure and an overlying photonic structure. Placing a glass substrate with an optical coupler on the photonic structure, wherein the optical coupler is interposed between the glass substrate and the photonic structure. Performing a laser writing process on the glass substrate to form a laser-written waveguide structure inside the glass substrate.

[0109] According to some embodiments of the present application, a packaging assembly includes a photonic structure, a cladding layer, and a laser-written waveguide structure. The photonic structure is disposed on an interposer structure. The cladding layer is laterally positioned to a side of the photonic structure. The laser-written waveguide structure is embedded in a glass substrate and disposed adjacent to the photonic structure, wherein the laser-written waveguide structure has a plurality of curved waveguide paths.

[0110] According to some embodiments of the present application, a packaging assembly includes a photonic structure, a laser-written waveguide structure, and a fiber array unit. The photonic structure is disposed on an interposer structure. The laser-written waveguide structure is embedded in a glass substrate and disposed adjacent to the photonic structure, wherein the laser-written waveguide structure has a plurality of waveguide paths. The fiber array unit is laterally disposed adjacent to the laser-written waveguide structure, wherein the fiber array unit includes a plurality of optical fibers corresponding to the plurality of waveguide paths. In some embodiments, the plurality of waveguide paths have different profiles as viewed from a cross-sectional view.

[0111] Other features and processes can also be included. For example, test structures can be included to assist in verifying testing of 3D packages or 3DIC devices. Test structures can include, for example, test pads formed on redistribution layers or substrates that allow for testing of 3D packages or 3DICs, use of probes and / or probe cards, etc. Verification testing can be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein can be used in conjunction with test methods that incorporate intermediate verification of known good dies to increase yield and reduce costs.

[0112] The foregoing overview of features of several embodiments enables a person of ordinary skill in the art to better understand aspects of the embodiments of the present application. Those skilled in the art will appreciate that, given the present disclosure, they can readily apply the teachings of the present application to design or modify other processes and structures to achieve the same advantages without departing from the spirit and scope of the embodiments of the present application. Those skilled in the art will also recognize or be able to ascertain, using no more than routine experimentation, many equivalents to the specific embodiments of the application described herein. It is therefore intended that the embodiments of the present application not be limited to the described embodiments but encompass all such departures from the present disclosure as come within the scope of the following claims and their equivalents.

Claims

1. A package assembly, characterized by, comprising: a photonic structure disposed on an interposer structure; an encapsulation layer laterally positioned to the photonic structure; and a laser-written waveguide structure embedded in a glass substrate and disposed adjacent to the photonic structure, wherein the laser-written waveguide structure has a plurality of curved waveguide paths. Further comprising a plurality of laser lenses embedded in the glass substrate and in contact with the laser-written waveguide structure.

2. The package assembly of claim 1, wherein, 3. The package assembly of claim 1, wherein the glass substrate with the laser- written waveguide structure is bonded to a top surface of the photonic structure. Further comprising an evanescent coupler disposed between the photonic structure and the glass substrate.

4. The package assembly of claim 3, wherein, Further comprising:

5. The package assembly of claim 4, wherein, a first reflector disposed adjacent to an optical integrated circuit in the photonic structure; and a second reflector disposed between the photonic structure and the glass substrate and adjacent to the evanescent coupler, wherein the second reflector and the first reflector are configured to reflect and reposition an optical beam received from the evanescent coupler to the optical integrated circuit. The glass substrate with the laser-written waveguide structure is bonded to a sidewall of the photonic structure. Further comprising an edge coupler disposed inside an optical integrated circuit of the photonic structure, and the laser-written waveguide structure inside the glass substrate is laterally aligned with the edge coupler.

6. The package assembly of claim 1, wherein, Further comprising a cap bonded to the photonic structure and the glass substrate.

7. The package assembly of claim 6, wherein, comprising:

8. The package assembly of claim 6, wherein, a photonic structure disposed on an interposer structure; 9. A package assembly, characterized by a laser-written waveguide structure embedded in a glass substrate and disposed adjacent to the photonic structure, wherein the laser-written waveguide structure has a plurality of waveguide paths; and an optical fiber array unit laterally disposed adjacent to the laser-written waveguide structure, wherein the optical fiber array unit comprises a plurality of optical fibers corresponding to the plurality of the waveguide paths, wherein the plurality of waveguide paths have different profiles as viewed in cross-section. Further comprising a support structure disposed on the interposer structure laterally to the photonic structure and configured to support the glass substrate. ​ 10. The package assembly of claim 9, wherein, ​

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