Display panel and display device

Abstract

The utility model discloses a display panel and a display device, and relates to the technical field of display. The display panel comprises a substrate, a plurality of pixel units and a plurality of signal lines. The second line segments, located in the non-pixel area, of the first type of signal lines in the multiple signal lines are made of transparent materials, so that the transparent display area of the display panel can be increased, and the transparent display effect is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] The display panel usually includes a plurality of pixel units arranged in an array in a display region of a substrate, and a signal line for providing a driving signal for each pixel unit.

[0003] In the related art, the substrate includes a display region and a peripheral region surrounding the display region. Two ends of the signal line are located in the peripheral region for connecting a driving circuit. The middle part of the signal line is located in the display region for connecting the pixel unit.

[0004] However, since the material of the signal line has low transmittance, the transparent display effect of the display panel is poor. CONTENT OF UTILITY MODEL

[0005] The present application provides a display panel and a display device, which can solve the problem of poor transparent display effect of the display panel. The technical solution is as follows:

[0006] In one aspect, a display panel is provided, which includes:

[0007] a substrate including a display region;

[0008] a plurality of pixel units located in the display region, the plurality of pixel units constituting a plurality of pixel unit groups arranged along a first direction and extending along a second direction, the pixel unit group including a plurality of pixel units, and the second direction intersecting the first direction;

[0009] and a plurality of signal lines arranged along the first direction and extending along the second direction, the signal lines being electrically connected to the pixel units, the plurality of signal lines including a first type of signal line, the first type of signal line including a first line segment and a second line segment electrically connected, a projection of the first line segment on the substrate at least partially overlapping a projection of the pixel unit on the substrate and not being located between adjacent pixel units arranged along the second direction, a projection of the second line segment on the substrate being located between the adjacent pixel units arranged along the second direction, and a material of the second line segment including a light-transmitting material.

[0010] Optionally, the first type of signal line includes a data signal line and a sensing signal line, and the plurality of signal lines further includes a first power signal line and a second power signal line.

[0011] The pixel unit comprises a pixel circuit and a light emitting unit, the pixel circuit comprises a plurality of thin film transistors and at least one storage capacitor, the light emitting unit comprises an anode, a light emitting part and a cathode, and the pixel circuit and the anode of the light emitting unit are electrically connected;

[0012] The data signal line, the sensing signal line and the first power signal line are electrically connected to the thin film transistors in the pixel circuit, the second power signal line is electrically connected to the cathode in the light emitting unit, and the potential of the first power signal provided by the first power signal line for the pixel unit is higher than the potential of the second power signal provided by the second power signal line for the pixel unit.

[0013] Optionally, the plurality of signal lines further comprise a second type of signal line, and a material of the second type of signal line comprises a non-light-transmitting material.

[0014] The plurality of signal lines form a plurality of signal line groups arranged along the first direction and corresponding to the plurality of pixel unit groups, the plurality of signal line groups comprise a first signal line group and a second signal line group arranged along the first direction and adjacent to each other, and at least one of the first signal line group and the second signal line group comprises the first power signal line and the second power signal line.

[0015] In the signal line group comprising the first power signal line and the second power signal line, one of the first power signal line and the second power signal line is the first type of signal line, and the other is the second type of signal line.

[0016] Optionally, the first signal line group comprises the first power signal line, the second signal line group comprises the first power signal line and the second power signal line, and the display panel further comprises a first connection signal line extending along the first direction.

[0017] One end of the first connection signal line is connected to the first power signal line in the first signal line group, and the other end is connected to the first power signal line in the second signal line group.

[0018] Optionally, the first power signal line in the second signal line group is closer to the first signal line group than the second power signal line in the second signal line group.

[0019] In the second signal line group, the first power signal line is the first type of signal line, and the first power signal line in the second signal line group is the second type of signal line.

[0020] Optionally, the first signal line group and the second signal line group each include the first power signal line and the second power signal line; the display panel further includes: a first connection signal line and a second connection signal line extending along the first direction;

[0021] One end of the first connection signal line is connected with the first power signal line in the first signal line group, and the other end is connected with the first power signal line in the second signal line group; one end of the second connection signal line is connected with the second power signal line in the first signal line group, and the other end is connected with the second power signal line in the second signal line group.

[0022] Optionally, the second power signal line in the first signal line group is closer to the second signal line group than the first power signal line in the first signal line group, and the first power signal line in the second signal line group is closer to the first signal line group than the second power signal line in the second signal line group.

[0023] The second power signal line in the first signal line group and the first power signal line in the second signal line group are first type signal lines, and the first power signal line in the first signal line group and the second power signal line in the second signal line group are second type signal lines.

[0024] Optionally, the display panel includes: a pixel unit layer, the pixel unit layer includes a pixel circuit layer and a light emitting unit layer, the pixel circuit layer includes pixel circuits of the plurality of pixel units, and the light emitting unit layer includes light emitting units of the plurality of pixel units.

[0025] The pixel circuit layer includes, in a direction away from the substrate, an opaque conductive layer, a light-transmitting conductive layer, a buffer layer, an active layer, a gate insulating layer, a gate layer, a passivation layer, and a planarization layer, which are sequentially stacked.

[0026] The light emitting unit layer includes, in a direction away from the substrate, an anode layer, a pixel defining layer, a light emitting functional layer, and a cathode layer, which are sequentially stacked.

[0027] The first line segment is located in the opaque conductive layer, the second line segment is located in the light-transmitting conductive layer, and the second line segment and the first line segment overlap and are in contact and electrically connected.

[0028] The active layer includes an active pattern of a thin film transistor, the gate layer includes a gate, a source and a drain of a thin film transistor, the gate is located between the source and the drain, and the source and the drain are electrically connected through a via in the gate insulating layer and the active pattern.

[0029] The material of the anode layer comprises a light-transmitting material, the anode layer comprises an anode of a light-emitting unit of the plurality of pixel units, the pixel boundary layer comprises a plurality of pixel openings for exposing at least part of the anode, the light-emitting functional layer comprises a light-emitting part of a light-emitting unit of the plurality of pixel units, the light-emitting part is located in the pixel opening and connected with at least part of the anode exposed by the pixel opening, and the cathode layer comprises a cathode of a light-emitting unit of the plurality of pixel units, the cathode being connected with the light-emitting part.

[0030] Optionally, the anode in the light-emitting unit in each of the pixel units comprises a first anode part and a second anode part arranged at intervals; and the display panel further comprises a repair architecture comprising a first repair part and a second repair part.

[0031] The first repair part is electrically connected with the pixel circuit, the second repair part is electrically connected with the first repair part, a first end of the second repair part is electrically connected with the first anode part, and a second end of the second repair part is electrically connected with the second anode part, the first end and the second end of the second repair part being respectively located on two sides of a position where the second repair part and the first repair part are electrically connected.

[0032] The first repair part is located on the light-transmitting conductive layer, and the second repair part is located on the anode layer.

[0033] Optionally, the display panel further comprises a connecting part located on the gate layer, a first overlapping area exists between a normal projection of the connecting part on the substrate and a normal projection of the first repair part on the substrate, a second overlapping area exists between a normal projection of the connecting part on the substrate and a normal projection of the second repair part on the substrate, and the first overlapping area and the second overlapping area do not overlap.

[0034] The connecting part and the first repair part are electrically connected through a via hole in the gate insulating layer and the buffer layer in the first overlapping area, and the connecting part and the second repair part are electrically connected through a via hole in the passivation layer and the planarization layer in the second overlapping area.

[0035] Optionally, the target power supply line of the first power supply signal line and the second power supply signal line included in the plurality of signal lines comprises a first power supply line part and a second power supply line part located on the light-shielding conductive layer, and a third power supply line part located on the gate layer.

[0036] Both the first power line portion and the second power line portion extend along the second direction, and the first power line portion and the second power line portion are spaced apart in the second direction. The orthographic projection of the third power line portion on the substrate and the orthographic projection of the first power line portion on the substrate at least partially overlap. The third power line portion is electrically connected to the first power line portion through vias in the gate insulating layer and the buffer layer. The orthographic projection of the third power line portion on the substrate and the orthographic projection of the second power line portion on the substrate at least partially overlap. The third power line portion is electrically connected to the second power line portion through vias in the gate insulating layer and the buffer layer.

[0037] Optionally, the storage capacitor included in the pixel circuit includes a first capacitor plate located in the light-shielding conductive layer and a second capacitor plate located in the gate layer, wherein the orthographic projection of the second capacitor plate on the substrate and the orthographic projection of the first capacitor plate on the substrate at least partially overlap.

[0038] The first repair section is a strip-shaped structure extending along the first direction. The first end of the first repair section overlaps with the first capacitor plate and is electrically connected. The second end of the first repair section is located on the side of the target power line away from the first capacitor plate.

[0039] The first repair section is at least partially located at the interval between the first power cord section and the second power cord section in the second direction.

[0040] Optionally, the plurality of signal lines includes a plurality of data signal lines, wherein the orthographic projection of the first target data signal line among the plurality of data signal lines on the substrate is located between the orthographic projection of the first end of the first repair part on the substrate and the orthographic projection of the second end of the first repair part on the substrate.

[0041] The first target data signal line includes: at least a first data line portion and a second data line portion located in the transparent conductive layer, and a third data line portion located in the gate layer;

[0042] The first data line portion and the second data line portion both extend along the second direction, and the first data line portion and the second data line portion have a spacing in the second direction, a projection of the third data line portion on the substrate substrate and a projection of the first data line portion on the substrate substrate at least partially overlap, the third data line portion is electrically connected with the first data line portion through a via in the gate insulating layer and the buffer layer, and a projection of the third data line portion on the substrate substrate and a projection of the second data line portion on the substrate substrate at least partially overlap, the third data line portion is electrically connected with the second data line portion through a via in the gate insulating layer and the buffer layer.

[0043] At least part of the first repair portion is located in the spacing of the first data line portion and the second data line portion in the second direction.

[0044] Optionally, the plurality of data signal lines further include a second target data signal line, a projection of the second target data signal line on the substrate substrate and a projection of the first repair portion on the substrate substrate have a spacing in the first direction; and the second target data signal line is located at least in the light-transmitting conductive layer.

[0045] Optionally, the first data line portion and the second data line portion, and the second target data signal line are further located in a light-shielding conductive layer.

[0046] A projection of the first data line portion, the second data line portion, and the second target data signal line on the substrate substrate and a projection of the pixel unit on the substrate substrate at least partially overlap, and are not located between pixel units arranged along the second direction and adjacent to each other.

[0047] A projection of the first data line portion, the second data line portion, and the second target data signal line on the substrate substrate and a projection of the pixel unit on the substrate substrate at least partially overlap, and are located between pixel units arranged along the second direction and adjacent to each other.

[0048] Optionally, a sensing signal line included in the plurality of signal lines has a projection on the substrate substrate and a projection of the first repair portion on the substrate substrate has a spacing in the first direction; and the sensing signal line is located at least in the light-transmitting conductive layer.

[0049] Optionally, the sensing signal line is further located in a light-shielding conductive layer.

[0050] The sensing signal line is located at least partially overlapped with the orthographic projection of the part of the light-shielding conductive layer on the substrate and the orthographic projection of the pixel unit on the substrate, and is not located between the pixel units arranged along the second direction and adjacent to each other.

[0051] The sensing signal line is located at least partially overlapped with the orthographic projection of the part of the light-shielding conductive layer on the substrate and the orthographic projection of the pixel unit on the substrate, and is not located between the pixel units arranged along the second direction and adjacent to each other.

[0052] Optionally, the display panel further comprises: a switching architecture, the switching architecture comprises a first switching part located at the light-transmitting conductive layer, a second switching part located at the gate layer, and a third switching part located at the anode layer.

[0053] The first switching part is a strip structure extending along the first direction, a first end of the first switching part is electrically connected with a second power signal line in the display panel, a second end of the first switching part is electrically connected with the second switching part through a via in the gate insulating layer and the buffer layer, the third switching part is electrically connected with the second switching part through a via in the planar layer and the passivation layer, and the third switching part is electrically connected with the cathode layer.

[0054] Optionally, the anode layer comprises a first material layer, a second material layer and a third material layer stacked in a direction away from the substrate, a material etching rate of the first material layer and the third material layer is less than a material etching rate of the second material layer.

[0055] The third switching part comprises a first part located at the first material layer, a second part located at the second material layer and a third part located at the third material layer, a boundary of the second part is recessed relative to boundaries of the first part and the third part.

[0056] The light-emitting functional layer further comprises an electron functional layer and a hole functional layer, the electron functional layer and the hole functional layer are integral film layers, and the electron functional layer and the hole functional layer are in a broken state at the boundary of the third part, and the cathode layer is electrically connected with the second part through a broken position of the electron functional layer and the hole functional layer.

[0057] On the other hand, a display device is provided, comprising: a power supply component and a display panel as described in the above aspects.

[0058] The power supply component is connected with the display panel, and is configured to supply power to the display panel.

[0059] The technical scheme provided in the application has at least the following beneficial effects:

[0060] The application provides a display panel and a display device. The display panel comprises a substrate, a plurality of pixel units and a plurality of signal lines. The first type of signal line in the plurality of signal lines is arranged in a second line segment of a non-pixel region and is made of transparent material, so that the transparent display area of the display panel is increased, and the transparent display effect is improved. BRIEF DESCRIPTION OF DRAWINGS

[0061] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0062] Figure 1 is a partial top view of a display panel provided by an embodiment of the present application;

[0063] Figure 2 is an equivalent circuit diagram of a pixel unit provided by an embodiment of the present application;

[0064] Figure 3 is a cross-sectional schematic view of a display panel provided by an embodiment of the present application;

[0065] Figure 4 is a partial top view of another display panel provided by an embodiment of the present application;

[0066] Figure 5 is a partial top view of still another display panel provided by an embodiment of the present application;

[0067] Figure 6 is a partial top view of yet another display panel provided by an embodiment of the present application;

[0068] Figure 7 is a partial top view of a light-transmitting conductive layer provided by an embodiment of the present application;

[0069] Figure 8 is a partial top view of a light-shielding conductive layer provided by an embodiment of the present application;

[0070] Figure 9 is a partial top view of a light-transmitting conductive layer and a light-shielding conductive layer provided by an embodiment of the present application;

[0071] Figure 10 is a partial top view of an active layer provided by an embodiment of the present application;

[0072] Figure 11 is a partial top view of a light-transmitting conductive layer, a light-shielding conductive layer and an active layer provided by an embodiment of the present application;

[0073] Figure 12 is a partial top view of a stack of a light-transmitting conductive layer, a light-blocking conductive layer, a buffer layer, an active layer, and a gate insulating layer provided by an embodiment of the present application;

[0074] Figure 13 is a partial top view of a gate layer provided by an embodiment of the present application;

[0075] Figure 14 is a partial top view of a stack of a light-transmitting conductive layer, a light-blocking conductive layer, a buffer layer, an active layer, a gate insulating layer, and a gate layer provided by an embodiment of the present application;

[0076] Figure 15 is a partial top view of a stack of a light-transmitting conductive layer, a light-blocking conductive layer, a buffer layer, an active layer, a gate insulating layer, a gate layer, and a passivation layer provided by an embodiment of the present application;

[0077] Figure 16 is a partial top view of a planarization layer provided by an embodiment of the present application;

[0078] Figure 17 is a partial top view of a stack of a light-transmitting conductive layer, a light-blocking conductive layer, a buffer layer, an active layer, a gate insulating layer, a gate layer, a passivation layer, and a planarization layer provided by an embodiment of the present application;

[0079] Figure 18 is a partial top view of an anode layer provided by an embodiment of the present application;

[0080] Figure 19 is a partial top view of a stack of a light-transmitting conductive layer, a light-blocking conductive layer, a buffer layer, an active layer, a gate insulating layer, a gate layer, a passivation layer, a planarization layer, and an anode layer provided by an embodiment of the present application;

[0081] Figure 20 is a partial top view of a stack of a planarization layer, an anode layer, and a pixel definition layer provided by an embodiment of the present application;

[0082] Figure 21 is a partial cross-sectional view of a transfer structure provided by an embodiment of the present application;

[0083] Figure 22 is another partial top view of a light-transmitting conductive layer provided by an embodiment of the present application;

[0084] Figure 23 is another partial top view of a light-blocking conductive layer provided by an embodiment of the present application;

[0085] Figure 24 is a partial top view of a stack of a light-transmitting conductive layer and a light-blocking conductive layer provided by an embodiment of the present application;

[0086] Figure 25 is another partial top view of an active layer provided by an embodiment of the present application;

[0087] Figure 26 is another partial top view of a stack of a light-transmitting conductive layer, a light-blocking conductive layer, and an active layer provided by an embodiment of the present application;

[0088] Figure 27 is another partial top view of a stack of a light-transmitting conductive layer, a light-blocking conductive layer, a buffer layer, an active layer, and a gate insulating layer provided by an embodiment of the present application;

[0089] Figure 28 is another partial top view of a gate layer provided by an embodiment of the present application;

[0090] Figure 29 is another partial top view of a stack of a light-transmitting conductive layer, a light-blocking conductive layer, a buffer layer, an active layer, a gate insulating layer, and a gate layer provided by an embodiment of the present application;

[0091] Figure 30 is another partial top view of a stack of a light-transmitting conductive layer, a light-blocking conductive layer, a buffer layer, an active layer, a gate insulating layer, a gate layer, and a passivation layer provided by an embodiment of the present application;

[0092] Figure 31 is another partial top view of a planarization layer provided by an embodiment of the present application;

[0093] Figure 32 is another partial top view of a stack of a light-transmitting conductive layer, a light-blocking conductive layer, a buffer layer, an active layer, a gate insulating layer, a gate layer, a passivation layer, and a planarization layer provided by an embodiment of the present application;

[0094] Figure 33 is another partial top view of an anode layer provided by an embodiment of the present application;

[0095] Figure 34 is another partial top view of a stack of a light-transmitting conductive layer, a light-blocking conductive layer, a buffer layer, an active layer, a gate insulating layer, a gate layer, a passivation layer, a planarization layer, and an anode layer provided by an embodiment of the present application;

[0096] Figure 35 is another partial top view of a stack of a light-transmitting conductive layer, a light-blocking conductive layer, a buffer layer, an active layer, a gate insulating layer, a gate layer, and a passivation layer provided by an embodiment of the present application;

[0097] Figure 36 is a structural schematic diagram of a display device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0098] For the purposes of the present application, the technical solutions and advantages thereof will be further described in detail below with reference to the drawings.

[0099] The current mature technologies in the display field are liquid crystal display (LCD) and active matrix organic light-emitting diode (OLED) display. The general technology of an OLED display panel is to excite various wavelengths of light spectrum by means of direct recombination of electrons and holes, thereby forming a pattern. The display device formed by the OLED display panel is self-emitting and has a fast response speed, and can achieve maximum contrast ratio, so the OLED display device is expected to become the mainstream product of the next generation of display.

[0100] Figure 1 is a partial top view of a display panel provided by an embodiment of the present application. Referring to Figure 1 It can be seen that the display panel 100 includes a substrate 101, a plurality of pixel units 102, and a plurality of signal lines 103.

[0101] The substrate 101 includes a display area. Figure 1 may be a partial top view of a portion of the display panel 100 located in the display area. Referring to Figure 1 The plurality of pixel units 102 can be located in the display area 101a. The plurality of pixel units 102 constitute a plurality of pixel unit groups 102z arranged along a first direction X and extending along a second direction Y. The pixel unit group 102z includes a plurality of pixel units 102. The second direction Y and the first direction X intersect. Figure 1 A partial area of one pixel unit group 102z is shown in

[0102] Optionally, the second direction Y and the first direction X are perpendicular, such as the first direction X is the pixel row direction of the display panel 100, and the second direction Y is the pixel column direction of the display panel 100.

[0103] Referring to Figure 1The plurality of signal lines 103 are arranged along the first direction X and extend along the second direction Y. The signal lines 103 are electrically connected to the pixel units 102 and are configured to provide driving signals for the pixel units 102. The plurality of signal lines 103 include first-type signal lines 1031. The first-type signal lines 1031 include first segments 10311 and second segments 10312. The first segments 10311 are arranged to at least partially overlap the pixel units 102 on the substrate 101 and are not located between adjacent pixel units 102 arranged along the second direction Y. The second segments 10312 are arranged to be located between adjacent pixel units 102 arranged along the second direction Y. The second segments 10312 are made of a light-transmitting material.

[0104] In the embodiments of the present application, the pixel units 102 on the substrate 101 can be pixel regions, and the regions between the pixel units 102 on the substrate 101 can be non-pixel regions. Generally, the pixel regions have lower transparency than the non-pixel regions because the pixel regions are provided with the pixel units 102 while the non-pixel regions are not provided with the pixel units 102. Therefore, in order to improve the transparency of the display panel 100, the area of the non-pixel regions can be increased.

[0105] Optionally, because the signal lines 103 in the display panel 100 need to transmit signals, the material for manufacturing the signal lines 103 needs to be selected from a metal material with a small sheet resistance. Because the metal material has poor transparency, the embodiments of the present application set the first-type signal lines 1031 in the plurality of signal lines 103 as segmented signal lines, set the first segments 10311 of the first-type signal lines 1031 located in the pixel regions as non-transparent materials (such as metal materials) to ensure signal transmission, and set the second segments 10312 of the first-type signal lines 1031 located in the non-pixel regions as transparent materials (such as indium tin oxide ITO) to improve the transparent display effect of the non-pixel regions.

[0106] Optionally, the sheet resistance of the indium tin oxide ITO is greater than that of the metal material, and therefore setting the material of the second segments 10312 of the first-type signal lines 1031 as indium tin oxide may have certain influence on the reliability of signal transmission of the signal lines 103. Therefore, in order to reduce the influence of signal transmission, the first-type signal lines 1031 in the plurality of signal lines 103 of the display panel 100, which have low stability requirements for signal transmission, can be set as segmented signal lines with transparent segments.

[0107] In summary, the display panel provided by the embodiment of the present application includes a substrate, a plurality of pixel units and a plurality of signal lines. The first type of signal line in the plurality of signal lines is arranged as a segmented signal line in the second line segment of the non-pixel region, thereby increasing the transparent display area of the display panel and improving the transparent display effect.

[0108] Reference Figure 1 As can be seen, in the display panel 100, in addition to the transparent display area between the pixel units 102 arranged along the second direction Y and adjacent to each other by arranging the first type of signal line 1031 as a segmented signal line, the transparent display area can also be between the pixel unit groups 102z arranged along the first direction X and adjacent to each other. Thus, the display panel 100 has a larger transparent display area, thereby improving the overall transmittance of the display panel 100 and ensuring the transparent display effect of the display panel 100. Moreover, the long black line display of the first type of signal line 1031 is eliminated in the off-state effect of the display panel 100 (i.e., in the non-display state), and instead becomes a broken black line, thereby improving the transparent display effect of the display panel 100.

[0109] In the embodiment of the present application, the signal transmitted by the data signal line (data) is a data signal, and the requirement for stability is relatively low. Therefore, the data signal line (data) can be arranged as a segmented signal line including a transparent line segment (second line segment 10312). That is, the first type of signal line 1031 can include the data signal line.

[0110] In addition, the sensing signal line (sense) is usually used to transmit various control signals, and therefore the sensing signal line usually focuses on the speed and efficiency of signal transmission, and the requirement for stability is relatively low. Therefore, the sensing signal line can also be arranged as a segmented signal line including a transparent line segment (second line segment 10312). That is, the first type of signal line 1031 can include the sensing signal line.

[0111] Optionally, in addition to the data signal line (data) and the sensing signal line (sense), the plurality of signal lines 103 can also include a first power signal line and a second power signal line. The first power signal line VDD and the second power signal line are both used to provide a power signal for the pixel unit 102. For example, the first power signal line provides a first power signal for the pixel unit, and the potential of the first power signal is higher than the potential of the second power signal provided by the second power signal line for the pixel unit 102. The first power signal line can be a positive power supply line (or referred to as a VDD line), and the second power signal line can be a negative power supply line (or referred to as a VSS line).

[0112] Figure 2 is an equivalent circuit diagram of a pixel unit provided by the embodiment of the present application. ReferenceFigure 2 The pixel unit 102 includes a pixel circuit 1021 and a light emitting unit 1022. The pixel circuit 1021 can include a plurality of thin film transistors (TFTs) and at least one storage capacitor.

[0113] For example Figure 2 The first transistor T1, the second transistor T2, the third transistor T3 and the storage capacitor Cst are shown in FIG. 1, i.e., the pixel circuit 1021 can be a 3T1C pixel circuit. Of course, the pixel circuit 1021 can also include other numbers of transistors and other numbers of storage capacitors. The number of transistors and storage capacitors included in the pixel circuit 1021 is not specifically limited in the embodiments of the present application.

[0114] Optionally, the first transistor T1, the second transistor T2 and the third transistor T3 can all be N-type transistors (denoted as NTFT), such as oxide thin film transistors.

[0115] Figure 3 FIG. 1 is a schematic view of a cross section of a display panel provided in the embodiments of the present application. Referring to Figure 3 The light emitting unit 1022 includes an anode 10221, a light emitting part 10222 and a cathode 10223. In combination with Figure 2 and Figure 3 The pixel circuit 1021 and the anode 10221 of the light emitting unit 1022 are electrically connected. Among them, the data signal line (data), the sensing signal line (sense) and the first power signal line VDD are all electrically connected to the thin film transistors in the pixel circuit 1021, and the second power signal line VSS is electrically connected to the cathode 10223 in the light emitting unit 1022. Optionally, the display panel 100 further includes a plurality of gate signal lines (scan) arranged along the second direction Y and extending along the first direction X.

[0116] Referring to Figure 2 The gate of the first transistor T1 is connected to the gate signal line, the first electrode of the first transistor T1 is connected to the data signal line, and the second electrode of the first transistor T1 is connected to the first node J1.

[0117] The gate of the second transistor T2 is connected to the gate signal line, the first electrode of the second transistor T2 is connected to the sensing signal line, and the second electrode of the second transistor T2 is connected to the second node J2.

[0118] The gate of the third transistor T3 is connected to the first node J1, the first electrode of the third transistor T3 is connected to the first power signal line VDD, and the second electrode of the third transistor T3 is connected to the second node J2.

[0119] The first pole of the storage capacitor Cst is connected with the first node J1, and the second pole of the storage capacitor Cst is connected with the second node J2.

[0120] Further, the anode 10221 of the light emitting unit 1022 can be connected with the second node J2 of the pixel circuit 1021, and the cathode 10223 of the light emitting unit 1022 can be connected with the second power supply signal line VSS.

[0121] Optionally, referring to Figure 4 The plurality of signal lines 103 form a plurality of signal line groups 103z arranged along the first direction X and corresponding to the plurality of pixel unit groups 102z. The plurality of signal line groups 103z include a first signal line group 103z1 and a second signal line group 103z2 arranged along the first direction X and adjacent to each other. At least one of the first signal line group 103z1 and the second signal line group 103z2 includes the first power supply signal line VDD and the second power supply signal line VSS. For example Figure 4 In some embodiments, the first signal line group 103z1 and the second signal line group 103z2 both include the first power supply signal line VDD and the second power supply signal line VSS.

[0122] In the embodiments of the present application, the plurality of signal lines 103 can include a second type of signal line 1032, and the material of the second type of signal line 1032 includes a non-transparent material. The material of the second type of signal line 1032 includes a non-transparent material means that the entire second type of signal line 1032 is a non-transparent material, and is not a segmented signal line including transparent segments. For example Figure 4 In some embodiments, the first signal line group 103z1 and the second signal line group 103z2 include the first power supply signal line VDD and the second power supply signal line VSS, both of which are the second type of signal line 1032.

[0123] Since the first power supply signal line VDD and the second power supply signal line VSS are both used to provide a power supply voltage, the stability of the signal is relatively high, and therefore the first power supply signal line VDD and the second power supply signal line VSS can be the second type of signal line 1032 included in the plurality of signal lines 103, which can ensure the stability and reliability of the transmission of the first power supply signal line VDD and the second power supply signal line VSS.

[0124] Of course, in order to further increase the area of the transparent display area of the display panel 100, the first power signal line VDD of one of the two adjacent signal line groups 103z can be the first type of signal line 1031, and the first power signal line VDD of the other signal line group 103z can be the second type of signal line 1032. In order to ensure the stability and reliability of the first power signal transmission, the first power signal lines VDD of the two signal line groups 103z can be connected by a connection signal line extending along the first direction X. In addition, the second power signal line VSS of one of the two adjacent signal line groups 103z can be the first type of signal line 1031, and the second power signal line VSS of the other signal line group 103z can be the second type of signal line 1032. In order to ensure the stability and reliability of the second power signal transmission, the second power signal lines VSS of the two signal line groups 103z can be connected by a connection signal line extending along the first direction X.

[0125] Optionally, in the signal line group 103z including the first power signal line VDD and the second power signal line VSS, one of the first power signal line VDD and the second power signal line VSS is the first type of signal line 1031, and the other is the second type of signal line 1032.

[0126] As an optional implementation, referring to Figure 5 , the first signal line group 103z1 and the second signal line group 103z2 both include the first power signal line VDD and the second power signal line VSS. The display panel 100 further includes a first connection signal line L1 and a second connection signal line L2 extending along the first direction X.

[0127] One end of the first connection signal line L1 is connected to the first power signal line VDD in the first signal line group 103z1, and the other end is connected to the first power signal line VDD in the second signal line group 103z2. One end of the second connection signal line L2 is connected to the second power signal line VSS in the first signal line group 103z1, and the other end is connected to the second power signal line VSS in the second signal line group 103z2.

[0128] For example, the second power signal line VSS in the first signal line group 103z1 is closer to the second signal line group 103z2 than the first power signal line VDD in the first signal line group 103z1. The first power signal line VDD in the second signal line group 103z2 is closer to the first signal line group 103z1 than the second power signal line VSS in the second signal line group 103z2. That is, the first power signal line VDD and the second power signal line VSS included in the first signal line group 103z1 and the first power signal line VDD and the second power signal line VSS included in the second signal line group 103z2 can be arranged in the following order: the first power signal line VDD in the first signal line group 103z1, the second power signal line VSS in the first signal line group 103z1, the first power signal line VDD in the second signal line group 103z2, and the second power signal line VSS in the second signal line group 103z2. That is, the second power signal line VSS in the first signal line group 103z1 and the first power signal line VDD in the second signal line group 103z2 can be located between the first power signal line VDD in the first signal line group 103z1 and the second power signal line VSS in the second signal line group 103z2.

[0129] In order to increase the area of the transparent display region, the two power signal lines located in the middle can be segmented signal lines (i.e., the first type of signal line 1031) including transparent segments. That is, the second power signal line VSS in the first signal line group 103z1 and the first power signal line VDD in the second signal line group 103z2 are both first type of signal lines 1031. In addition, the first power signal line VDD in the first signal line group 103z1 and the second power signal line VSS in the second signal line group 103z2 are both second type of signal lines 1032.

[0130] Reference Figure 5 As can be seen, the first transparent display region A1 between the pixel units 102 arranged along the second direction Y and adjacent to each other can be connected with the second transparent display region A2 between the pixel unit groups 102z arranged along the first direction X and adjacent to each other, further increasing the area of the transparent display region, improving the overall transmittance of the display panel 100, and ensuring the transparent display effect of the display panel 100. In addition, the display effect of the display panel 100 under the off-state effect can be further improved.

[0131] It should be noted that since the material of the gate signal line scan included in the display panel 100 can be a metal material (not a light-transmitting material), a plurality of gate signal lines extending along the first direction X will divide the transparent display area between the pixel unit groups 102z arranged along the first direction X and adjacent to each other into a plurality of sub-transparent display areas arranged along the second direction Y. Correspondingly, the communication of the first transparent display area and the second transparent display area described above can mean that the second transparent display area A2 can be in communication with the nearest first transparent display area A1.

[0132] Optionally, the first connection signal line L1 and the second connection signal line L2 are needed to be arranged in the display panel 100, mainly because the first power signal line VDD or the second power signal line VSS of the signal line group 103z is arranged as the first type of signal line 1031. In this case, in order to ensure the stability and reliability of the first connection signal line L1 and the second connection signal line L2 in transmitting the power signal, the material of the first connection signal line L1 and the second connection signal line L2 can be a metal material with a small sheet resistance.

[0133] Generally, the light-transmitting property of a metal material is poor, and therefore, in order to reduce the influence of the arrangement of the first connection signal line L1 and the second connection signal line L2 on the transparent display, the first connection signal line L1 and the second connection signal line L2 can be arranged near the gate signal line. For example Figure 5 two gate signal lines scan are shown, the first connection signal line L1 can be located at the lower part of the first gate signal line scan1, and the second connection signal line L2 can be located at the upper part of the second gate signal line scan2. Moreover, the distance between the first connection signal line L1 and the first gate signal line scan1, and the distance between the second connection signal line L2 and the second gate signal line scan2 are both small. In this case, the upper and lower boundaries of the second transparent display area A2 can be defined by the first connection signal line L1 and the second connection signal line L2.

[0134] As another optional implementation manner, referring to Figure 6 , the first signal line group 103z1 includes the first power signal line VDD, and the second signal line group 103z2 includes the first power signal line VDD and the second power signal line VSS. Alternatively, it can be understood that the second power signal line VSS of the first signal line group 103z1 and the second signal line group 103z2 is shared, and this shared second power signal line VSS is arranged at the position of the second signal line group 103z2.

[0135] In Figure 6In the embodiment, the first power signal line VDD in the second signal line group 103z2 is closer to the first signal line group 103z1 than the second power signal line VSS in the second signal line group 103z2. In this case, the first power signal line VDD included in the second signal line group 103z2 is the first type signal line 1031, and the second power signal line VSS included in the second signal line group 103z2 is the second type signal line 1032. In this case, in order to ensure the stability and reliability of the first power signal transmitted by the first power signal line VDD, the display panel further includes a first connection signal line L1 extending along the first direction X. One end of the first connection signal line L1 is connected to the first power signal line VDD in the first signal line group 103z1, and the other end is connected to the first power signal line VDD in the second signal line group 103z2.

[0136] Reference Figure 6 As can be seen, the first transparent display area A1 between the pixel units 102 arranged along the second direction Y and adjacent to each other can be in communication with the second transparent display area A2 between the pixel unit groups 102z arranged along the first direction X and adjacent to each other, further improving the area of the transparent display area and ensuring the transparent display effect of the display panel 100.

[0137] It should be noted that since the material of the gate signal line scan included in the display panel 100 can be a metal material (not a light-transmitting material), a plurality of gate signal lines extending along the first direction X will divide the transparent display area between the pixel unit groups 102z arranged along the first direction X and adjacent to each other into a plurality of sub-transparent display areas arranged along the second direction Y. Correspondingly, the communication between the first transparent display area A1 and the second transparent display area A2 described above can mean that the second transparent display area A2 can be in communication with the nearest first transparent display area A1.

[0138] Optionally, the reason why the first connection signal line L1 needs to be provided in the display panel 100 is that the first power signal line VDD in the first signal line group 103z1 of the two adjacent signal line groups 103z is provided as the first type signal line 1031. In this case, in order to ensure the stability and reliability of the first connection signal line L1 in transmitting the first power signal, the material of the first connection signal line L1 can be a metal material with a smaller sheet resistance.

[0139] Generally, the light transmission of a metal material is poor. Therefore, in order to reduce the influence of the provision of the first connection signal line L1 on the transparent display, the first connection signal line L1 can be provided in a region close to the gate signal line. For example Figure 6As shown in FIG. 1, two gate signal lines are shown, the first connection signal line L1 can be located in the upper part of the second gate signal line scan2. And the distance between the first connection signal line L1 and the second gate signal line scan is small. In this case, the upper and lower boundaries of the second transparent display area A2 can be defined by the first gate signal line scan1 and the first connection signal line L1.

[0140] Reference Figure 3 As can be seen, the display panel 100 includes a pixel unit 102 layer. The pixel unit 102 layer includes a pixel circuit layer M and a light emitting unit layer N. The pixel circuit layer M includes a pixel circuit 1021 of a plurality of pixel units 102, and the light emitting unit layer N includes a light emitting unit 1022 of a plurality of pixel units 102.

[0141] Optionally, the pixel circuit layer M includes, in order from the direction away from the substrate substrate 101, a light-transmitting conductive layer m1, a light-shielding conductive layer (SHL) m2, a buffer layer (buffer) m3, an active layer (poly) m4, a gate insulating layer (gate insulator, GI) m5, a gate layer m6, a passivation layer (PVX) m7, and a planarization layer (PLN) m8. Optionally, the material of the light-transmitting conductive layer m1 can be indium tin oxide (ITO). The material of the planarization layer m8 can be resin.

[0142] The light emitting unit layer N includes, in order from the direction away from the substrate substrate 101, an anode layer n1, a pixel definition layer (PDL) n2, a light emitting functional layer n3, and a cathode layer n4.

[0143] The first line segment 10311 can be located in the light-shielding conductive layer m2, and the second line segment 10312 can be located in the light-transmitting conductive layer m1. Since no insulating layer is provided between the light-shielding conductive layer m2 and the light-transmitting conductive layer m1, the second line segment 10312 and the first line segment 10311 can be electrically connected by overlapping and directly contacting.

[0144] The active layer m4 includes an active pattern m41 of a thin film transistor, and the gate layer m6 includes a gate, a source and a drain of a thin film transistor. The gate is located between the source and the drain, and the source and the drain are electrically connected through a via in the gate insulating layer m5 and the active pattern. Figure 3In the embodiment, the gate, the source and the drain of the thin film transistor are located in the same layer, so that the number of film layers of the display panel 100 can be saved, and the manufacturing process of the display panel 100 can be simplified. Of course, the source and the drain of the thin film transistor can be located in different layers from the gate of the thin film transistor, and the embodiment of the present application does not limit this.

[0145] The material of the anode layer n1 includes a light-transmitting material, for example, the material of the anode layer n1 can include indium tin oxide (ITO). The anode layer n1 includes an anode 10221 of the light-emitting unit 1022 of the plurality of pixel units 102. The pixel defining layer n2 includes a plurality of pixel openings n21 for exposing at least part of the anode 10221. The light-emitting functional layer n3 includes a light-emitting part 10222 of the light-emitting unit 1022 of the plurality of pixel units 102, which can be located in the pixel opening n21 and connected with at least part of the anode 10221 exposed by the pixel opening n21. The cathode layer n4 includes a cathode 10223 of the light-emitting unit 1022 of the plurality of pixel units 102, which is connected with the light-emitting part 10222. Optionally, the cathodes 10223 of the light-emitting unit 1022 of the plurality of pixel units 102 can be connected in series, that is, the cathode layer n4 can be an integral film layer.

[0146] Optionally, the light-emitting functional layer n3 can include an electron functional layer and a hole functional layer in addition to the light-emitting part 10222 of the light-emitting unit 1022 of the plurality of pixel units 102. The electron functional layer can include an electron injection layer (EIL), an electron transport layer (ETL) and an electron blocking layer (EBL), etc. The hole functional layer can include a hole injection layer (HIL), a hole transport layer (HTL) and a hole blocking layer (HBL), etc. Among them, the electron functional layer and the hole functional layer can be an integral film layer, that is, an integral layer covering the substrate 101.

[0147] Reference Figure 1 , and Figures 4 to 6It can be seen that the anode 10221 in the light emitting unit 1022 in each pixel unit 102 includes a first anode part 102211 and a second anode part 102212 arranged at intervals. The area where the first anode part 102211 in the light emitting unit 1022 is located and the area where the second anode part 102212 is located can both be the light emitting area of the light emitting unit 1022. The display panel 100 further includes a maintenance architecture 104. The maintenance architecture 104 includes a first maintenance part 1041 and a second maintenance part 1042.

[0148] The first maintenance part 1041 is electrically connected with the pixel circuit 1021, for example, the first maintenance part 1041 can be electrically connected with the second node J2 in the pixel circuit 1021. The second maintenance part 1042 is electrically connected with the first maintenance part 1041. The first end of the second maintenance part 1042 is electrically connected with the first anode part 102211, and the second end of the second maintenance part 1042 is electrically connected with the second anode part 102212. The first end and the second end of the second maintenance part 1042 are respectively located on the two sides of the position where the second maintenance part 1042 and the first maintenance part 1041 are electrically connected. The first maintenance part 1041 is located on the light-transmitting conductive layer m1, and the second maintenance part 1042 is located on the anode layer n1.

[0149] In the embodiment of the present application, the anode 10221 of the light emitting unit 1022 of the pixel unit 102 is divided into the first anode part 102211 and the second anode part 102212, and the maintenance architecture 104 is arranged, so that when the area where a certain anode part of the first anode part 102211 and the second anode part 102212 of the light emitting unit 1022 is located emits light abnormally, the connection between the maintenance architecture 104 and the anode part can be directly cut off, and then the abnormal display of the display panel 100 can be avoided. In this case, the area where the other anode part of the light emitting unit 1022 is located can display normally, and the reliability of the display of the display panel 100 can be ensured.

[0150] In addition, since the materials of the light-transmitting conductive layer m1 and the anode layer n1 both include light-transmitting materials, the first maintenance part 1041 of the maintenance architecture 104 is arranged on the light-transmitting conductive layer m1, and the second maintenance part 1042 is arranged on the anode layer n1, so that the influence of the arrangement of the maintenance architecture 104 on the transparent display of the display panel 100 can be avoided.

[0151] Optionally, since the second maintenance part 1042, the first anode part 102211 and the second anode part 102212 are all electrically connected, and the second maintenance part 1042, the first anode part 102211 and the second anode part 102212 are all located on the anode layer n1, the second maintenance part 1042, the first anode part 102211 and the second anode part 102212 can be an integrated structure.

[0152] In the embodiment of the present application, the repair architecture 104 further includes a connecting portion 1043 located at the gate layer m6. The connecting portion 1043 has a first overlapping area with the first repair portion 1041 on the substrate 101, and has a second overlapping area with the second repair portion 1042 on the substrate 101. The first overlapping area and the second overlapping area can not overlap.

[0153] Optionally, the connecting portion 1043 and the first repair portion 1041 are electrically connected through the first via hole K1 in the gate insulating layer m5 and the buffer layer m3 in the first overlapping area, and the connecting portion 1043 and the second repair portion 1042 are electrically connected through the second via hole K2 in the passivation layer m7 and the planarization layer m8 in the second overlapping area.

[0154] Since the connecting portion 1043 is located at the gate layer m6, and the material of the gate layer m6 is usually a non-transparent material, in order to reduce the influence of the setting of the connecting portion 1043 on the transparent display, the size of the connecting portion 1043 can be reduced as much as possible on the basis of realizing the electrical connection of the first repair portion 1041 and the second repair portion 1042. For example, the size of the connecting portion 1043 can be slightly larger than the total size of the first via hole K1 and the second via hole K2.

[0155] The embodiment of the present application takes the scheme shown in Figure 4 as an example to introduce each film layer. In combination with Figures 7 to 19 , the target power supply trace B included in the first power supply signal line VDD and the second power supply signal line VSS includes a first power supply line portion B1 and a second power supply line portion B2 located at the light-shielding conductive layer m2. In addition, the target power supply trace B further includes a third power supply line portion B3 located at the gate layer m6. Figures 7 to 19 Taking the first power supply signal line VDD and the second power supply signal line VSS as the target power supply trace B as an example.

[0156] The first power line portion B1 and the second power line portion B2 each extend in the second direction Y, and the first power line portion B1 and the second power line portion B2 have a gap in the second direction Y. A projection of the third power line portion B3 on the substrate 101 at least partially overlaps a projection of the first power line portion B1 on the substrate 101. The third power line portion B3 is electrically connected to the first power line portion B1 through a via in the gate insulating layer m5 and the buffer layer m3. Further, a projection of the third power line portion B3 on the substrate 101 at least partially overlaps a projection of the second power line portion B2 on the substrate 101, and the third power line portion B3 is electrically connected to the second power line portion B2 through a via in the gate insulating layer m5 and the buffer layer m3. That is, the target power line B can be routed on the light-shielding conductive layer m2 and the gate layer m6.

[0157] Optionally, the gap G between the first power line portion B1 and the second power line portion B2 of the target power line B is needed to avoid the first repair portion 1041 of the repair structure 104.

[0158] For example, the storage capacitor Cst included in the pixel circuit 1021 includes a first capacitor plate Cst1 on the light-shielding conductive layer m2 and a second capacitor plate Cst2 on the gate layer m6. A projection of the second capacitor plate Cst2 on the substrate 101 at least partially overlaps a projection of the first capacitor plate Cst1 on the substrate 101. Since the first repair portion 1041 of the repair structure 104 is connected to the second node J2 of the pixel circuit 1021, the first repair portion 1041 can be connected to the first capacitor plate Cst1 of the storage capacitor.

[0159] Reference Figures 7 to 19 The first repair portion 1041 is a strip structure extending in the first direction X, and a first end of the first repair portion 1041 (the light-transmitting conductive layer m1) overlaps and is in contact with the first capacitor plate Cst1 (the light-shielding conductive layer m2). A second end of the first repair portion 1041 is located on a side of the target power line B away from the first capacitor plate Cst1.

[0160] For example Figure 4As shown in FIG. 1, a plurality of repair structures 104 are shown, and a part of the repair structures 104 are arranged on the side of the first power signal line VDD away from the second power signal line VSS, and another part of the repair structures 104 are arranged on the side of the second power signal line VSS away from the first power signal line VDD. The second end of the first repair part 1041 in the repair structure 104 on the side of the first power signal line VDD away from the second power signal line VSS can be located on the side of the first power signal line VDD away from the first capacitor plate Cst1. The second end of the first repair part 1041 in the repair structure 104 on the side of the second power signal line VSS away from the first power signal line VDD can be located on the side of the second power signal line VSS away from the first capacitor plate Cst1.

[0161] In this case, in order to avoid the first repair part 1041 of the repair structure 104 and the target power trace B intersecting and causing a short circuit, the interval G between the first power line part B1 and the second power line part B2 of the first repair part 1041 passing through the target power trace B can be made. That is, at least part of the first repair part 1041 can be located on the interval G between the first power line part B1 and the second power line part B2 in the second direction Y.

[0162] In the embodiments of the present application, the plurality of pixel units 102 can include pixel units 102 of a first color (hereinafter referred to as first pixel units), pixel units 102 of a second color (hereinafter referred to as second pixel units), pixel units 102 of a third color (hereinafter referred to as third pixel units), and pixel units 102 of a fourth color (hereinafter referred to as fourth pixel units). The first color, the second color, the third color, and the fourth color are different from each other.

[0163] For example, the first pixel unit can be a red pixel unit (red, R), and the first pixel unit 102 can be used to emit red light. The second pixel unit can be a green pixel unit (green, G), and the second pixel unit can be used to emit green light. The third pixel unit can be a blue pixel unit (blue, B), and the third pixel unit can be used to emit blue light. The fourth pixel unit can be a white pixel unit (white, W), and the fourth pixel unit can be used to emit white light.

[0164] Optionally, the display panel 100 includes a first pixel unit 102, a second pixel unit 102, a third pixel unit 102, and a fourth pixel unit 102. Optionally, the pixel unit group 102z described in the embodiments of the present application can include a plurality of light-emitting pixels arranged along the second direction Y. Each light-emitting pixel can include two columns of pixel units 102 arranged along the first direction X, and two rows of pixel units arranged along the second direction Y.

[0165] For example, in Figure 1 In each luminescent pixel F, white pixel units W and green pixel units G are arranged along a first direction X, and red pixel units R and blue pixel units B are arranged along the first direction X. Furthermore, in each luminescent pixel F, white pixel units W and red pixel units R are arranged along a second direction Y, and green pixel units G and blue pixel units B are arranged along the second direction Y. Alternatively, it can be understood that the four pixel units 102 included in the luminescent pixel F can be arranged in a 2x2 grid, where the pixel unit 102 in the first row and first column is the white pixel unit W, the pixel unit 102 in the first row and second column is the green pixel unit G, the pixel unit 102 in the second row and first column is the red pixel unit R, and the pixel unit 102 in the second row and second column is the blue pixel unit B.

[0166] Optionally, each color pixel unit 102 can be provided with a corresponding data signal line. That is, there can be multiple data signal lines for each pixel unit group 102z. For example, there can be four data signal lines for each pixel unit group 102z: the data signal line (dataR) corresponding to the red pixel unit R, the data signal line (dataG) corresponding to the green pixel unit G, the data signal line (dataB) corresponding to the blue pixel unit B, and the data signal line (dataW) corresponding to the white pixel unit W.

[0167] Since there are a large number of data signal lines corresponding to each pixel unit group 102z, some data signal lines will be located on one side of the two sides of the light-emitting pixel in the layout (these data signal lines will be referred to as the first target data signal line dataM1 in the following text), and other data signal lines will be located between the two columns of pixel units 102 in the light-emitting pixel F (these data signal lines will be referred to as the second target data signal line dataM2 in the following text).

[0168] Example, reference Figure 9 The orthographic projection of the first target data signal line dataM1 on the substrate 101 is located between the orthographic projection of the first end of the first repair unit 1041 on the substrate 101 and the orthographic projection of the second end of the first repair unit 1041 on the substrate 101. That is, the first repair unit 1041 is positioned across the first target data signal line dataM1.

[0169] In this case, in order to avoid the first repair portion 1041 affecting the first target data signal line dataM1, the first target data signal line dataM1 can include at least the first data line portion C1 and the second data line portion C2 of the light-transmissive conductive layer m1, and the third data line portion C3 of the gate layer m6. The first data line portion C1 and the second data line portion C2 extend along the second direction Y, and the first data line portion C1 and the second data line portion C2 have a spacing H in the second direction Y. The third data line portion C3 has a projection on the substrate 101 that at least partially overlaps a projection of the first data line portion C1 on the substrate 101, and the third data line portion C3 is electrically connected to the first data line portion C1 through a via in the gate insulating layer m5 and the buffer layer m3. The third data line portion C3 also has a projection on the substrate 101 that at least partially overlaps a projection of the second data line portion C2 on the substrate 101, and the third data line portion C3 is electrically connected to the second data line portion C2 through a via in the gate insulating layer m5 and the buffer layer m3. At least part of the first repair portion 1041 is located in the spacing H between the first data line portion C1 and the second data line portion C2 in the second direction Y.

[0170] That is, the first target data signal line dataM1 can be routed to the gate layer m6 at a position overlapping the first repair portion 1041, thereby avoiding short circuiting between the first repair portion 1041 and the first target data signal line dataM1.

[0171] In the embodiments of the present application, with reference to Figure 9 , the second target data signal line dataM2 has a projection on the substrate 101 that has a spacing from a projection of the first repair portion 1041 on the substrate 101 in the first direction X. That is, the projection of the first repair portion 1041 on the substrate 101 and the projection of the second target data signal line dataM2 on the substrate 101 do not overlap. In this case, the second target data signal line dataM2 can be routed without layer switching to the gate layer m6, but can be located in the light-transmissive conductive layer m1.

[0172] With reference to Figure 9The number of data signal lines corresponding to each pixel unit group 102z can be four. The data signal line (dataW) corresponding to the white pixel unit W is located between the first power signal line VDD and the first column of pixel units 102, the data signal line (dataR) corresponding to the red pixel unit R and the data signal line (dataG) corresponding to the green pixel unit G are located between the first column of pixel units 102 and the second column of pixel units 102, and the data signal line (dataB) corresponding to the blue pixel unit B is located between the second column of pixel units 102 and the second power signal line VSS. In this case, the data signal line (dataW) and the data signal line (dataB) can be the first target data signal line dataM1, and the data signal line (dataR) and the data signal line (dataG) can be the second target data signal line dataM2.

[0173] In the embodiments of the present application, referring to Figure 9 The orthogonal projection of the sensing signal line sense included in the plurality of signal lines 103 on the substrate 101 and the orthogonal projection of the first repair unit 1041 on the substrate 101 have a gap in the first direction X. That is, the orthogonal projection of the sensing signal line on the substrate 101 and the orthogonal projection of the first repair unit 1041 on the substrate 101 do not overlap. In this case, the sensing signal line sense can not need to be routed to the gate layer m6, but can be located in the light-transmitting conductive layer m1.

[0174] In the embodiments of the present application, since the data signal line and the sensing signal line are both used for signal transmission, in order to reduce the resistance of signal transmission, the data signal line and the sensing signal line can be double-layer routed using the light-shielding conductive layer m2 and the light-transmitting conductive layer m1.

[0175] Optionally, the first data line part C1 and the second data line part C2 included in the first target data signal line dataM1, and the second target data signal line dataM2 can also be located in the light-shielding conductive layer m2 in addition to being located in the light-transmitting conductive layer m1.

[0176] For example, the first data line portion C1, the second data line portion C2, and the second target data signal line dataM2 are located at least partially overlapping the orthogonal projection of the portion of the light-shielding conductive layer m2 on the substrate 101 and the orthogonal projection of the pixel unit 102 on the substrate 101, and are not located between the pixel units 102 arranged adjacent to each other in the second direction Y. Also, the first data line portion C1, the second data line portion C2, and the second target data signal line dataM2 are located at least partially overlapping the orthogonal projection of the portion of the light-transmitting conductive layer m1 on the substrate 101 and the orthogonal projection of the pixel unit 102 on the substrate 101, and are located between the pixel units 102 arranged adjacent to each other in the second direction Y. Alternatively, it can be understood that the portion of the first data line portion C1, the second data line portion C2, and the second target data signal line dataM2 located in the pixel region can be provided as a double-layer wiring of the light-shielding conductive layer m2 and the light-transmitting conductive layer m1, and the portion located in the non-pixel region can be provided as a single-layer wiring of the light-transmitting conductive layer m1.

[0177] Optionally, the sensing signal line sense is located in the light-shielding conductive layer m2 in addition to the light-transmitting conductive layer m1. For example, the portion of the sensing signal line sense located in the light-shielding conductive layer m2 is located at least partially overlapping the orthogonal projection of the portion of the light-shielding conductive layer m2 on the substrate 101 and the orthogonal projection of the pixel unit 102 on the substrate 101, and is not located between the pixel units 102 arranged adjacent to each other in the second direction Y. Also, the portion of the sensing signal line sense located in the light-transmitting conductive layer m1 is located at least partially overlapping the orthogonal projection of the portion of the light-transmitting conductive layer m1 on the substrate 101 and the orthogonal projection of the pixel unit 102 on the substrate 101, and is located between the pixel units 102 arranged adjacent to each other in the second direction Y. Alternatively, it can be understood that the portion of the sensing signal line sense located in the pixel region can be provided as a double-layer wiring of the light-shielding conductive layer m2 and the light-transmitting conductive layer m1, and the portion located in the non-pixel region can be provided as a single-layer wiring of the light-transmitting conductive layer m1.

[0178] In combination Figure 1 , and Figures 4 to 19The display panel 100 further comprises a switching architecture 105. The switching architecture 105 comprises a first switching part 1051 located at the light-transmitting conductive layer m1, a second switching part 1052 located at the gate layer m6, and a third switching part 1053 located at the anode layer n1. The first switching part 1051 is in a strip structure extending along the first direction X, a first end of the first switching part 1051 is electrically connected with the second power signal line VSS in the display panel 100, and a second end of the first switching part 1051 is electrically connected with the second switching part 1052 through a via in the gate insulating layer m5 and the buffer layer m3. The third switching part 1053 is electrically connected with the second switching part 1052 through a via in the planarization layer m8 and the passivation layer m7, and the third switching part 1053 is electrically connected with the cathode layer n4. That is, the second power signal line VSS and the cathode layer n4 can be electrically connected through the switching architecture 105 in the embodiments of the present application.

[0179] Since the first switching part 1051 of the switching architecture 105 is located at the light-transmitting conductive layer m1, the transparent display of the display panel 100 can be less affected by the switching architecture 105.

[0180] Optionally, the planarization layer m8 at the position where the third switching part 1053 and the second switching part 1052 are electrically connected can be a hollow area, so that the third switching part 1053 can be directly electrically connected with the second switching part 1052 through the hollow area of the planarization layer m8 and the via m71 of the passivation layer m7.

[0181] In the embodiments of the present application, referring to Figure 10 The active layer m4 comprises an active pattern m41 of the first transistor T1, an active pattern m41 of the second transistor T2, and an active pattern m41 of the third transistor T3. The size and shape of the active pattern m41 of different transistors can be different, and the channel width-length ratio of the transistors can be determined according to the actual product requirements, so as to determine the size and shape of the active pattern m41 of the transistors. The size and shape of the active pattern m41 of each transistor are not limited in the embodiments of the present application.

[0182] In the embodiments of the present application, referring to Figure 20 The pixel defining layer n2 can be a hollow area except for the pixel opening n21. The orthogonal projection of the hollow area on the substrate 101 can cover the orthogonal projection of the third switching part 1053 on the substrate 101. In this case, the cathode layer n4 can be directly connected with the third switching part 1053 located at the anode layer n1. Optionally, Figure 20 The passivation layer (via), the planarization layer, the anode layer, and the pixel defining layer shown in the above embodiments can be applied to the schemes of all the embodiments of the present application.

[0183] Optionally, the anode layer n1 includes a first material layer, a second material layer and a third material layer which are stacked in a direction away from the substrate 101. The first material layer and the third material layer can be made of the same material, and the material of the second material layer is different from the materials of the first material layer and the third material layer. The etching rate of the material of the first material layer and the third material layer is less than the etching rate of the material of the second material layer. Thus, in the process of etching to form the third transfer part 1053, the first material layer, the second material layer and the third material layer can form an undercut structure as shown in FIG. 1. Figure 21

[0184] Optionally, the materials of the first material layer and the third material layer can be titanium (Ti), and the material of the second material layer can be aluminum (Al).

[0185] Referring to Figure 21 , the third transfer part 1053 includes a first part 10531 located in the first material layer, a second part 10532 located in the second material layer and a third part 10533 located in the third material layer. The boundary of the second part 10532 is inwardly recessed relative to the boundaries of the first part 10531 and the third part 10533. Thus, when the electron functional layer and the hole functional layer in the light-emitting functional layer n3 are formed by EL (electron layer and hole layer are marked by EL), the electron functional layer and the hole functional layer can be in a broken state at the boundary of the third part 10533. Thus, the cathode layer n4 can be electrically connected to the second part 10532 of the third transfer part 1053 through the broken position of the electron functional layer and the hole functional layer. Figure 21

[0186] In the embodiment of the present application, since the first transfer part 1051 of the transfer architecture 105 is located in the light-transmitting conductive layer m1, the setting of the transfer architecture 105 can reduce the influence on transparent display, and the transparent display effect of the display panel 100 can be ensured.

[0187] The present application takes the scheme shown in Figure 6 as an example to introduce various film layers. In combination with Figures 22 to 35 , a partial structure of the first signal line group 103z1 which includes the first power signal line VDD and does not include the second power signal line VSS is shown. In this scheme, since the first signal line group 103z1 does not include the second power signal line VSS, the transfer architecture 105 does not need to be arranged at the position of the pixel unit group 102z corresponding to the first signal line group 103z1. The explanation of other features except the transfer architecture 105 can refer to the above-mentioned embodiments, which will not be described herein again.

[0188] From Figure 35 ​​As can be seen, the first power signal line VDD in the first signal line group 103z1 is connected through the first connection signal line L1 and the first power signal line VDD in the second signal line group 103z2. The first connection signal line L1 can be located at the gate layer.

[0189] In the embodiments of the present application, the shape of each via can be rectangular. Of course, it can also be circular, elliptical, polygonal, and the like. The embodiments of the present application do not make specific limitations on the shape of the via.

[0190] In the embodiments of the present application, the process of preparing the substrate 101 to the pixel definition layer n2 in the display panel 100 can include:

[0191] 1. Obtain a substrate. The substrate can be a transparent substrate, which can be a glass substrate or a flexible substrate.

[0192] 2. Form a light-transmitting conductive film on one side of the substrate, and perform a patterning process on the light-transmitting conductive film using a first mask to obtain a light-transmitting conductive layer. The patterning process includes photoresist coating, exposure, development, etching, and photoresist removal.

[0193] 3. Form a light-shielding conductive film on the side of the light-transmitting conductive layer away from the substrate, and perform a patterning process on the light-shielding conductive film using a second mask to obtain a light-shielding conductive layer. The second mask and the first mask are different masks, but no insulating layer is provided between the light-shielding conductive layer and the light-transmitting conductive layer, and they can be directly electrically connected.

[0194] 4. Form a buffer film on the side of the light-shielding conductive layer away from the substrate.

[0195] 5. Form an active film on the side of the buffer film away from the substrate, and perform a patterning process on the active film using a third mask to obtain an active layer.

[0196] 5. Form a gate insulating film on the side of the active layer away from the substrate using a deposition process.

[0197] 6. Perform a process on the gate insulating film and the buffer film using a fourth mask to obtain a gate insulating layer and a buffer layer. The gate insulating layer and the buffer layer can include a via.

[0198] 7. Form a gate film on the side of the gate insulating layer away from the substrate, and perform a patterning process on the gate film using a fifth mask to obtain a gate layer.

[0199] 8. Form a passivation film on the side of the gate layer away from the substrate using a deposition process.

[0200] 9. Forming a planar film on the side of the passivation film away from the substrate base by a deposition process.

[0201] 10. Patterning the planar film by a sixth mask to obtain a planar layer.

[0202] 11. Patterning the passivation film by a seventh mask to obtain a passivation layer.

[0203] 12. Forming an anode film on the side of the passivation layer away from the substrate base, and patterning the anode film by an eighth mask to obtain an anode layer.

[0204] 13. Forming a pixel defining film on the side of the anode layer away from the substrate base, and patterning the pixel defining film by a ninth mask to obtain a pixel defining layer.

[0205] That is, the process of preparing the substrate base 101 to the pixel defining layer n2 in the display panel 100 can be: light-transmitting conductive layer → light-blocking conductive layer → buffer film → active layer → depositing gate insulating film → forming via hole of gate insulating layer and buffer layer → gate layer → depositing passivation film → depositing planar film → planar layer → passivation layer → anode layer → pixel defining layer.

[0206] In summary, the display panel provided by the embodiments of the present application includes a substrate base, a plurality of pixel units, and a plurality of signal lines. The first type of signal lines in the plurality of signal lines are arranged in the second line segment of the non-pixel region and are made of transparent material, so that the transparent display area of the display panel can be increased, and the transparent display effect can be improved.

[0207] Figure 36 is a structural schematic diagram of a display device provided by an embodiment of the present application. Referring to Figure 36 , the display device includes a power supply component 200 and a display module 100 provided by the above-described embodiments. The power supply component 200 and the display module 100 are connected and used to supply power to the display module 100.

[0208] Optionally, the display device can be an organic light-emitting diode (OLED) display device. The display device can be any appropriate display device, including but not limited to a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a vehicle-mounted navigation device, and an electronic book, or any product or component having a display function.

[0209] Since the display device can have substantially the same technical effects as the display panel described in the above embodiments, for the purpose of brevity, the technical effects of the display panel are not described again here.

[0210] The terminology used in the description of the implementations herein is for the purpose of describing particular embodiments only and is not intended to limit the application. Unless otherwise defined, all technical and scientific terms used herein are intended to have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0211] The description of the embodiments of the application part describes a plurality of embodiments, but the description is exemplary, rather than limiting, and it will be apparent to those of ordinary skill in the art that more embodiments and implementations can be within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Unless specifically intended otherwise, any feature or element of any embodiment can be used with any other feature or element of any other embodiment, or in any other embodiment, whether or not that feature or element is specifically disclosed in that other embodiment.

[0212] The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed herein can also be combined with any conventional feature or element to form a unique application of the presently claimed application that is not specifically disclosed. Any feature or element of any embodiment can also be combined with features or elements from other application schemes to form another unique application of the presently claimed application that is not specifically disclosed. Thus, it should be understood that any feature shown and / or discussed in the specification can be implemented alone or in any suitable combination. Accordingly, the embodiments are not to be restricted, except as by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the attached claims.

[0213] Furthermore, in describing representative embodiments, the specification can have presented the method and / or process as a particular sequence of steps. However, to the extent that the method or process depends on more than one step, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps can be possible, and are within the scope of the application. Thus, the particular order of the steps set forth in the specification is not an limitation on the claims. Further, the claims should not be limited to the order of execution of the steps, as the order of execution of the steps can vary, and still remain within the scope of the application.

[0214] In the drawings, the size, the thickness or the region of one or more constituent elements is sometimes exaggerated, for the sake of clarity. Furthermore, the drawings are schematically show ideal examples, and the shape, the numerical value, and the like are not limited to the drawings.

[0215] The ordinal numbers "first", "second", "third" and the like in this specification are used to avoid confusion among components, and are not intended to indicate or imply a quantity or order. "A plurality of" in this specification means two or more.

[0216] The thickness range of A to B of a film layer in this specification is used to indicate that the thickness is between A and B, and includes both end point values of A and B.

[0217] In this specification, the words "center", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like that indicate the orientation or positional relationship of components are used to describe the positional relationship of components with reference to the drawings, only for the convenience of describing this specification and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. The positional relationship of the components is appropriately changed according to the direction of the described components. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0218] In this specification, unless explicitly specified and limited otherwise, the terms "connected", "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or communication inside two elements. For those skilled in the art, the meaning of the above terms in this application can be understood according to the situation.

[0219] In this specification, a transistor refers to an element including at least a gate electrode (gate), a drain electrode (drain terminal, drain region or drain), and a source electrode (source terminal, source region or source). The transistor has a channel region between the drain electrode and the source electrode, and current can flow through the drain electrode, the channel region and the source electrode. Note that in this specification, the channel region refers to the region where current mainly flows.

[0220] In this specification, the first electrode of the transistor can be the drain electrode, and the second electrode of the transistor can be the source electrode, or the first electrode of the transistor can be the source electrode, and the second electrode of the transistor can be the drain electrode. In the case of using a transistor with opposite polarity, or in the case of changing the direction of current in the circuit operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in this specification, "source electrode" and "drain electrode" can be exchanged with each other, and "source terminal" and "drain terminal" can be exchanged with each other.

[0221] In this specification, "connection" includes the situation where constituent elements are connected together by a component that has a certain electrical function. There are no particular limitations on the "component that has a certain electrical function," as long as it enables the transmission of electrical signals between the connected constituent elements. Examples of "components that have a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0222] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0223] In this application, "thickness" and "height" refer to the vertical distance between the surface of the film layer away from the substrate and the surface of the film layer closer to the substrate.

[0224] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0225] In this application, "about" means a value that is not strictly limited and allows for process and measurement errors.

[0226] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A display panel, characterized in that, The display panel includes: A substrate, the substrate including a display area; Multiple pixel units are located in the display area. The multiple pixel units form a group of multiple pixel units arranged along a first direction and extending along a second direction. The group of pixel units includes multiple pixel units. The second direction intersects the first direction. In addition, a plurality of signal lines arranged along the first direction and extending along the second direction, the signal lines being electrically connected to the pixel units, the plurality of signal lines including a first type of signal lines, the first type of signal lines including a first line segment and a second line segment electrically connected, the orthographic projection of the first line segment on the substrate and the orthographic projection of the pixel unit on the substrate at least partially overlapping and not located between adjacent pixel units arranged along the second direction, the orthographic projection of the second line segment on the substrate being at least located between adjacent pixel units arranged along the second direction, the material of the second line segment including a light-transmitting material.

2. The display panel according to claim 1, characterized in that, The first type of signal lines includes: data signal lines and sensing signal lines; the plurality of signal lines also includes a first power signal line and a second power signal line; The pixel unit includes a pixel circuit and a light-emitting unit. The pixel circuit includes a plurality of thin-film transistors and at least one storage capacitor. The light-emitting unit includes an anode, a light-emitting portion, and a cathode. The pixel circuit and the anode of the light-emitting unit are electrically connected. The data signal line, the sensing signal line, and the first power signal line are all electrically connected to the thin-film transistor in the pixel circuit. The second power signal line is electrically connected to the cathode in the light-emitting unit. The potential of the first power signal line providing the first power signal to the pixel unit is higher than the potential of the second power signal line providing the second power signal to the pixel unit.

3. The display panel according to claim 2, characterized in that, The plurality of signal lines also includes a second type of signal line, the material of which includes a non-transparent material; The plurality of signal lines constitute a plurality of signal line groups arranged along the first direction and corresponding to the plurality of pixel unit groups; the plurality of signal line groups include a first signal line group and a second signal line group arranged along the first direction and adjacent to each other, and at least one of the first signal line group and the second signal line group includes a first power signal line and a second power signal line. In the signal line group that includes the first power signal line and the second power signal line, one of the first power signal line and the second power signal line is a first type of signal line, and the other is a second type of signal line.

4. The display panel according to claim 3, characterized in that, The first signal line group includes the first power signal line, and the second signal line group includes the first power signal line and the second power signal line; the display panel further includes: a first connection signal line extending along the first direction; One end of the first connection signal line is connected to the first power signal line in the first signal line group, and the other end is connected to the first power signal line in the second signal line group.

5. The display panel according to claim 4, characterized in that, The first power signal line in the second signal line group is closer to the first signal line group than the second power signal line in the second signal line group. Among them, the first power signal line in the second signal line group is a first type of signal line, and the first power signal line in the second signal line group is a second type of signal line.

6. The display panel according to claim 3, characterized in that, Both the first signal line group and the second signal line group include the first power signal line and the second power signal line; the display panel further includes: a first connection signal line and a second connection signal line extending along the first direction; One end of the first connecting signal line is connected to the first power signal line in the first signal line group, and the other end is connected to the first power signal line in the second signal line group. One end of the second connecting signal line is connected to the second power signal line in the first signal line group, and the other end is connected to the second power signal line in the second signal line group.

7. The display panel according to claim 6, characterized in that, The second power signal line in the first signal line group is closer to the second signal line group than the first power signal line in the first signal line group, and the first power signal line in the second signal line group is closer to the first signal line group than the second power signal line in the second signal line group. Among them, the second power signal line in the first signal line group and the first power signal line in the second signal line group are both Class I signal lines, and the first power signal line in the first signal line group and the second power signal line in the second signal line group are both Class II signal lines.

8. The display panel according to any one of claims 1 to 7, characterized in that, The display panel includes: a pixel unit layer, the pixel unit layer including a pixel circuit layer and a light-emitting unit layer, the pixel circuit layer including pixel circuits of the plurality of pixel units, and the light-emitting unit layer including light-emitting units of the plurality of pixel units; The pixel circuit layer includes: a light-shielding conductive layer, a light-transmitting conductive layer, a buffer layer, an active layer, a gate insulating layer, a gate layer, a passivation layer, and a planarization layer, which are sequentially stacked along the direction away from the substrate. The light-emitting unit layer includes: an anode layer, a pixel defining layer, a light-emitting functional layer, and a cathode layer stacked sequentially along a direction away from the substrate. Wherein, the first line segment is located in the light-shielding conductive layer, the second line segment is located in the light-transmitting conductive layer, and the second line segment and the first line segment overlap and are electrically connected in contact; The active layer includes an active pattern of a thin-film transistor, and the gate layer includes a gate, a source, and a drain of a thin-film transistor. The gate is located between the source and the drain, and the source and the drain are electrically connected to the active pattern through vias in the gate insulating layer. The anode layer is made of a light-transmitting material. The anode layer includes the anode of the light-emitting unit of the plurality of pixel units. The pixel defining layer includes a plurality of pixel openings for exposing at least a portion of the anode. The light-emitting functional layer includes the light-emitting portion of the light-emitting unit of the plurality of pixel units. The light-emitting portion is located within the pixel opening and is connected to at least a portion of the anode exposed by the pixel opening. The cathode layer includes the cathode of the light-emitting unit of the plurality of pixel units, and the cathode is connected to the light-emitting portion.

9. The display panel according to claim 8, characterized in that, The anode in the light-emitting unit of each pixel unit includes a first anode portion and a second anode portion arranged at intervals; the display panel further includes a maintenance structure, which includes a first maintenance section and a second maintenance section; The first repair section is electrically connected to the pixel circuit, the second repair section is electrically connected to the first repair section, and the first end of the second repair section is electrically connected to the first anode section, the second end of the second repair section is electrically connected to the second anode section, and the first end and the second end of the second repair section are respectively located on both sides of the position where the second repair section and the first repair section are electrically connected; The first repair section is located in the light-transmitting conductive layer, and the second repair section is located in the anode layer.

10. The display panel according to claim 9, characterized in that, The display panel further includes: a connection portion located on the gate layer, wherein the orthographic projection of the connection portion on the substrate and the orthographic projection of the first repair portion on the substrate have a first overlapping area, and the orthographic projection of the connection portion on the substrate and the orthographic projection of the second repair portion on the substrate have a second overlapping area, wherein the first overlapping area and the second overlapping area do not overlap; The connection portion and the first maintenance portion are electrically connected in the first overlap region through vias in the gate insulating layer and the buffer layer, and the connection portion and the second maintenance portion are electrically connected in the second overlap region through vias in the passivation layer and the planarization layer.

11. The display panel according to claim 9, characterized in that, The target power traces in the first power signal line and the second power signal line of the multiple signal lines include a first power line portion and a second power line portion located in the light-shielding conductive layer, and a third power line portion located in the gate layer. Both the first power line portion and the second power line portion extend along the second direction, and the first power line portion and the second power line portion are spaced apart in the second direction. The orthographic projection of the third power line portion on the substrate and the orthographic projection of the first power line portion on the substrate at least partially overlap. The third power line portion is electrically connected to the first power line portion through vias in the gate insulating layer and the buffer layer. The orthographic projection of the third power line portion on the substrate and the orthographic projection of the second power line portion on the substrate at least partially overlap. The third power line portion is electrically connected to the second power line portion through vias in the gate insulating layer and the buffer layer.

12. The display panel according to claim 11, characterized in that, The pixel circuit includes a storage capacitor comprising a first capacitor plate located in the light-shielding conductive layer and a second capacitor plate located in the gate layer, wherein the orthographic projection of the second capacitor plate on the substrate and the orthographic projection of the first capacitor plate on the substrate at least partially overlap. The first repair section is a strip-shaped structure extending along the first direction. The first end of the first repair section overlaps with the first capacitor plate and is electrically connected. The second end of the first repair section is located on the side of the target power line away from the first capacitor plate. The first repair section is at least partially located at the interval between the first power cord section and the second power cord section in the second direction.

13. The display panel according to claim 12, characterized in that, The plurality of signal lines include a plurality of data signal lines, wherein the orthographic projection of the first target data signal line among the plurality of data signal lines on the substrate is located between the orthographic projection of the first end of the first repair part on the substrate and the orthographic projection of the second end of the first repair part on the substrate. The first target data signal line includes: at least a first data line portion and a second data line portion located in the transparent conductive layer, and a third data line portion located in the gate layer; Both the first data line portion and the second data line portion extend along the second direction, and the first data line portion and the second data line portion are spaced apart in the second direction. The orthographic projection of the third data line portion on the substrate and the orthographic projection of the first data line portion on the substrate at least partially overlap. The third data line portion is electrically connected to the first data line portion through vias in the gate insulating layer and the buffer layer. The orthographic projection of the third data line portion on the substrate and the orthographic projection of the second data line portion on the substrate at least partially overlap. The third data line portion is electrically connected to the second data line portion through vias in the gate insulating layer and the buffer layer. Wherein, at least a portion of the first repair section is located at the interval between the first data line portion and the second data line portion in the second direction.

14. The display panel according to claim 13, characterized in that, The plurality of data signal lines also includes a second target data signal line, wherein the orthographic projection of the second target data signal line on the substrate and the orthographic projection of the first repair part on the substrate are spaced apart in the first direction; The second target data signal line is located at least in the light-transmitting conductive layer.

15. The display panel according to claim 14, characterized in that, The first data line portion, the second data line portion, and the second target data signal line are also located in the light-shielding conductive layer; The orthographic projections of the first data line portion, the second data line portion, and the portion of the second target data signal line located on the light-shielding conductive layer on the substrate and the orthographic projections of the pixel units on the substrate at least partially overlap, and are not located between adjacent pixel units arranged along the second direction. The orthographic projections of the first data line portion, the second data line portion, and the portion of the second target data signal line located on the light-transmitting conductive layer on the substrate and the orthographic projections of the pixel units on the substrate at least partially overlap, and are located between adjacent pixel units arranged along the second direction.

16. The display panel according to any one of claims 9 to 15, characterized in that, The multiple signal lines include a sensing signal line whose orthogonal projection on the substrate and the first repair part's orthogonal projection on the substrate are spaced apart in the first direction; the sensing signal line is located at least in the light-transmitting conductive layer.

17. The display panel according to claim 16, characterized in that, The sensing signal line is also located in the light-shielding conductive layer; The orthographic projection of the portion of the sensing signal line located on the light-shielding conductive layer on the substrate and the orthographic projection of the pixel unit on the substrate at least partially overlap, and are not located between adjacent pixel units arranged along the second direction; The orthographic projection of the portion of the sensing signal line located on the light-transmitting conductive layer on the substrate and the orthographic projection of the pixel unit on the substrate at least partially overlap, and are located between adjacent pixel units arranged along the second direction.

18. The display panel according to claim 8, characterized in that, The display panel further includes: a transition structure, the transition structure including a first transition portion located in the light-transmitting conductive layer, a second transition portion located in the gate layer, and a third transition portion located in the anode layer; The first adapter is a strip-shaped structure extending along the first direction. The first end of the first adapter is electrically connected to the second power signal line in the display panel. The second end of the first adapter is electrically connected to the second adapter through vias in the gate insulating layer and the buffer layer. The third adapter is electrically connected to the second adapter through vias in the planarization layer and the passivation layer. The third adapter is electrically connected to the cathode layer.

19. The display panel according to claim 18, characterized in that, The anode layer includes a first material layer, a second material layer, and a third material layer stacked in a direction away from the substrate, wherein the material etching rates of the first material layer and the third material layer are less than the material etching rate of the second material layer; The third transition portion includes a first portion located in the first material layer, a second portion located in the second material layer, and a third portion located in the third material layer, wherein the boundary of the second portion is recessed relative to the boundaries of the first portion and the third portion; The light-emitting functional layer further includes an electronic functional layer and a hole functional layer. The electronic functional layer and the hole functional layer are integral film layers, and the electronic functional layer and the hole functional layer are in a broken state at the boundary of the third part. The cathode layer is electrically connected to the second part through the broken positions of the electronic functional layer and the hole functional layer.

20. A display device, characterized in that, The display device includes: a power supply component and a display panel as described in any one of claims 1 to 19; The power supply component is connected to the display panel, and the power supply component is used to supply power to the display panel.

Images