Glass substrate structure and chip packaging structure thereof

Abstract

The utility model provides a glass substrate structure and a chip packaging structure, the glass substrate structure comprises at least two glass substrates, the two adjacent glass substrates are electrically connected through a conductive circuit and / or a conductive through hole, the traditional complex process of prefabricating a middle rewiring layer is abandoned, and the production cost is reduced. Through direct stacking without an intermediate layer between glass substrates and interconnection of conductive through holes / circuits, a three-dimensional packaging structure is realized, so that parasitic impedance brought by an intermediate layer is eliminated, interlayer thermal resistance is reduced, and signal transmission efficiency is optimized. Meanwhile, the packaging structure is filled with the conductive paste, the thermal expansion coefficient of the conductive paste is matched with the height of the glass substrate, interface thermal stress is reduced, layering failure under high-temperature circulation is avoided, and the reliability of the packaging structure is improved. And moreover, the conductive circuit and the conductive through hole are filled in a hole groove and slurry manner, so that the defect-free forming of the high-aspect-ratio through hole is realized, and the transmission loss of a high-frequency signal is reduced.

Description

Technical Field

[0001] This utility model relates to the field of chip packaging technology, and in particular to a glass substrate structure and a chip packaging structure. Background Technology

[0002] With the rapid development of 5G communication, artificial intelligence, and high-performance computing, electronic packaging technology is facing severe challenges in miniaturization, high integration, and multifunctionality. 3D integrated packaging, as a core development direction of advanced packaging, faces technical bottlenecks in its key technology, TSV (Through Silicon Via), such as high dielectric loss of substrate materials and significant differences in thermal expansion coefficients. Against this backdrop, packaging technology based on TGV (Through Glass Via) is gradually becoming the core carrier of next-generation 3D packaging due to its superior dielectric properties (dielectric constant reduced by approximately 40%), 3.5-fold increase in signal transmission rate, and 50% reduction in energy consumption.

[0003] However, the existing TGV manufacturing technology has the following technical bottlenecks: (1) Due to the significant difference in thermal expansion coefficients between metal and glass, the interface is prone to delamination under high temperature conditions, which leads to electrical connection failure; (2) Electroplating hole filling technology is difficult to achieve defect-free filling of high aspect ratio through holes, and the problem of voids in the holes is prominent, which seriously affects the high frequency signal transmission performance; (3) Glass substrate bonding depends on the intermediate redistribution layer, which introduces additional thermal resistance and signal loss, restricting the packaging integration density and heat dissipation performance. Utility Model Content

[0004] The main purpose of this application is to propose a glass substrate structure and its chip packaging structure, which aims to solve the problems of interface delamination, high aspect ratio via filling defects, and thermal resistance and signal loss introduced by bonding dependence on intermediate layers in traditional glass via technology due to thermal expansion coefficient mismatch.

[0005] To address the above problems, this application proposes a glass substrate structure, comprising:

[0006] At least two glass substrates having opposing first and second surfaces; each glass substrate is provided with:

[0007] Conductive lines are disposed on the first surface and / or the second surface of the glass substrate;

[0008] A conductive via is provided through the glass substrate, and its end is connected to the conductive line or exposed on the first surface and / or the second surface;

[0009] Two adjacent glass substrates are electrically connected at the bonding interface through conductive lines and / or conductive vias, wherein the conductive lines and conductive vias are filled with conductive paste.

[0010] In one embodiment, each of the conductive lines includes:

[0011] Line grooves are formed on the first and / or second surfaces of the glass substrate;

[0012] A first conductive metal is filled in the line groove and is flush with the surface of the glass substrate forming the line groove.

[0013] In one embodiment, each of the conductive vias includes:

[0014] A via is provided, penetrating the glass substrate, and its end is connected to the conductive line or exposed to the first surface and / or the second surface;

[0015] A second conductive metal is filled in the via and flush with the surface of the glass substrate through which it penetrates.

[0016] In one embodiment, the first conductive metal and the second conductive metal are respectively filled and cured by conductive paste in the corresponding line groove and via.

[0017] In one embodiment, the conductive lines and conductive vias are electrically connected at the bonding interface of adjacent glass substrates to form a three-dimensional interconnect network.

[0018] In one embodiment, the via is a vertical through hole, and the ratio of the hole depth to the hole diameter is greater than 6:1.

[0019] In one embodiment, the thickness of the glass substrate is 1.0 mm, and the diameter of the via is 0.1 mm.

[0020] In one embodiment, the width of the line groove is 0.075 mm and the depth is 0.1 mm.

[0021] In addition, this application also proposes a chip packaging structure, including a chip and a glass substrate structure as described above.

[0022] In one embodiment of a chip packaging structure, the chip is disposed on the side of the glass substrate facing away from the rest of the glass substrate, and the chip is electrically connected to the line groove or conductive via.

[0023] This application comprises at least two glass substrates, each of which is provided with conductive lines and conductive vias. Adjacent glass substrates are electrically connected through conductive lines and / or conductive vias. This eliminates the complex process of traditional pre-fabricated intermediate redistribution layers. By directly stacking glass substrates without intermediate layers and interconnecting them with conductive vias / lines, a three-dimensional encapsulation structure is achieved, thereby eliminating parasitic impedance caused by interlayers, reducing interlayer thermal resistance, and optimizing signal transmission efficiency. Furthermore, this application uses conductive paste filling, whose coefficient of thermal expansion is highly compatible with the glass substrates, reducing interfacial thermal stress, preventing delamination failure under high-temperature cycling, and improving the reliability of the encapsulation structure. Additionally, the conductive lines and conductive vias are formed using a trench + paste filling method, achieving defect-free molding of high aspect ratio vias and reducing high-frequency signal transmission loss. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0025] Figure 1 This is a structural diagram of a glass substrate structure according to the present invention;

[0026] Figure 2 This is a cross-sectional view of a glass substrate structure according to the present invention;

[0027] Figure 3 This is a structural diagram of the production process of a glass substrate structure according to the present invention;

[0028] Figure 4 This is a flowchart illustrating the production process of a glass substrate structure according to this utility model.

[0029] Reference numerals: Glass substrate 01, conductive line 02, conductive through hole 03.

[0030] The realization of the purpose, functional features and advantages of this utility model will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0031] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0032] It should be noted that if the embodiments of this utility model involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0033] Furthermore, if the embodiments of this utility model involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, if the word "and / or" appears throughout the text, it means including three parallel solutions; for example, "A and / or B" includes solution A, solution B, or a solution that simultaneously satisfies A and B. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this utility model.

[0034] This application proposes a glass substrate 01 structure, such as Figure 1 and Figure 2 As shown, it includes:

[0035] At least two glass substrates 01, each having a first surface and a second surface opposite to each other; each glass substrate 01 is provided with:

[0036] Conductive lines 02 are disposed on the first surface and / or the second surface of the glass substrate 01;

[0037] A conductive via 03 is provided through the glass substrate 01, and its end is connected to the conductive line 02 or exposed on the first surface and / or the second surface;

[0038] Two adjacent glass substrates 01 are electrically connected at the bonding interface through conductive lines 02 and / or conductive vias 03, wherein the conductive lines 02 and conductive vias 03 are filled with conductive paste.

[0039] Specifically, electronic devices are increasingly demanding miniaturization, high integration, low power consumption, and high-frequency, high-speed signal transmission. Packaging includes 2D packaging (two-dimensional packaging) and 3D integrated packaging. 2D packaging arranges all chips and interconnect structures horizontally in the same plane, relying on wires on the substrate (such as PCB or organic substrate) to achieve electrical connections between devices. 3D integrated packaging, by vertically stacking chips or substrates, constructs a multi-layered interconnect structure in three-dimensional space. Its core innovation lies in breaking the limitations of the plane and achieving "Z-axis extension."

[0040] Traditional 2D packaging has reached its physical limits, while 3D integrated packaging, through vertically stacking chips or substrates, achieves higher-density functional integration within a limited space, becoming a core technology direction for overcoming Moore's Law bottlenecks. Current key technologies in 3D packaging include TSV (Through-Silicon Vias), microbumps, TCB (Thermo-Compression Bonding), hybrid bonding, TGV (Through Glass Via) on glass substrates, copper via filling, and its RDL (Reverse Drilling Limit). Compared to TSV technology using silicon as a substrate, TGV technology based on glass vias offers advantages such as higher interconnect density and lower loss transmission. It can package more chiplets in a smaller footprint, possessing lower dielectric constant, shorter interconnect length, higher transmission rate, and higher bandwidth density, while effectively reducing energy consumption.

[0041] However, the existing TGV manufacturing technology has the following technical bottlenecks: (1) Due to the significant difference in thermal expansion coefficients between metal and glass, the interface is prone to delamination under high temperature conditions, which leads to electrical connection failure; (2) Electroplating hole filling technology is difficult to achieve defect-free filling of high aspect ratio through holes, and the problem of voids in the holes is prominent, which seriously affects the high frequency signal transmission performance; (3) Glass substrate 01 bonding depends on the intermediate redistribution layer, which introduces additional thermal resistance and signal loss, restricting the packaging integration density and heat dissipation performance.

[0042] To address this, this application proposes a glass substrate structure comprising at least two glass substrates 01, each substrate having a first surface and a second surface, with conductive functional units integrated on the surfaces and interiors, such as conductive lines 02 and conductive vias 03. The conductive lines 02 are distributed on the substrate surface (single-sided or double-sided), serving as lateral signal transmission channels to support high-density wiring requirements. The line routing is customized according to signal transmission needs, such as differential pair wiring and shielding layer design, to reduce crosstalk and electromagnetic interference. The conductive lines 02 are formed by molding to create line grooves, which are then filled with conductive paste, saving coating, photolithography, and electroplating processes compared to line transfer (CTT) technology.

[0043] The conductive via 03 penetrates the substrate vertically, with its ends connected to the surface conductive lines 02 or external exposed areas, achieving vertical interconnection between layers. The conductive via 03 is a vertical channel penetrating the glass substrate 01. The via shape can be designed as cylindrical, conical, or stepped. Both ends of the via directly connect to the surface conductive lines 02, or extend to the edge of the substrate to form external exposed pads, facilitating interlayer stacking or external device connection. The conductive via 03 is formed by laser-induced etching, and simultaneously filled with conductive paste, solving the problems of forming accuracy and reliability of high aspect ratio glass vias.

[0044] Two adjacent glass substrates 01 are electrically connected at the bonding interface through conductive lines 02 and / or conductive vias 03. The conductive lines 02 and conductive vias 03 work together to achieve a three-dimensional interconnect architecture. High-precision alignment marks ensure accurate alignment of the conductive lines 02 and vias on the upper and lower substrates, improving accuracy. Lateral + vertical synergy: signals are transmitted laterally through surface lines and vertically across layers vias, shortening the total path length compared to traditional planar wiring. Adjusting the via diameter and paste conductivity allows for precise control of the transmission line characteristic impedance, reducing signal reflection. Simultaneously, the conductive paste has a significantly higher thermal conductivity than traditional organic media, allowing heat to be rapidly conducted vertically through the vias, reducing local hotspot temperatures. The via array serves as a heat diffusion path, balancing interlayer temperature gradients and preventing thermal stress concentration.

[0045] This application addresses the problem that the significant difference in thermal expansion coefficients between the glass substrate 01 and the metal conductor (such as copper) leads to delamination or cracking at the interface due to accumulated thermal stress during high-temperature processes or operating environments. This directly compromises the stability of electrical connections and affects the long-term reliability of the device. Existing technologies require intermediate redistribution layers (such as silicon interlayers or organic dielectrics) to achieve electrical connections between multiple layers of glass substrate 01, resulting in a more complex packaging structure. These intermediate layers not only increase thermal resistance and limit heat dissipation efficiency but also introduce parasitic capacitance and impedance discontinuities, hindering the improvement of high-frequency signal transmission performance and packaging density.

[0046] This design abandons the traditional intermediate redistribution layer and instead employs a direct stacking of multiple glass substrates 01. Interlayer electrical connections are achieved through conductive lines 02 on the substrate surface and through-hole conductive vias 03. This simplifies the process, eliminates parasitic impedance and signal reflection caused by the interposer, reduces interlayer thermal resistance, and improves heat dissipation efficiency and signal transmission rate. The vertical interconnection of conductive lines 02 and vias on the glass substrate 01 surface creates a compact three-dimensional packaging structure. This architecture reduces lateral wiring length, lowers signal delay, and supports higher-density device integration, providing a highly reliable carrier for advanced packaging (such as chiplets and RF modules). A conductive paste (such as a silver or copper paste composite material) with a thermal expansion coefficient highly matched to the glass substrate 01 is used to fill the vias and lines, replacing the traditional copper plating process. After curing, the paste forms a strong interfacial bond with the glass substrate 01, effectively mitigating stress concentration during thermal cycling, preventing delamination failure, and enhancing the high-temperature reliability of the packaging structure.

[0047] Meanwhile, based on the rheological properties of the slurry and the optimization of the cavity structure, dense filling of high aspect ratio through-holes is achieved through vacuum-assisted filling or pressure injection processes. This eliminates voids and cracks within the holes, and the conductivity of the slurry further reduces interfacial contact resistance, ensuring low-loss transmission of high-frequency signals. This technology overcomes the problem that traditional electroplating techniques struggle to uniformly fill high aspect ratio glass through-holes, which often leave voids or cracks inside, leading to uneven conductivity, degraded signal integrity, and severe losses, especially in high-frequency transmission scenarios.

[0048] This application includes at least two glass substrates 01, each of which is provided with conductive lines 02 and conductive vias 03. Adjacent glass substrates 01 are electrically connected through conductive lines 02 and / or conductive vias 03. This eliminates the complex process of traditional pre-fabricated intermediate redistribution layers. By directly stacking the glass substrates 01 without intermediate layers and interconnecting them with conductive vias 03 / lines, a three-dimensional encapsulation structure is achieved, thereby eliminating parasitic impedance caused by interlayers, reducing interlayer thermal resistance, and optimizing signal transmission efficiency. Simultaneously, this application uses conductive paste filling, whose coefficient of thermal expansion is highly compatible with the glass substrates 01, reducing interfacial thermal stress, avoiding delamination failure under high-temperature cycling, and improving the reliability of the encapsulation structure. Furthermore, the conductive lines 02 and conductive vias 03 are formed using a trench + paste filling method, achieving defect-free molding of high aspect ratio vias and reducing high-frequency signal transmission loss.

[0049] This application includes at least two glass substrates 01, each of which is provided with conductive lines 02 and conductive vias 03. Adjacent glass substrates 01 are electrically connected through conductive lines 02 and / or conductive vias 03. This eliminates the complex process of traditional pre-fabricated intermediate redistribution layers. By directly stacking the glass substrates 01 without intermediate layers and interconnecting them with conductive vias 03 / lines, a three-dimensional encapsulation structure is achieved, thereby eliminating parasitic impedance caused by interlayers, reducing interlayer thermal resistance, and optimizing signal transmission efficiency. Simultaneously, this application uses conductive paste filling, whose coefficient of thermal expansion is highly compatible with the glass substrates 01, reducing interfacial thermal stress, avoiding delamination failure under high-temperature cycling, and improving the reliability of the encapsulation structure. Furthermore, the conductive lines 02 and conductive vias 03 are formed using a trench + paste filling method, achieving defect-free molding of high aspect ratio vias and reducing high-frequency signal transmission loss.

[0050] In one embodiment, each of the conductive lines 02 includes:

[0051] Circuit grooves are formed on the first and / or second surfaces of the glass substrate 01. The circuit grooves are formed on the surfaces of the glass substrate 01 (first and / or second surfaces) through a thermoforming process, and their shape and depth are precisely controlled according to circuit design requirements. The manufacturing process is as follows:

[0052] First, a mold with a specific circuit pattern is prepared using a high-temperature resistant material. The mold surface is precision-machined to ensure the geometric accuracy of the groove structure. The glass substrate 01 and the mold are simultaneously heated in an oxygen-free environment. When the temperature reaches the glass's softening point, the glass enters a plastic state. At this point, uniform pressure is applied to make the glass adhere to the mold surface, and the mold's raised structure is pressed into the glass surface to form a groove of predetermined depth. During this process, precise control of temperature and pressure ensures full utilization of the glass's fluidity, avoiding excessive deformation while ensuring the clarity of the groove edges. After the holding pressure stage, the substrate is slowly cooled below the glass transition point to stabilize and solidify the substrate structure. Demolding then yields a smooth circuit groove with a depth and width perfectly matching the mold design, providing precise space for subsequent filling with conductive paste.

[0053] A first conductive metal is filled into the circuit groove and is flush with the surface of the glass substrate 01 forming the circuit groove. After the groove is formed, a conductive paste (such as silver paste, copper paste, or their alloy paste) is used to fill it until it is flush with the surface of the glass substrate 01, forming a smooth conductive path. High-temperature sintering or low-temperature curing technology ensures that the conductive paste fills the circuit groove without gaps and that the interface is tightly bonded, thus preserving the surface flatness of the glass substrate 01 while achieving the construction of a high-precision signal transmission channel. The flush design of the first conductive metal with the glass surface avoids the mechanical stress concentration problem of traditional raised circuits and provides an ideal contact interface for subsequent interlayer stacking and bonding.

[0054] In one embodiment, each of the conductive vias 03 includes:

[0055] Vias are formed through the glass substrate 01, with their ends connected to the conductive lines 02 or exposed on the first surface and / or the second surface. The vias penetrate the glass substrate 01 using a combination of laser-induced etching and chemical etching processes, with their ends connected to the surface conductive lines 02 or exposed areas of the substrate, forming vertical interconnect channels. The fabrication process is as follows:

[0056] In the target bonding area (PAD), a short-pulse laser locally irradiates the glass surface, breaking down the amorphous structure of the glass through photon energy and forming a micron-sized region of enhanced chemical activity. This process generates a network of microcracks within the glass and alters the local chemical composition, significantly improving the selective penetration of subsequent etchants. The substrate is then immersed in a hydrofluoric acid solution. The modified areas dissolve rapidly due to the enhanced chemical activity, while the unmodified areas maintain an extremely low etching rate, resulting in vias with steep sidewalls and excellent aspect ratios. The precise laser positioning combined with the anisotropic properties of the etchant ensures controllable via morphology, smooth walls, and the absence of deep cracks, laying the structural foundation for high-density interconnects.

[0057] After etching, etching debris or microscopic irregularities may remain on the inner walls of the vias and the glass surface. At this point, chemical mechanical polishing (CMP) is used for global polishing: the chemical components in the polishing slurry react gently with the glass surface, softening the surface material; simultaneously, the mechanical polishing action, transmitted through the rotation and pressure of the polishing pad, uniformly removes the softened layer and residue. This synergistic process not only eliminates microscopic defects on the via walls but also achieves atomic-level flatness on the glass surface, preventing poor contact due to interface roughness during subsequent conductive paste filling. The polished inner walls of the vias are mirror-smooth, forming a seamless transition with the glass substrate surface, ensuring precise alignment and reliable bonding during interlayer stacking.

[0058] A second conductive metal is filled within the via and flush with the surface of the glass substrate 01 through which it penetrates. The via is filled with a conductive paste identical to the conductive line 02. The filling process utilizes the paste's flow characteristics to achieve a dense, gapless structure between the paste and the via after curing, ultimately forming a conductive channel completely flush with the upper and lower surfaces of the glass. This flush structure eliminates gaps during interlayer stacking, avoiding stress concentration caused by height differences, while ensuring precise alignment of vertical interconnects and lateral conductive paths, providing a reliable foundation for high-density 3D packaging. After filling, the surface of the second conductive metal is flush with the upper and lower surfaces of the glass substrate 01, ensuring seamless alignment during interlayer stacking. By precisely controlling the etching rate and filling flow, defect-free forming of high aspect ratio vias is achieved. The tight adhesion between the second conductive metal (formed by curing the conductive paste) and the glass via wall effectively reduces contact resistance. Simultaneously, the flush structure eliminates interlayer gaps associated with traditional raised electrodes, improving packaging density and thermomechanical reliability.

[0059] In one embodiment, the first conductive metal and the second conductive metal are respectively filled and cured with conductive paste to form corresponding line grooves and vias. The specific process is as follows:

[0060] The glass substrate 01 with the prepared circuit grooves and vias is placed in a vacuum chamber. Air is removed from the grooves by creating a negative pressure environment to prevent air bubbles from remaining during paste filling. Conductive paste (such as silver paste or copper paste) is injected into the grooves and vias under vacuum conditions, utilizing the paste's fluidity to achieve dense filling of high aspect ratio structures. The ratio of metal particle size to organic carrier in the paste is optimized to ensure that it fully penetrates to the bottom and sidewalls of the micron-sized grooves under vacuum, forming a void-free pre-formed structure.

[0061] After filling, the substrate is gradually heated to 200-300°C in an inert atmosphere, causing the organic solvents in the slurry to evaporate and the resin to crosslink and cure. Subsequently, it is sintered briefly at a higher temperature (e.g., 400°C) to promote the formation of neck connections between metal particles, creating a continuous conductive path. During sintering, the matching thermal expansion coefficients of the slurry and the glass substrate significantly reduce interfacial stress, improve the metal-glass interface bonding strength, and avoid the risk of delamination under high-temperature operating conditions. Simultaneously, low-temperature curing technology can be used, with gradient heating (e.g., 10°C / min) to prevent rapid solvent evaporation that could cause slurry cracking, and nitrogen / argon protection to prevent metal oxidation (especially copper paste). Epoxy or acrylic resins complete crosslinking at 120-180°C, forming a three-dimensional network structure that fixes the position of conductive particles. Afterwards, slow heating and holding release interfacial thermal stress, promoting the rearrangement and densification of conductive particles.

[0062] The cured substrate surface may have slurry overflow or slight unevenness. Chemical mechanical polishing (CMP) is used, employing an alkaline polishing slurry with a soft polishing pad to selectively remove excess metal layers while simultaneously planarizing the glass surface globally. The CMP process achieves nanoscale roughness on the glass surface, ensuring the conductive lines 02 and the metal layers at the via ends are completely flush with the glass surface, providing an atomically smooth contact interface for subsequent chip bonding or multilayer substrate stacking. Vacuum filling ensures the second conductive metal within the via is dense and defect-free, while CMP eliminates surface unevenness; the combination of these two processes guarantees the stability of electrical connections and signal integrity.

[0063] In one embodiment, such as Figure 3 As shown, the conductive line 02 and the conductive via 03 are electrically connected at the bonding interface of adjacent glass substrates 01 to form a three-dimensional interconnect network. The glass-to-glass bonding process is as follows: First, contaminants (such as organic matter and metal residues) on the surface of the glass substrate 01 are removed by high-energy ion bombardment. The glass substrate is placed in a vacuum chamber, and a mixture of argon and oxygen is introduced. A high-voltage electric field is applied to generate plasma. High-energy ions bombard the glass surface at high speed, stripping away contaminants through a sputtering effect. Simultaneously, the oxygen plasma oxidizes residual organic matter, converting it into volatile gases such as CO2 and H2O, which are then discharged. At the same time, the surface is micro-roughened to increase bonding active sites. The treated glass is then immersed in an aqueous solution of hydrogen peroxide or ozone. The hydroxyl radicals generated in the solution react with the silicon-oxygen bonds on the glass surface, generating a large number of silanol groups, forming a dense hydrophilic layer, thus making the glass surface highly activated.

[0064] After treatment, the glass substrates 01 are bonded in a cleanroom environment (Class 100 or below), initially adhering through hydrogen bonding of surface hydroxyl groups. The activated surfaces of the two treated glass substrates 01 are aligned and slowly bonded (avoiding air bubbles). The surface hydroxyl groups form initial adhesion through hydrogen bonding; at this stage, the bond strength is low but sufficient to fix the substrate position. The bonded glass substrates are then placed in an annealing furnace and heated to the target temperature at a slow heating rate. At high temperature, the Si-OH groups on adjacent glass surfaces undergo dehydration condensation, generating silicon-oxygen covalent bonds (Si-O-Si), significantly increasing the bonding interface strength, ultimately reaching near-glass bulk mechanical strength. During the bonding of adjacent glass substrates 01, the pre-designed conductive lines 02 and conductive vias 03 are precisely aligned at the bonding interface. Through the thermal expansion effect or localized pressure during annealing, microscopic diffusion occurs at the metal contact surface, forming an ohmic contact and ensuring conductive continuity.

[0065] In a three-dimensional interconnect network, conductive vias 03 directly connect adjacent layer lines, shortening signal paths and reducing transmission delays. The multi-layer stacked structure can achieve high-density wiring within a limited area, making it suitable for miniaturized devices. The high insulation and thermal stability of the glass dielectric reduce the risk of crosstalk and thermal failure.

[0066] In one embodiment, the via is a vertical through-hole, and the depth-to-diameter ratio of the via is greater than 6:1. Depth-to-width ratio = via depth / via diameter. For example, if we want to fabricate a through-hole with a diameter of 20µm and a depth of 100µm, then the depth-to-width ratio is 100 / 20 = 5:1. A high depth-to-width ratio generally refers to a large ratio, typically above 5:1. High depth-to-width structures are more difficult to fabricate: 1. In filling processes such as electroplating, chemical vapor deposition (CVD), or physical vapor deposition (PVD), high depth-to-width structures are more prone to voids. 2. In dry etching processes, the transport efficiency of gas and byproducts is reduced in deep-hole structures, leading to uneven etching rates and insufficient bottom etching. 3. The processes of photoresist coating, exposure, and development are more challenging.

[0067] In this embodiment, the via depth-to-diameter ratio is greater than 6:1, constituting a high aspect ratio via. High aspect ratio vias can realize more vertical interconnect channels within a limited substrate area, increasing packaging density, shortening signal transmission paths, reducing parasitic effects, and are suitable for millimeter-wave communication and as efficient heat dissipation paths, reducing chip junction temperature. The via described in this application adopts a vertical through-hole design, with a depth-to-diameter ratio higher than that of conventional via structures, forming a high aspect ratio three-dimensional interconnect channel. Precise shaping is achieved through a laser-induced and chemical etching synergistic process, resulting in steep hole walls and smooth inner surfaces, ensuring that the conductive paste can fully wet the channel during filling, forming a dense and defect-free conductive path. The high aspect ratio design significantly increases vertical interconnect density within a limited substrate area, making it particularly suitable for high-performance packaging scenarios requiring multi-layer stacking, while also providing a low-loss transmission path for high-frequency signals.

[0068] In one embodiment, the thickness of the glass substrate 01 is 1.0 mm, and the diameter of the via is 0.1 mm. The above embodiment illustrates the concept and advantages of a high aspect ratio. In this embodiment, the via depth is equal to the substrate thickness (1.0 mm), the aperture is 0.1 mm, and the aspect ratio reaches 10:1. A 10:1 aspect ratio via supports >500 vertical interconnect channels per square centimeter, doubling the density compared to traditional vias (5:1 aspect ratio). The insertion loss of the 10:1 aspect ratio via in the 60 GHz band is ≤0.15 dB (40% lower than traditional copper pillars). High aspect ratio vias connect antenna arrays and RF chips, reducing feeder loss; micro-line integration of filtering and matching networks; multi-layer glass substrate 01 stacking; vertical interconnection of CPU, memory, and optical engine chips vias; reduced interconnect latency. The via array carries high current, and the micro-line layout drives the circuitry, improving heat dissipation efficiency.

[0069] In one embodiment, the width of the line groove is 0.075 mm and the depth is 0.1 mm. In the field of chip packaging, the size of this line groove can adapt to the requirements of high-density interconnect (HDI). The 0.075 mm line width (approximately 3 mil) can achieve a wiring density of 13 lines per millimeter, meeting the challenges of the surge in pin count in high-frequency and high-bandwidth scenarios such as 5G communication and AI chips, while avoiding impedance abrupt changes and signal integrity degradation caused by excessively thin line widths (e.g., <0.05 mm). The 0.1 mm depth design optimizes structural stability and functionality: on the one hand, the groove with a depth-to-width ratio of 1.33:1 can be stably formed by laser etching or semi-additive process (SAP), avoiding problems such as plating voids or insufficient filler caused by excessively high depth-to-width ratios (e.g., >2:1). From a process economy perspective, a 0.075mm linewidth strikes a balance between the cost-effectiveness of precision laser direct writing (LDI) and projection lithography. Compared to finer linewidths, it can reduce mask correction costs by 20% to 30%, while maintaining compatibility with existing placement equipment (such as ±15μm placement accuracy), which meets the core demand of cost reduction and efficiency improvement in consumer electronics packaging.

[0070] According to the above embodiments and in conjunction with the appendix Figure 3 With appendix Figure 4 The process steps of this application are described as follows:

[0071] S100: The glass substrate is manufactured using a precision-machined mold. In a protective environment without oxidation, the glass and mold are heated together to the glass softening point temperature range (600℃~900℃). Once the glass and mold reach temperature equilibrium, pressure is applied to the glass and maintained constant. Subsequently, the temperature is slowly reduced to below the glass transformation point, and finally, the mold is removed, forming a pre-defined circuit groove structure on the surface of the glass substrate 01. This process achieves precise replication of the groove through thermoforming, and the geometric accuracy of the mold directly determines the dimensional consistency of the groove.

[0072] S200: At the designed pad locations, pulsed laser-induced etching (PLA) is used to form glass vias (TGVs). The specific steps are as follows: First, a pulsed laser scans the glass surface to create a continuous modified region; then, the glass is immersed in a hydrofluoric acid solution. Utilizing the difference in etching rates between the modified and unmodified glass, TGV vias with a depth-to-diameter ratio of 10:1 are selectively etched. After etching, chemical mechanical polishing (CMP) is used to remove etching residues inside and outside the vias, and the glass surface is polished to ensure a smooth inner wall and flat surface of the via.

[0073] S300: A vacuum plugging process is used to fill conductive paste into TGV vias and circuit grooves, ensuring complete filling of the holes and trenches. After filling, the glass substrate 01 is baked, causing the conductive paste to sinter at high temperature or cure at low temperature, forming continuous metallized circuitry. This step achieves electrical interconnection between the vias and grooves, providing conductive paths for subsequent circuit layers. Chemical mechanical polishing (CMP) is then used to polish the surface of the glass substrate 01, removing excess metal that overflowed due to paste filling, restoring the glass surface to flatness while preserving the complete metallized structure within the grooves and vias. This step ensures interface cleanliness and flatness for subsequent bonding processes.

[0074] S400: The metallized TGV glass substrate 01 is laminated and bonded according to the designed circuit pattern. First, the glass surface is activated using argon-oxygen mixed plasma to enhance its surface energy; then, the bonding interface is further modified by hydroxyl radical solution treatment to promote chemical bonding between glass layers. Finally, permanent bonding of the multilayer glass substrate 01 is achieved under the synergistic effect of pressure and temperature, forming a highly integrated three-dimensional TGV glass circuit structure.

[0075] Furthermore, this application also proposes a chip packaging structure, including a chip and a glass substrate 01 structure as described above. The glass substrate 01 structure includes: at least two glass substrates 01, each having a first surface and a second surface opposite to each other; each glass substrate 01 is provided with: a conductive line 02 disposed on the first surface and / or the second surface of the glass substrate 01; a conductive via 03 penetrating the glass substrate 01, with its end connected to the conductive line 02 or exposed on the first surface and / or the second surface; adjacent two glass substrates 01 are electrically connected at a bonding interface through the conductive line 02 and / or the conductive via 03, wherein the conductive line 02 and the conductive via 03 are filled with conductive paste.

[0076] This application includes at least two glass substrates 01, each of which is provided with conductive lines 02 and conductive vias 03. Adjacent glass substrates 01 are electrically connected through conductive lines 02 and / or conductive vias 03. This eliminates the complex process of traditional pre-fabricated intermediate redistribution layers. By directly stacking the glass substrates 01 without intermediate layers and interconnecting them with conductive vias 03 / lines, a three-dimensional encapsulation structure is achieved, thereby eliminating parasitic impedance caused by interlayers, reducing interlayer thermal resistance, and optimizing signal transmission efficiency. Simultaneously, this application uses conductive paste filling, whose coefficient of thermal expansion is highly compatible with the glass substrates 01, reducing interfacial thermal stress, avoiding delamination failure under high-temperature cycling, and improving the reliability of the encapsulation structure. Furthermore, the conductive lines 02 and conductive vias 03 are formed using a trench + paste filling method, achieving defect-free molding of high aspect ratio vias and reducing high-frequency signal transmission loss.

[0077] In one embodiment of a chip packaging structure, the chip is disposed on the side of the glass substrate 01 facing away from the other glass substrates 01, and the chip is electrically connected to the wiring recesses or conductive vias 03. The chip pads are directly connected to the surface conductive lines 02 via gold wire bonding or flip-chip bonding, utilizing the lateral conductive paths of the lines to transmit signals. If the chip needs to communicate with the underlying substrate, its signal passes vertically through the conductive vias 03 on the back substrate to the stacking interface, and then is transmitted to the target layer via the interlayer interconnect network. The direct interconnection between the chip and the glass substrate 01 reduces parasitic inductance and capacitance, making it particularly suitable for high-frequency or high-speed signal transmission. This embodiment achieves efficient integration of the chip and the packaging structure through the synergy of chip layout and the three-dimensional interconnect architecture of the glass substrate 01.

[0078] The above embodiments are merely preferred embodiments of this utility model and do not limit the patent scope of this utility model. Any equivalent structural or procedural transformations made based on the content of this utility model specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this utility model.

Claims

1. A glass substrate structure, characterized in that, include: At least two glass substrates having opposing first and second surfaces; each glass substrate is provided with: Conductive lines are disposed on the first surface and / or the second surface of the glass substrate; A conductive via is provided through the glass substrate, and its end is connected to the conductive line or exposed on the first surface and / or the second surface; Two adjacent glass substrates are electrically connected at the bonding interface through conductive lines and / or conductive vias, wherein the conductive lines and conductive vias are filled with conductive paste.

2. The glass substrate structure as described in claim 1, characterized in that, Each of the aforementioned conductive lines includes: Line grooves are formed on the first and / or second surfaces of the glass substrate; A first conductive metal is filled in the line groove and is flush with the surface of the glass substrate forming the line groove.

3. The glass substrate structure as described in claim 1, characterized in that, Each of the aforementioned conductive vias includes: A via is provided, penetrating the glass substrate, and its end is connected to the conductive line or exposed to the first surface and / or the second surface; A second conductive metal is filled in the via and flush with the surface of the glass substrate through which it penetrates.

4. The glass substrate structure as described in claim 2, characterized in that, The first conductive metal and the second conductive metal are respectively filled with conductive paste and solidified in the corresponding line grooves and vias.

5. The glass substrate structure as described in claim 4, characterized in that, The conductive lines and conductive vias are electrically connected at the bonding interface of adjacent glass substrates to form a three-dimensional interconnect network.

6. The glass substrate structure as described in claim 3, characterized in that, The via is a vertical through hole, and the ratio of the hole depth to the hole diameter is greater than 6:

1.

7. The glass substrate structure as described in claim 3, characterized in that, The glass substrate has a thickness of 1.0 mm, and the via diameter is 0.1 mm.

8. The glass substrate structure as described in claim 2, characterized in that, The width of the groove is 0.075 mm and the depth is 0.1 mm.

9. A chip packaging structure, characterized in that, Includes a chip and a glass substrate structure as described in any one of claims 1-8.

10. The chip packaging structure as described in claim 9, characterized in that, The chip is disposed on the side of the glass substrate facing away from the rest of the glass substrate, and the chip is electrically connected to the line groove or conductive via.

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