Spark suppression circuit based on RC delay network

Abstract

The utility model discloses a spark suppression circuit based on an RC (Resistance-Capacitance) delay network, which comprises a power supply input end positive electrode B +, a power supply input end negative electrode B-, an RC delay network circuit, a power switch circuit, a transistor control circuit and a second capacitor C2, the power input end positive electrode B + is connected with the power input end negative electrode B-through the RC delay network circuit, the power switch circuit comprises a power tube U1 and a power resistor R7, one end of the power resistor R7 is connected with the power input end negative electrode B-, the other end of the power resistor R7 is connected with the D level of the power tube U1, and the G level of the power tube U1 is connected with the power input end positive electrode B + through the transistor control circuit. The D pole of the power tube U1 is connected with a system ground wire PGND, and the S pole of the power tube U1 is connected with the negative pole B-of the power supply input end; the spark phenomenon at the moment of circuit connection can be effectively suppressed, the scheme is simple and reliable, the circuit is more stable and simpler, and the cost is remarkably reduced.

Description

Technical Field

[0001] This utility model relates to the field of high voltage DC circuit technology, and in particular to a spark suppression circuit based on an RC delay network. Background Technology

[0002] In applications involving high-current switching, such as control circuits for electromagnetic devices like relays and contactors, large-capacity electrolytic capacitors are typically used for filtering. When DC power is supplied to the motherboard, these large electrolytic capacitors are charged to a voltage equal to the DC power supply voltage. However, since the capacitor voltage cannot change abruptly, adding DC power is equivalent to a short circuit, resulting in a large current. This can easily cause sparking on the motherboard (for example, in some inductive load circuits, sudden changes in current may generate electric sparks at the contacts). In severe cases, this can damage other electronic components in the circuit or even cause the power supply section of the entire circuit to malfunction. Utility Model Content

[0003] In view of this, the present invention addresses the deficiencies of the existing technology and its main purpose is to provide a spark suppression circuit based on an RC delay network, which can effectively suppress the spark phenomenon at the moment of circuit connection. This solution is simple and reliable, making the circuit more stable, simple, and significantly reducing costs.

[0004] To achieve the above objectives, the present invention adopts the following technical solution:

[0005] A spark suppression circuit based on an RC delay network includes a positive power input terminal B+, a negative power input terminal B-, an RC delay network circuit, a power switch circuit, a transistor control circuit, and a second capacitor C2. The positive power input terminal B+ is connected to the ground line GND of the DC power supply through the second capacitor C2. The positive power input terminal B+ is connected to the negative power input terminal B- through the RC delay network circuit. The power switch circuit includes a power transistor U1 and a power resistor R7. One end of the power resistor R7 is connected to the negative power input terminal B-, and the other end is connected to the drain (D) terminal of the power transistor U1. The gate (G) terminal of the power transistor U1 is connected to the positive power input terminal B+ through the transistor control circuit. The drain terminal of the power transistor U1 is connected to the system ground line PGND, and the source (S) terminal of the power transistor U1 is connected to the negative power input terminal B-.

[0006] As a preferred embodiment, the RC delay network circuit includes a first resistor R1 and a first capacitor C1. One end of the first resistor R1 is connected to the positive terminal B+ of the power input terminal, and the other end is connected to the positive terminal of the first capacitor C1. The negative terminal of the first capacitor C1 is connected to the negative terminal B- of the power input terminal.

[0007] As a preferred embodiment, the transistor control circuit includes a transistor Q9 and a switching transistor Q10. The base of the transistor Q9 is connected between the first resistor R1 and the first capacitor C1 through a fourth resistor R4. The emitter of the transistor Q9 is connected to the negative terminal B- of the power input. The collector of the transistor Q9 is connected to the base of the switching transistor Q10 through an eighth resistor R8. The end of the eighth resistor R8 away from the collector of the transistor Q9 is connected to the source of the switching transistor Q10 through a third resistor R3. The source of the switching transistor Q10 is connected to the positive terminal B+ of the power input. The drain of the switching transistor Q10 is connected to the gate (G) terminal of the power transistor U1.

[0008] As a preferred embodiment, the gate (G) of the power transistor U1 is connected in series with the source (S) of the power transistor U1 through a fifth resistor R5.

[0009] As a preferred embodiment, the drain of the switching transistor Q10 is connected to the gate (G) of the power transistor U1 via a sixth resistor R6.

[0010] As a preferred embodiment, a current-limiting resistor R2 is connected in series between the positive terminal B+ of the power input and the negative terminal B- of the power input.

[0011] Compared with the prior art, this utility model has obvious advantages and beneficial effects. Specifically, as can be seen from the above technical solution, firstly, the ground of the DC power supply and the ground of the motherboard system are isolated through the power transistor U1, and a power resistor R7 is connected between the two grounds. When the DC power supply supplies power to the motherboard, the large capacitor C2 is charged through the power resistor R7. When the capacitor is fully charged, the power transistor U1 is turned on using the RC delay network, so that the two grounds are fully connected. The entire circuit will enter a relatively stable working state. When the power transistor U1 is fully turned on, the ground line GND of the DC power supply and the system ground line PGND are directly connected, which is equivalent to forming a low impedance path between the two grounds. At this time, the DC power supply can stably supply power to the motherboard system. The current can flow smoothly from the positive terminal of the power supply through the various loads on the motherboard, and then flow back to the negative terminal of the power supply through the power transistor U1, thereby ensuring that the various electronic components on the motherboard system can work normally. During the turn-on or turn-off process of power transistor U1, the RC delay network circuit plays a crucial role in spark suppression. When power transistor U1 is turned on, the RC network circuit can limit the rate of current rise and prevent the current from becoming too large and generating sparks. When U1 is turned off, the first capacitor C1 and the second capacitor C2 can store energy to prevent the voltage from dropping suddenly and generating sparks.

[0012] Secondly, the control circuit composed of transistor Q9 and switching transistor Q10 can further stabilize the switching state of power transistor U1, reducing the sparking phenomenon caused by voltage and current changes during the switching process; and, it avoids repeatedly switching power transistor U1, preventing power transistor U1 from overheating.

[0013] Furthermore, due to the presence of the RC delay network, even if slight voltage fluctuations or interference occur during power supply, the RC network can buffer and filter these changes. When the power supply voltage suddenly rises, capacitors C1 and C2 can absorb some energy, preventing damage to the motherboard system from the instantaneous voltage increase; when the power supply voltage drops, the capacitors can release the stored energy, maintaining the power supply stability of the motherboard system and minimizing circuit radiation.

[0014] To more clearly illustrate the structural features and effects of this utility model, the following detailed description of this utility model is provided in conjunction with the accompanying drawings and specific embodiments. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the circuit structure of an embodiment of the present invention. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the scope of the present utility model.

[0017] It should be noted that when a component is said to be "fixed to" another component, it can be directly attached to the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0018] Please see Figure 1This utility model embodiment provides a spark suppression circuit based on an RC delay network, including a positive power input terminal B+, a negative power input terminal B-, an RC delay network circuit, a power switch circuit, a transistor control circuit, and a second capacitor C2. The second capacitor C2 is a large-capacity electrolytic capacitor. The positive power input terminal B+ is connected to the ground line GND of the DC power supply through the second capacitor C2. The positive power input terminal B+ is connected to the negative power input terminal B- through the RC delay network circuit. The power switch circuit includes a power transistor U1 and a power resistor R7. One end of the power resistor R7 is connected to the negative power input terminal B-, and the other end is connected to the drain (D) of the power transistor U1. The gate (G) of the power transistor U1 is connected to the positive power input terminal B+ through the transistor control circuit. The drain of the power transistor U1 is connected to the system ground line PGND, and the source (S) of the power transistor U1 is connected to the negative power input terminal B-. The power resistor R7 is the current-limiting resistor for the gate of the power transistor U1. It is used to limit the current flowing into the gate of the power transistor U1, prevent the current flowing into the gate of the power transistor U1 from being too large, protect the power transistor U1, and control its switching speed.

[0019] Furthermore, the RC delay network circuit includes a first resistor R1 and a first capacitor C1. One end of the first resistor R1 is connected to the positive terminal B+ of the power input, and the other end is connected to the positive terminal of the first capacitor C1. The negative terminal of the first capacitor C1 is connected to the negative terminal B- of the power input. The first resistor R1 and the first capacitor C1 form an RC low-pass filter circuit. When the voltage in the circuit changes, the first capacitor C1 will charge and discharge. Since the charging and discharging process of the capacitor takes a certain amount of time, the current through the first resistor R1 and the first capacitor C1 cannot change abruptly, thereby delaying the voltage change. In this circuit, it can buffer and delay the voltage change of the input power supply VBAT_L1, avoiding instability in subsequent circuits caused by rapid voltage changes, and also helping to suppress sparks that may be caused by voltage changes.

[0020] Furthermore, the transistor control circuit includes a transistor Q9 and a switching transistor Q10. The base of transistor Q9 is connected between the first resistor R1 and the first capacitor C1 via a fourth resistor R4. The emitter of transistor Q9 is connected to the negative terminal B- of the power input. The collector of transistor Q9 is connected to the base of switching transistor Q10 via an eighth resistor R8. The end of the eighth resistor R8 away from the collector of transistor Q9 is connected to the source of switching transistor Q10 via a third resistor R3. The source of switching transistor Q10 is connected to the positive terminal B+ of the power input. The drain of switching transistor Q10 is connected to the gate (G) terminal of power transistor U1. The fourth resistor R4 acts as a current-limiting resistor for the base of transistor Q9, limiting the current flowing into the base of transistor Q9 to ensure that transistor Q9 operates within a safe current range. It also plays a role in voltage division, adjusting the conduction threshold of transistor Q9.

[0021] When the voltage output by the RC delay network circuit reaches a certain threshold, giving the base of transistor Q9 sufficient forward bias voltage, transistor Q9 turns on and opens the path between the collector and emitter, allowing current to flow, thereby controlling the state of switching transistor Q10.

[0022] When the switching transistor Q10 is turned on, it pulls the gate of the power transistor U1 low, causing U1 to turn off and thus disconnecting the load circuit. When the switching transistor Q10 is turned off, the gate of the power transistor U1 is turned on at a suitable voltage, allowing current to flow through the load circuit. This transistor-to-MOSFET control method enables smooth switching of the load current, avoiding large sparks caused by sudden current changes during current cut-off or on-off. The power transistor U1 acts as the switching device in the circuit, and its gate (G) is controlled by the switching transistor Q10. When Q10 is turned on, it pulls the gate of the power transistor U1 low, turning U1 on and allowing current to flow from the power supply through the power transistor U1 to the system ground PGND. This creates a low-impedance path between the two grounds, allowing the entire circuit to enter a relatively stable operating state. At this time, the DC power supply can stably power the motherboard system, and the current can smoothly flow from the positive terminal of the power supply through the various loads on the motherboard, and then back to the negative terminal of the power supply through the power transistor U1, ensuring the normal operation of all electronic components on the motherboard system.

[0023] Furthermore, the gate (G) of power transistor U1 is connected in series with the source (S) of power transistor U1 through the fifth resistor R5. The fifth resistor R5 is connected between the collector of switching transistor Q10 and the gate of power transistor U1, serving as a current limiter and protector to prevent excessive inrush current to the gate of power transistor U1 when switching transistor Q10 is turned on. It also participates in the control of the gate voltage of power transistor U1.

[0024] Furthermore, the drain of the switching transistor Q10 is connected to the gate (G) of the power transistor U1 via the sixth resistor R6. The sixth resistor R6 is connected between the collector of the switching transistor Q10 and the input power supply VBAT_L1, further adjusting the voltage at the collector of Q10 and affecting the control effect of the switching transistor Q10 on the gate of the power transistor U1, ensuring that the power transistor U1 can turn on and off as expected. The fifth resistor R5 and the sixth resistor R6 are used to set the operating points of the switching transistor Q10 and the transistor Q9, as well as the signal transmission characteristics. The sixth resistor R6 is connected to the collector of the transistor Q9, affecting the control effect of the transistor Q9 on the switching transistor Q10.

[0025] Furthermore, a current-limiting resistor R2 is connected in series between the positive terminal B+ and the negative terminal B- of the power input. This current-limiting resistor R2, connected in parallel with the transformer output, serves to limit current and divide voltage, preventing excessive current surges during circuit startup or abnormal conditions. The current-limiting resistor R2 and the second capacitor C2 also form an RC low-pass filter circuit, with R2 = 2MΩ and C2 = 2000uF / 35V. This RC network further filters and delays the input voltage VBAT_L1. Compared to the RC network circuit of the first resistor R1 and the first capacitor C1, its time constant is larger, enabling more effective smoothing of voltage fluctuations and providing a more stable power supply environment for subsequent circuits, reducing the risk of sparks caused by power supply voltage fluctuations.

[0026] Spark suppression principle: At the instant the circuit is switched on, due to the presence of the RC delay network circuit (first resistor R1 and first capacitor C1), the second capacitor C2 needs a certain amount of time to charge to a voltage sufficient to turn on transistor Q9 and switching transistor Q10. During this delay time, power transistor U1 will not turn on immediately, thus avoiding sparking phenomena that may occur due to sudden current changes at the moment of switching on. When the second capacitor C2 has finished charging, transistor Q9 and switching transistor Q10 turn on sequentially, thereby enabling power transistor U1 to enter the normal operating state of the circuit. By reasonably adjusting the time constant of the RC delay network (i.e., the values ​​of the first resistor R1 and the first capacitor C1), the turn-on delay time of the switching devices can be precisely controlled to achieve a good spark suppression effect.

[0027] Detailed implementation: When the motherboard is supplied with 24V, the circuit first charges the second capacitor C2 with a small current through the power resistor R7. When the voltage of the second capacitor C2 is close to the input power supply VBAT_L1 voltage, the first delay time T1 is calculated using the formula: T = CV / I. In the RC delay circuit, T2 is calculated as T2 = RC * ln((V-V0) / (V-V1)), where V = input power supply VBAT_L1 voltage, V0 is the initial voltage of the second capacitor C2 (0V), and V1 is the voltage required to turn on the power transistor U1. After completing a series of operations, and T2 > T1, there will be no sparking.

[0028] In summary, this spark suppression circuit based on an RC delay network, through the cooperation of the RC delay network circuit and the transistor, effectively controls the turn-on timing of the power switching device, thereby suppressing the sparking phenomenon at the moment of circuit switching. This solution is simple and reliable, significantly eliminates sparking, and offers greater circuit stability, simplicity, and significantly reduced cost.

[0029] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions and improvements made within the principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A spark suppression circuit based on RC delay network characterized by: The circuit includes a positive power input terminal B+, a negative power input terminal B-, an RC delay network circuit, a power switch circuit, a transistor control circuit, and a second capacitor C2. The positive power input terminal B+ is connected to the DC power supply ground GND through the second capacitor C2. The positive power input terminal B+ is connected to the negative power input terminal B- through the RC delay network circuit. The power switch circuit includes a power transistor U1 and a power resistor R7. One end of the power resistor R7 is connected to the negative power input terminal B-, and the other end is connected to the drain (D) terminal of the power transistor U1. The gate (G) terminal of the power transistor U1 is connected to the positive power input terminal B+ through the transistor control circuit. The drain terminal of the power transistor U1 is connected to the system ground PGND, and the source (S) terminal of the power transistor U1 is connected to the negative power input terminal B-.

2. The RC delay network based spark suppression circuit of claim 1, wherein: The RC delay network circuit includes a first resistor R1 and a first capacitor C1. One end of the first resistor R1 is connected to the positive terminal B+ of the power input terminal, and the other end is connected to the positive terminal of the first capacitor C1. The negative terminal of the first capacitor C1 is connected to the negative terminal B- of the power input terminal.

3. The RC delay network based spark suppression circuit of claim 2, wherein: The transistor control circuit includes a transistor Q9 and a switching transistor Q10. The base of transistor Q9 is connected between the first resistor R1 and the first capacitor C1 through a fourth resistor R4. The emitter of transistor Q9 is connected to the negative terminal B- of the power input. The collector of transistor Q9 is connected to the base of switching transistor Q10 through an eighth resistor R8. The end of the eighth resistor R8 away from the collector of transistor Q9 is connected to the source of switching transistor Q10 through a third resistor R3. The source of switching transistor Q10 is connected to the positive terminal B+ of the power input. The drain of switching transistor Q10 is connected to the gate (G) terminal of power transistor U1.

4. The RC delay network based spark suppression circuit of claim 3, wherein: The gate (G) of the power transistor U1 is connected in series with the source (S) of the power transistor U1 through the fifth resistor R5.

5. The RC delay network based spark suppression circuit of claim 3, wherein: The drain of the switching transistor Q10 is connected to the gate (G) terminal of the power transistor U1 via a sixth resistor R6.

6. The RC delay network based spark suppression circuit of claim 1, wherein: A current-limiting resistor R2 is connected in series between the positive terminal B+ of the power input terminal and the negative terminal B- of the power input terminal.

Images