semiconductor chip

Abstract

Semiconductor chip (100) with a sequence of semiconductor layers, comprising a first semiconductor layer (1) which has a lateral variation of material composition and a constant thickness along at least one direction of extension, wherein - the semiconductor chip (100) is designed as a laser diode chip and has a laser stripe in which light is generated during operation and a facet through which light is emitted during operation, - the first semiconductor layer (1) has at least one first region (11) and second regions (12) adjacent laterally to it, - the first area (11) and the second areas (12) have the same material system, - the material composition of the first area (11) differs from the material composition of the second areas (12), wherein the first area (11) and the second areas (12) have the same thickness, - the first area (11) is formed in a stripe shape in the area of ​​the laser strip, - the second areas (12) are formed in a lateral direction transverse to the extension direction of the laser stripe on both sides next to the first area (11), - the material composition in the first and second areas (11, 12) is selected such that a band spacing in the second areas (12) is smaller than a band spacing in the first area (11), and - the first semiconductor layer (1) is at least part of an active layer.

Description

[0001] This patent application claims priority from German patent application 10 2016 108 891.9, the disclosure of which is hereby incorporated by reference.

[0002] A semiconductor chip is specified. In particular, the semiconductor chip can be embodied as an optoelectronic semiconductor chip, such as a light-emitting semiconductor chip, for example, a light-emitting diode chip or laser diode chip, or a light-detecting semiconductor chip.

[0003] The document DE 10 2008 022 941 A1 describes a sensor system with an illumination device and a detection device.

[0004] The document GB 2 358 281 A describes a method for manufacturing a semiconductor laser component.

[0005] Laser diodes are increasingly being used in new areas instead of light-emitting diodes, for example, in lighting and production applications, where they can leverage their advantages of increased luminance and depth of field over LEDs. However, the use of laser diodes can be disadvantageous compared to competing LED-based technologies because laser diodes only exhibit laser emission above a certain, often comparatively very high, current value, the laser threshold, and because laser facets, due to the high luminance, are susceptible to facet damage, which can lead to spontaneous failure.

[0006] Due to the higher operating current of laser diodes, i.e. the height of the laser threshold, laser diodes lose efficiency compared to light-emitting diodes, especially in the low current range. To lower the laser threshold, one option is to increase the reflectivity of the facet coating on the output facet. However, this can simultaneously reduce the steepness of the laser diode characteristic curve and thus have a negative impact on the efficiency of the laser diode. Another option is to reduce the resonator geometry, for example the resonator length and width. This, however, correspondingly limits the achievable optical power of the laser diode. Alternatively, an increase in index guidance and reduced current spreading can be achieved by creating a tall waveguide structure known as a ridge waveguide.However, a disadvantage here can be that the etching process used to produce the waveguide structure extends close to or through the active zone, which can lead to damage and thus to problems with component stability.

[0007] To increase the facet loading limit, the resonator geometry can be enlarged, although this has a negative impact due to an increased laser threshold. Alternatively, there are efforts and approaches in various material systems to make the laser facet region as absorption-free as possible. For example, attempts can be made to mix the quantum well structure near the facet using implantation or diffusion, which can correspondingly increase the band gap. However, a disadvantage of this approach is that the dopants required for this can be incorporated into interstitial lattice sites, which can lead to additional absorption centers that can negatively impact device efficiency. Therefore, especially in the case of implanted layers, an attempt must be made to incorporate the dopants into lattice sites in a subsequent annealing step.However, the temperatures required for this can lead to damage to the quantum well structure and thus to losses in the laser threshold and characteristic slope. Furthermore, the high temperatures of the diffusion and implantation annealing steps can cause decomposition of the contact layer by releasing volatile components such as Group V components (i.e., As, P, or N) of the III-V semiconductor, which can lead to increased operating voltages of the laser diode.

[0008] Alternative technological approaches are based on the principle of depositing a crystalline or semi-crystalline layer onto the laser facet created by fracturing. This layer can lead to an increase in the band gap of the semiconductor material with as few defects and strains as possible. Suitable processes for this include coatings using MBE (molecular beam epitaxy) or IBD (ion beam deposition). The disadvantage of this approach is the high level of effort required, particularly in handling laser bars, which correspondingly increases manufacturing costs. In addition, a uniform coating with a material with an increased band gap across the entire laser facet leads to additional strain on the facet, which can have a negative impact on component stability.

[0009] Semiconductor chips are specified, for example, in the following publications: JP S63-114287 A, JP S62-145888 A, JP 2010-092952 A, JP 2003-303993 A, DE 10 2005 025 416 A1, US 2004 / 0 119 080 A1.

[0010] At least one object of certain embodiments is to provide a semiconductor chip.

[0011] This object is achieved by a subject matter according to the independent patent claim. Advantageous embodiments and further developments of the subject matter are characterized in the dependent claims and will further become apparent from the following description and the drawings.

[0012] The semiconductor chip has at least a first semiconductor layer. The first semiconductor layer can, in particular, be part of a semiconductor layer sequence comprising a plurality of semiconductor layers.

[0013] In a method for producing a semiconductor chip, at least a first semiconductor layer is grown. The first semiconductor layer can, in particular, be part of a semiconductor layer sequence.

[0014] The embodiments and examples described above and below relate equally to the method for producing the semiconductor chip and to the semiconductor chip.

[0015] The semiconductor chip can be embodied, for example, as an optoelectronic semiconductor chip, i.e., as a light-emitting or light-detecting semiconductor chip, such as a light-emitting diode chip, laser diode chip, or photodiode chip. Furthermore, the semiconductor chip can, alternatively or in addition to optoelectronic functionality, also have electronic functionality and, for example, be embodied as a transistor or other electronic power component. Even though the following description primarily refers to optoelectronic and, in particular, light-emitting semiconductor chips, the embodiments of the semiconductor chip described below also apply to other, in particular non-optoelectronic, semiconductor chips.

[0016] The semiconductor layer sequence can be designed, in particular, as an epitaxial layer sequence, i.e., as an epitaxially grown semiconductor layer sequence. The semiconductor layer sequence can be based on InAlGaN, for example. InAlGaN-based semiconductor layer sequences include, in particular, those in which the epitaxially produced semiconductor layer sequence generally comprises a layer sequence of different individual layers, which contains at least one individual layer that is a material from the III-V compound semiconductor material system In x Al y Ga 1-x-yN with 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and x + y ≤ 1. In particular, the first semiconductor layer can be based on such a material. Semiconductor layer sequences that, as part of a light-emitting semiconductor chip, have at least one active layer based on InAlGaN can, for example, preferably emit electromagnetic radiation in an ultraviolet to green wavelength range.

[0017] Alternatively or additionally, the semiconductor layer sequence can also be based on InAlGaP, i.e. the semiconductor layer sequence can have different individual layers, of which at least one individual layer, for example the first semiconductor layer, is a material from the III-V compound semiconductor material system In x Al y Ga 1-x-yP with 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and x + y ≤ 1. Semiconductor layer sequences which, as part of a light-emitting semiconductor chip, have at least one active layer based on InAlGaP can, for example, preferably emit electromagnetic radiation with one or more spectral components in a green to red wavelength range.

[0018] Alternatively or additionally, the semiconductor layer sequence may also comprise other III-V compound semiconductor material systems, for example, an InAlGaAs-based material, or II-VI compound semiconductor material systems. In particular, an active layer of a light-emitting semiconductor chip comprising an InAlGaAs-based material may be suitable for emitting electromagnetic radiation with one or more spectral components in a red to infrared wavelength range.

[0019] A II-VI compound semiconductor material can comprise at least one element from the second main group, such as Be, Mg, Ca, Sr, and one element from the sixth main group, such as O, S, Se. In particular, a II-VI compound semiconductor material comprises a binary, ternary, or quaternary compound comprising at least one element from the second main group and at least one element from the sixth main group. Such a binary, ternary, or quaternary compound can additionally comprise, for example, one or more dopants and additional constituents. Examples of II / VI compound semiconductor materials include: ZnO, ZnMgO, CdS, ZnCdS, MgBeO.

[0020] The first semiconductor layer, and in particular the semiconductor layer sequence comprising the first semiconductor layer, can be grown on a substrate, which can also be referred to here and below as a growth substrate. The substrate can comprise a semiconductor material, for example, a compound semiconductor material system mentioned above, or another material that allows epitaxial deposition. In particular, the substrate can comprise sapphire, GaAs, GaP, GaN, InP, SiC, Si, and / or Ge, or be made of such a material.

[0021] The semiconductor layer sequence of a semiconductor chip designed as an optoelectronic semiconductor chip can have, for example, a conventional pn junction, a double heterostructure, a single quantum well structure (SQW structure), or a multiple quantum well structure (MQW structure) for light generation or light detection as the active layer. In addition to the active layer, the semiconductor layer sequence can comprise further functional layers and functional regions, such as p- or n-doped charge carrier transport layers, i.e., electron or hole transport layers, undoped or p- or n-doped confinement, cladding, or waveguide layers, barrier layers, planarization layers, buffer layers, protective layers, and / or electrodes, as well as combinations thereof. In particular, the first semiconductor layer can be at least part of a waveguide layer and / or an active layer, or can be such a layer.Furthermore, the first semiconductor layer can also be part of another functional layer of the semiconductor layer sequence, or can be such a layer. For example, the first semiconductor layer can consist of a single layer. Furthermore, it can also be possible for the first semiconductor layer to have a plurality of layers or to consist of a plurality of layers.

[0022] In addition, additional layers, such as buffer layers, barrier layers and / or protective layers, can also be arranged perpendicular to the growth direction of the semiconductor layer sequence, for example around the semiconductor layer sequence, for example on the side surfaces of the semiconductor layer sequence.

[0023] The first semiconductor layer, and in particular a semiconductor layer sequence comprising the first semiconductor layer, can be grown on a growth substrate using an epitaxial process, for example, using metal-organic vapor phase epitaxy (MOVPE) or molecular beam epitaxy (MBE), and can also be provided with electrical contacts. The fabrication of the first semiconductor layer, and in particular a semiconductor layer sequence comprising the first semiconductor layer, described in detail below, can particularly preferably be carried out in a wafer assembly, which can be separated into a plurality of semiconductor chips by dicing after the growth process.

[0024] According to a further embodiment, during the growth process for growing the first semiconductor layer, an inhomogeneous lateral temperature distribution is generated along at least one extension direction of the growing first semiconductor layer. "Lateral" here and below refers to a direction that is oriented perpendicular or substantially perpendicular to a growth direction of the first semiconductor layer and in particular to the semiconductor layer sequence comprising the first semiconductor layer. The growth direction corresponds to the arrangement direction of the individual layers of the semiconductor layer sequence arranged on top of one another. In particular, the first semiconductor layer and also the remaining layers of the semiconductor layer sequence can have an extension in the lateral direction that is greater than a thickness of the corresponding layers in the growth direction.Accordingly, the first semiconductor layer and also the remaining layers of the semiconductor layer sequence can extend along extension directions in different lateral directions over the growth substrate.

[0025] Due to the inhomogeneous lateral temperature distribution along at least one extension direction of the growing first semiconductor layer, a lateral variation in a material composition of the first semiconductor layer is brought about and produced in the method described here. The lateral variation in the material composition occurs within the same material system. A variation in the material composition can mean a gradient of a proportion of one or more components of the first semiconductor layer along the at least one extension direction. Put simply, due to a temperature-dependent incorporation of the components of the material composition of the first semiconductor layer, the proportion of at least one component increases or decreases. The first semiconductor layer thus has at least two laterally adjacent regions which are based on the same material system and which have different material compositions.The transition in the material composition, i.e. the gradient of a portion of one or more constituents of the first semiconductor layer, from a first of these regions to a second of these regions can be abrupt, i.e., step-like as far as technically possible, or continuous. The layer thickness of the first semiconductor layer is constant. In other words, the at least two regions arranged laterally next to one another, which have different material compositions, have the same thickness. An "equal" or "constant" thickness can in particular mean that the thickness of the first semiconductor layer varies by no more than 10% or by no more than 5%, or particularly preferably by no more than 1%, regardless of a varying material composition.

[0026] The difference in the material composition and thus the difference in the proportion of one or more constituents of the first semiconductor layer in the at least two laterally adjacent regions can, based on a respective average proportion of the one or more constituents in the regions, be such that a first region has a proportion of one or more constituents of the material composition of, for example, less than or equal to 99% or less than or equal to 97% or less than or equal to 95% or less than or equal to 90% or less than or equal to 85% or less than or equal to 80% or less than or equal to 75% or less than or equal to 50% or less than or equal to 25% compared to a second region, or vice versa. The proportion of the constituents of the material composition can preferably be specified in relation to the chemical formula.

[0027] For example, in the case of an InAlGaN material system, the incorporation of one or more semiconductor crystal components, in particular indium, can be varied in the manner described by an inhomogeneous lateral temperature distribution. Thus, a first semiconductor layer based on the InAlGaN material system can have a first region with the composition In x Al y Ga 1-x-y N and a second area with the composition In a Al b Ga 1-a-bN, where x ≤ 0.99a or x ≤ 0.97a or x ≤ 0.95a or x ≤ 0.90a or x ≤ 0.85a or x ≤ 0.80a or x ≤ 0.75a or x ≤ 0.50a or x ≤ 0.25a. Accordingly, alternatively or additionally, the Al content and / or the Ga content can also vary in the manner described. The composition in the regions can in particular be a composition averaged over the respective region. Likewise, in other semiconductor material systems such as InAlGaP or InAlGaAs, the incorporation of one or more components, for example the In content and / or the Ga content and / or the Al content, can be varied by the inhomogeneous lateral temperature distribution.

[0028] In particular, the inhomogeneous lateral temperature distribution is present over at least one region on the growth substrate that corresponds to a subsequent semiconductor chip. In other words, this means that the first semiconductor layer is grown in a region on the growth substrate that corresponds to a semiconductor chip and has an inhomogeneous material composition along at least one extension direction, which is generated by the inhomogeneous lateral temperature distribution during the growth process.Accordingly, the inhomogeneous lateral temperature distribution can repeat periodically across the growth substrate along the at least one extension direction according to the sequence of regions on the growth substrate corresponding to multiple semiconductor chips, so that a plurality of semiconductor chips with identical or at least substantially identical lateral variations in the material composition of the first semiconductor layer can be produced in the wafer assembly. In the method described here, an inhomogeneous lateral temperature distribution is thus deliberately generated during the growth process for growing the first semiconductor layer, so that a targeted lateral variation in the material composition of the first semiconductor layer can be generated.

[0029] The inhomogeneous lateral temperature distribution can result in a first temperature range and a second temperature range that have a temperature difference of greater than or equal to 1 K, or greater than or equal to 2 K, or greater than or equal to 5 K, or even greater than or equal to 10 K. The transition from the first to the second temperature range can be abrupt, i.e., essentially step-like as far as technically possible, or continuous according to a desired temperature profile. In conventional wafer-based epitaxial processes, unwanted temperature differences can exist across the entire wafer and lead to different properties of semiconductor chips separated from the wafer. In this case, temperature differences of a few Kelvin can exist between distant regions of the wafer, the magnitude and distance of which, however, are far greater than the semiconductor chips to be manufactured.In contrast, the temperature distribution over a distance corresponding to the chip's dimensions is essentially homogeneous in conventional growth processes, so that the semiconductor layers of the semiconductor chips are grown with material compositions that are homogeneous in the lateral direction, at least over a length scale corresponding to the chip size. In contrast, the process described here deliberately creates an inhomogeneous lateral temperature distribution on a length scale that is on the order of the chip dimensions in order to create an associated inhomogeneous material composition in at least the first semiconductor layer within the semiconductor chip.In contrast to conventional epitaxy processes, the method described here thus deliberately creates a temperature difference on a length scale that corresponds to an extension of the semiconductor chips or less, so that an inhomogeneous material composition is created within a semiconductor chip in at least the first semiconductor layer.

[0030] Different local material compositions of the first semiconductor layer can lead to laterally varying band gaps, absorption coefficients, and / or refractive indices in the material of the first semiconductor layer. In the case of an active semiconductor layer intended for light generation, a laterally varying material composition can also lead to the generation of laterally varying wavelengths of the light emitted during operation of the semiconductor chip.In contrast to the process described here, known epitaxial deposition processes tend to attempt to compensate for previously described temperature variations and inhomogeneities in order to obtain a temperature distribution that is as uniform as possible over the entire surface of a growth substrate wafer, so that the material compositions of the growing layers do not vary in the lateral direction as far as possible in order to minimize the described variations in the absorption coefficient, the refractive index and / or the wavelength of the light generated during operation from semiconductor chip to semiconductor chip.

[0031] The semiconductor chip is designed as a light-emitting semiconductor chip in the form of a semiconductor laser diode. The method described here allows the growth temperature on the growth substrate to be specifically varied locally during the production of the first semiconductor layer, which may in particular be a waveguide layer and / or an active layer or a part thereof. For example, in the case of an InAlGaN material system, the incorporation of one or more semiconductor crystal constituents, in particular indium, can be varied by an inhomogeneous lateral temperature distribution in the lateral direction. This makes it possible, for example, to achieve a higher incorporation of indium into the active layer or a waveguide layer in the region of the laser stripe, i.e., the region of the semiconductor chip in which light generation is to take place, than in adjacent regions.Since a reduction of the indium content in InAlGaN leads, among other things, to a reduction of the refractive index, a refractive index gradient can be generated in the lateral direction in the first semiconductor layer, by means of which an index guidance can be achieved, which is already "built in" after the growth process into the first semiconductor layer and thus connected to the semiconductor layer sequence with the first semiconductor layer.

[0032] The semiconductor chip is designed as a laser diode chip and has a facet through which light is emitted during operation. The index guide already built into the semiconductor chip makes it possible to manufacture an index-guided laser diode without the need for a ridge waveguide, eliminating the need for a corresponding ridge etching. This simplifies chip production and makes it more cost-effective. For example, in broad-area lasers, a higher band gap created by lateral variation in the material composition of the first semiconductor layer next to a laser stripe can reduce current spreading and absorption, thereby improving laser performance.

[0033] For example, at least a second semiconductor layer is grown over the first semiconductor layer, in which a ridge waveguide is created. By combining the lateral variation of the material composition in the first semiconductor layer with a ridge waveguide structure above it in the second semiconductor layer, very strong index guidance can be achieved, which would not be possible with a ridge waveguide alone. This can make it possible, for example, to lower the lasing threshold and improve efficiency in high-power laser diodes.Furthermore, compared to conventional laser diodes with ridge waveguides, it may be possible to reduce the etch depth of the ridge waveguide structure while still achieving reduced current spreading and improved index guidance. This can, for example, prevent the risk of damage caused by the etching process, especially when etching near the active layer, leading to undesirable component aging. Furthermore, the risk of leakage currents through the active layer due to surface recombination, which can occur when etching through the active layer, can be avoided.Accordingly, the process described here allows the depth of the ridge etching and thus the height of the ridge waveguide structure to be significantly reduced compared to conventional components or to dispense with a corresponding waveguide structure altogether, since both the current limitation and the index guidance can be "built in" into the semiconductor layer sequence during the growth process.

[0034] Particularly preferably, in a semiconductor chip designed as a laser diode chip, a lateral variation of the material composition in the first semiconductor layer on both sides of a laser stripe, which can also be referred to as a laser ridge and which can be defined by a corresponding contact region or additionally a corresponding ridge wave structure, can be produced in such a way that the band gap in the material of the first semiconductor layer is increased on both sides of the laser ridge. In the InAlGaN material system, this can preferably be achieved by reducing the In content on both sides of the laser ridge, in particular in a first semiconductor layer designed as an active layer, wherein the reduction is already brought about during the epitaxial growth process in the manner described by generating an inhomogeneous lateral temperature distribution.This can minimize unwanted current spreading, while reducing absorption and simultaneously improving index guidance as described above. Alternatively, it can also be advantageous to reduce the band gap in the material of the first semiconductor layer on both sides of the laser stripe, thus increasing absorption on both sides of the laser stripe. This can be particularly preferred in the case of a broad-area laser with a plurality of laser stripes arranged side by side, so that the laser stripes are separated from one another by regions of higher absorption. This can prevent or at least reduce the propagation of ring modes or crosstalk between adjacent laser stripes.

[0035] Furthermore, in a semiconductor chip designed as a laser diode chip, a lateral variation of the material composition in the first semiconductor layer can be produced in a facet region, i.e., a region of the first semiconductor layer adjacent to a facet, such that the band gap in a second region designed as a facet region is increased compared to a first region of the first semiconductor layer, which, viewed from the facet, is farther away from the facet than the second region. In other words, the second region can be arranged adjacent to the facet and between the facet and the first region and can have a larger band gap than the first region.In the InAlGaN material system, the bandgap increase can preferably be achieved by reducing the In content in the facet region, particularly in a first semiconductor layer formed as the active layer. This reduction is already achieved during the epitaxial growth process in the manner described by generating an inhomogeneous lateral temperature distribution. This can reduce or even prevent the absorption of the active layer in the facet region, thus increasing the facet loading limit.

[0036] Furthermore, in the case of a light-emitting semiconductor chip, i.e., a laser diode chip or a light-emitting diode chip, a different material composition of the first semiconductor layer can result in different emission wavelengths, particularly if the first semiconductor layer forms at least part of an active layer of the semiconductor chip intended for light generation, so that it may be possible for the semiconductor chip with the first semiconductor layer to emit light at different wavelengths from different areas during operation. The inhomogeneous lateral temperature distribution during the growth of the first semiconductor layer can thus result in a lateral wavelength distribution of the light emission during subsequent operation of the semiconductor chip.

[0037] Furthermore, in a semiconductor chip designed as a light-emitting diode chip, a lateral variation of the material composition in the first semiconductor layer can be produced below a contact layer designed at least partially as a bond pad such that the band gap in the material of the first semiconductor layer below the bond pad is increased. In the InAlGaN material system, this can preferably be achieved by reducing the In content in the first semiconductor layer, which can preferably be designed as an active layer, below the bond pad. This can in particular be a non-current-carrying region of the first semiconductor layer. As a result, absorption in such a non-current-carrying region of the active layer can be reduced or even prevented. Furthermore, the contact layer can have current-carrying webs for current distribution in addition to a bond pad.

[0038] Below the current-carrying bridges, the material composition of the first semiconductor layer can be varied accordingly.

[0039] Furthermore, in a semiconductor chip designed as a light-emitting diode chip, the material composition in a first semiconductor layer, preferably designed as an active layer, can be varied towards a lateral edge of the semiconductor chip in such a way that the band edge of the quantum wells, and thus the band gap, of the first semiconductor layer is increased towards the edge. In particular, in this case the first semiconductor layer can have a second region which encloses a first region in the lateral direction and which borders the edge of the semiconductor chip all the way around and which has a correspondingly different material composition compared to the first region. By increasing the band gap at the edge, leakage currents at the edge of the semiconductor chip formed by the edge can be reduced, thereby increasing the performance and aging stability of the semiconductor chip.

[0040] According to a further embodiment, the inhomogeneous lateral temperature distribution is deliberately generated during the growth of the first semiconductor layer by locally thermally influencing predetermined and specifically selected regions. In particular, the inhomogeneous lateral temperature distribution can be generated at least partially by a temperature distribution structure and / or by locally varying light irradiation. The measures described here for generating the inhomogeneous lateral temperature distribution are used in particular in addition to the conventional, locally non-controllable epitaxial heating systems.

[0041] The locally varying light irradiation can, for example, comprise irradiation with a laser that radiates light onto the growing first semiconductor layer in predetermined and specifically selected regions. This light, through absorption in the growing first semiconductor layer or an underlying layer, such as an already grown layer and / or a growth substrate, leads to local and inhomogeneous heating in these regions, so that different effective growth temperatures prevail for the growing first semiconductor layer in different regions. The light irradiation thus has, in particular, at least one spectral component that can be absorbed in the first semiconductor layer and / or a layer or structure arranged therebelow in the growth direction, such as the temperature distribution structure.The locally varying light irradiation can in particular be designed such that one or more regions can be irradiated simultaneously or successively on the growth substrate, the areal dimensions of which are smaller than those of the semiconductor chip.

[0042] Furthermore, the light irradiation can be pulsed. Particularly in conjunction with a moving, for example, rotating, growth substrate, pulsed irradiation can irradiate predetermined separate regions that move beneath the light beam. Furthermore, light can be directed specifically to predetermined regions by a light deflection device, for example, made of or including a mirror. These measures make it possible to scan the area on which the first semiconductor layer is grown. In this case, it may be possible to use a single light beam, in particular a single laser beam.Alternatively or additionally, a plurality of light sources that can be controlled synchronously or independently of one another, in particular a plurality of laser light sources that can be controlled synchronously or independently of one another, can be used to generate a locally varying light irradiation, which, depending on the control, can, for example, illuminate a plurality of areas and thus warm them up locally.

[0043] The described local heating based on light irradiation for controlling the temperature distribution can also be coupled with the in-situ measuring devices typically present in the growth reactor, i.e., temperature measuring devices and / or measuring devices for measuring wafer curvature. This allows the light output radiated onto each growth substrate to be locally adjusted, for example, based on the current curvature data based on a curvature measurement and / or a spatially resolved temperature measurement, so that, in a first step, the temperature profile during the growth phase, in particular each growth phase, can be homogenized. The homogenization can compensate for temperature differences on the growth substrate as well as between multiple growth substrates simultaneously intended for coating in the reactor.In a second step, a targeted modulation can be applied to the homogenized temperature profile so that the desired lateral inhomogeneous temperature distribution can be created on the growth substrate, making it possible to create the desired regions of the first semiconductor layer with different material compositions. The second step can be further improved by applying special markings in the form of alignment or trigger markings to the growth substrate, particularly before the process. These can be detected during the growth process as part of the light irradiation, so that the temperature profile can be adjusted to these markings. This makes it possible to precisely assign the regions with the different material compositions and thus the different wavelength ranges to the chip structures during the further course of the manufacturing process.

[0044] The temperature distribution structure can have at least one temperature distribution structure element that causes a local increase or decrease in the temperature of the growing first semiconductor layer. The temperature distribution structure element can have a lateral extent, at least along one extension direction, that is smaller than a lateral extent of the semiconductor chip, so that the local temperature change can be effected in a partial region of the semiconductor chip. In particular, the temperature distribution structure can have a plurality of temperature distribution structure elements that are arranged regularly and / or periodically in the lateral direction according to the intended inhomogeneous lateral temperature distribution profile. The temperature distribution structure element(s) can be formed, for example, in the form of mutually separate islands and / or line structures.

[0045] The temperature distribution structure mentioned in the following description can represent one or a plurality of temperature distribution structure elements. In particular, the following embodiments and features relating to the temperature distribution structure can be combined with one another, so that different temperature distribution structure elements can also be present, which, in combination, can achieve the desired temperature distribution.

[0046] Depending on the desired temperature-changing effect of the temperature distribution structure, it can comprise or be made of a dielectric material, a semiconducting material, a metal, or a plurality or combination thereof. Dielectric materials can, for example, locally influence thermal conductivity and thus, through improved or reduced heat supply or dissipation, cause a local increase or decrease in the temperature in the growing first semiconductor layer. Semiconducting and metallic materials can also influence thermal conductivity and / or be specifically heated by irradiation with light or other suitable electromagnetic radiation, such as microwave radiation. The electromagnetic radiation can, for example, be irradiated uniformly and over a large area or in a locally variable manner.

[0047] The temperature distribution structure can, for example, comprise or be made of a different material than the growth substrate. Furthermore, it may also be possible for the temperature distribution structure to comprise the same material as the growth substrate. In this case, the temperature distribution structure and the growth substrate can be formed in one piece.

[0048] According to one embodiment, the temperature distribution structure is arranged on a side of the growth substrate facing away from the first semiconductor layer. In other words, the growth substrate has a rear side on which the temperature distribution structure is arranged, and a front side on which the first semiconductor layer is grown. Alternatively or additionally, it may also be possible for the temperature distribution structure to be arranged on a side of the growth substrate facing the semiconductor layer. In this case, the temperature distribution structure can be arranged below the growing first semiconductor layer in the growth direction and thus between the growth substrate and the first semiconductor layer. Alternatively or additionally, it may also be possible for the temperature distribution structure to be embedded in the growth substrate and / or in a semiconductor layer on the growth substrate.

[0049] It can be particularly advantageous if the temperature distribution structure is arranged in direct contact with the growth substrate. This can mean, in particular, that the temperature distribution structure is arranged directly on the back and / or front side of the growth substrate or even embedded in the growth substrate.

[0050] According to a further embodiment, the temperature distribution structure is at least partially covered with a protective layer. This can mean that the temperature distribution structure is covered with a protective layer as viewed from the growth substrate and / or that a protective layer is arranged between the temperature distribution structure and the growth substrate. If the temperature distribution structure is covered on all sides by a protective layer, this can in particular be embedded in the protective layer. The protective layer can in particular be provided and designed so that the growth process during the growth of the first semiconductor layer and in particular of the semiconductor layer sequence with the first semiconductor layer is not negatively influenced by the temperature distribution structure. For example, outgassing or evaporation of material of the temperature distribution structure can be prevented by the protective layer.

[0051] According to a further embodiment, the temperature distribution structure and / or the protective layer remain at least partially or even entirely in the finished semiconductor chip. This can be the case, for example, if the temperature distribution structure is arranged on the side of the growth substrate facing the first semiconductor layer or is embedded in the growth substrate and the growth substrate remains at least partially in the semiconductor chip. Furthermore, it can also be possible for the temperature distribution structure to be arranged on the rear side of the growth substrate facing away from the first semiconductor layer and for the growth substrate to remain in the semiconductor chip together with the temperature distribution structure. Alternatively, it can also be the case that the temperature distribution structure does not remain in the semiconductor chip or only remains partially in the semiconductor chip and is at least partially or completely removed before the semiconductor chip is completed.For example, at least partial or complete removal of the temperature distribution structure can be carried out as part of at least partial removal, i.e. thinning, or complete removal of the growth substrate.

[0052] According to a further embodiment, the temperature distribution structure is designed for the targeted local heating of regions of the growing first semiconductor layer. In this case, the one or more temperature distribution structure elements can be designed as heating elements. For example, a temperature distribution structure element designed as a heating element can comprise a material that absorbs electromagnetic radiation, in particular a semiconductor or a metal. Furthermore, the one or more temperature distribution structure elements can be designed as temperature-conducting elements, which can conduct heat provided by a carrier carrying the growth substrate to the growing first semiconductor layer better than laterally adjacent material, for example the growth substrate or a semiconductor layer.

[0053] According to a further embodiment, the temperature distribution structure is designed for the targeted local reduction of the temperature of regions of the growing first semiconductor layer. In this case, the one or more temperature distribution structure elements can be designed as thermal barrier elements that are less able to conduct heat provided by a carrier carrying the growth substrate to the growing first semiconductor layer than laterally adjacent material, for example, the growth substrate or a semiconductor layer.

[0054] According to a further embodiment, one or a plurality of temperature distribution structural elements each have an elevation and / or a depression in the growth substrate. Alternatively, the one or the plurality of temperature distribution structural elements can be applied to the growth substrate and, together with the growth substrate, each form an elevation and / or a depression. For example, a temperature distribution structural element can have or form a depression in or on the growth substrate, in which a thermal barrier material with a lower thermal conductivity than the growth substrate is arranged. Alternatively or additionally, it may also be possible for a temperature distribution structural element to have or form an elevation in the growth substrate.Such topographically formed temperature distribution structure elements can, for example, achieve a targeted locally varying thermal coupling to a carrier on which the growth substrate is arranged.

[0055] According to a further embodiment, the protective layer comprises a dielectric material. For example, the protective layer can be formed by an oxide and / or nitride and / or oxynitride with a metal and / or semimetal, for example, silicon oxide, titanium oxide, aluminum nitride, and / or aluminum oxide. To achieve the best possible protective effect, it may be advantageous if the protective layer is applied using a process that allows for the densest possible layer formation. For example, an atomic layer deposition process may be advantageous for this purpose.

[0056] The semiconductor chip comprises a semiconductor layer sequence with a first semiconductor layer which has a lateral variation of a material composition and a constant thickness along at least one extension direction, wherein - the semiconductor chip is designed as a laser diode chip and has a laser strip in which light is generated during operation and a facet via which light is emitted during operation, - the first semiconductor layer has at least a first region and second regions laterally adjacent thereto, - the first area and the second areas have the same material system, - the material composition of the first region is different from the material composition of the second regions, wherein the first region and the second regions have the same thickness, - the first region is strip-shaped in the region of the laser stripe, - second regions are formed in the lateral direction transverse to the direction of extension of the laser strip on both sides next to the first region, and - the material composition in the first and second regions is selected such that a band gap in the second regions is smaller than a band gap in the first region, and - the first semiconductor layer is at least part of an active layer.

[0057] Further advantages, advantageous embodiments and further developments emerge from the examples and embodiments described below in conjunction with the figures.

[0058] They show: Fig. 1 a schematic representation of a method for producing a semiconductor chip according to an example, Fig. 2A to 2E are schematic diagrams of semiconductor chips according to further examples, Fig. 2F to 2J are schematic representations of semiconductor chips according to various embodiments, Fig. 3, 4A, 4C and 5A to 5C are schematic diagrams of semiconductor chips according to further examples, Fig. 4B, Fig. 4D, and Fig. 4E schematic representations of semiconductor chips according to further embodiments, Fig. 6A to 6D are schematic representations of variations of the material composition of the first semiconductor layer according to further embodiments and Fig. 7A to 10F are schematic illustrations of features of methods for manufacturing semiconductor chips according to further examples.

[0059] In the exemplary embodiments and figures, identical, similar, or similarly functioning elements may be provided with the same reference numerals. The illustrated elements and their relative sizes are not to be considered to scale; rather, individual elements, such as layers, components, structural elements, and regions, may be exaggerated for clarity and / or clarity.

[0060] In Fig. 1 shows a method for producing a semiconductor chip according to an example, in which the semiconductor chip is produced with a first semiconductor layer with a lateral variation of a material composition. For this purpose, in a first method step 1000, a surface is provided on which the first semiconductor layer is grown. The first semiconductor layer can preferably be part of a semiconductor layer sequence which, in addition to the first semiconductor layer, has a plurality of further semiconductor layers. The surface provided for growing the first semiconductor layer can be formed by a growth substrate or a semiconductor layer grown on a growth substrate, which can also be part of an already grown sublayer stack of the semiconductor layer sequence.

[0061] In a further method step 2000, the first semiconductor layer sequence is grown on the provided surface. This may also mean that one or more further semiconductor layers of the semiconductor layer sequence can be grown on the surface before the first semiconductor layer is grown. During the growth process for growing the first semiconductor layer, an inhomogeneous lateral temperature distribution is generated along at least one extension direction of the growing first semiconductor layer. The inhomogeneous lateral temperature distribution during the growth process causes a lateral variation in the material composition of the first semiconductor layer.In other words, this means that the material provided and supplied for growing the first semiconductor layer is deposited on at least two or more surface regions of the provided surface, which have different temperatures, during the growth process. The composition of the growing material depends on the local temperature of the respective surface region, so that the different temperatures in the at least two or more surface regions result in different material compositions. Accordingly, the first semiconductor layer has at least two or more regions with different material compositions, which are arranged laterally adjacent to one another along at least one extension direction of the first semiconductor layer.The temperature differences between the surface areas of the provided surface can be greater than or equal to 1 K, or greater than or equal to 2 K, or greater than or equal to 5 K, or even greater than or equal to 10 K. Between two adjacent surface areas with different temperatures, the surface temperature can change abruptly, i.e., essentially in steps, as far as technically possible, or continuously with a desired temperature profile.

[0062] In a further method step 3000, the semiconductor chip is completed after the growth of the first semiconductor layer with the lateral variation of the material composition. This may mean, for example, that, among other things, one or more further semiconductor layers of the semiconductor layer sequence and / or one or more passivation layers and / or one or more contact layers are applied. Alternatively or additionally, other processing steps such as etching processes and other structuring processes, as well as dicing steps for dicing a wafer composite into individual semiconductor chips, may also be performed.

[0063] Further features of the method for producing the semiconductor chip, as well as further features of the semiconductor chip produced in this way, are described in the following figures. However, the exemplary embodiments described below should not be understood as limiting the possible method features and the features of the semiconductor chips that can be produced using the method to only the features specifically described below. Rather, the following exemplary embodiments are to be understood purely as examples of possible method features and features of the semiconductor chips that can be produced using the method.

[0064] In connection with the Fig. 2A to 5C, embodiments and examples of semiconductor chips 100 are described. The semiconductor chips 100 can be manufactured in particular using a method according to the example of Fig. 1, i.e., a method in which, during a growth process for growing a first semiconductor layer 1, an inhomogeneous lateral temperature distribution is generated along at least one extension direction of the growing first semiconductor layer 1, such that a lateral variation in a material composition of the first semiconductor layer 1 is produced. The semiconductor chips 100 shown thus have a first semiconductor layer 1 which, along at least one extension direction, has a lateral variation in a material composition caused by a laterally varying temperature distribution during a growth process.

[0065] In the exemplary embodiments and examples shown, the first semiconductor layer 1 is, purely by way of example, part of a semiconductor layer sequence which, in addition to the first semiconductor layer 1, has, for example, a second semiconductor layer 2 and a third layer 3, between which the first semiconductor layer 1 is arranged. Each of the layers 1, 2, 3 of the semiconductor layer sequence can have or consist of one or more layers. The layers of the semiconductor layer sequence are arranged on top of one another along a growth direction. The growth direction can also be referred to as the vertical direction. Perpendicular to the growth direction, the layers of the semiconductor layer sequence have an extension along extension directions in the lateral direction, wherein the lateral extension is preferably greater than the thickness of the layers in the vertical direction.The semiconductor layer sequence can be grown in particular in the wafer composite, which can then be separated into a plurality of semiconductor chips 100.

[0066] For example, the third layer 3 can have a substrate, which can be electrically conductive or electrically insulating and on which the further layers of the semiconductor layer sequence are applied. The substrate can be a growth substrate as described above in the general part, on which the semiconductor layers of the semiconductor layer sequence are grown using an epitaxial growth process such as MOVPE or MBE. Alternatively, the substrate can be a so-called carrier substrate, onto which the semiconductor layers of the semiconductor layer sequence are transferred after growth on a growth substrate. The growth substrate can be thinned or completely removed after the growth process, so that it is also possible for layer 3 in the finished semiconductor chip 100 to have no substrate.

[0067] In the examples and examples of the Fig. 2A to 4E, the semiconductor chips 100 are designed purely by way of example as edge-emitting laser diode chips with an active layer for generating light, in particular laser light. The first semiconductor layer 1 can in particular be formed by at least a portion of a waveguide layer and / or the active layer. In other words, the first semiconductor layer 1 can be a portion of a waveguide layer and / or a portion of an active layer and / or be or comprise a waveguide layer and / or be or comprise an active layer. Furthermore, the first semiconductor layer 1 can also be formed by a plurality of layers which together form at least a portion of a waveguide layer and / or at least a portion of an active layer and / or a waveguide layer and / or an active layer.

[0068] In addition to the first semiconductor layer 1, the semiconductor layer sequence of the semiconductor chips 100 can comprise further functional semiconductor layers, such as one or more layers selected from waveguide layers, cladding layers, buffer layers, and semiconductor contact layers, which can be part of the second semiconductor layer 2 and the third layer 3 or which, individually or in combination, can form the second semiconductor layer 2 and the third layer 3 of the semiconductor layer sequence. Furthermore, the first semiconductor layer 1 can also comprise such a layer.

[0069] A contact layer 4 comprising a bondable and / or solderable metal is applied to the semiconductor layer sequence for electrically contacting the semiconductor chips 100. The contact layer 4 can also comprise a corresponding layer sequence consisting of multiple metal layers. In addition to a pure metal, the term "metal" can also refer to mixtures, alloys, and compounds with or consisting of multiple metals that have properties suitable for electrical contacting and electrical connection. Suitable metals for the contact layer 4 can be one or more selected from gold, aluminum, silver, titanium, platinum, nickel, palladium, rhodium, and tungsten, alone or in combination.

[0070] The semiconductor chips 100 have at least one further contact layer, which is not shown in the figures for the sake of clarity and which, together with the contact layer 4, enables an electrical connection of the semiconductor chips 100. For example, the third layer 3 can be electrically conductive, and the further contact layer is applied to a side of the third layer 3 facing away from the first semiconductor layer 1. Alternatively, the further contact layer can be arranged on a correspondingly exposed part of the top side of the semiconductor chip 100 next to the contact layer 4 shown.

[0071] In at least some embodiments and examples, the semiconductor chips 100 have a passivation layer 5 in some regions, i.e., in partial regions between the contact layer 4 and the semiconductor layer sequence, which electrically insulates a portion of the upper side of the semiconductor layer sequence from the contact layer 4. The passivation layer 5 may, for example, comprise or be composed of an electrically insulating oxide, nitride, or oxynitride, or a combination of several such materials. For example, the passivation layer may comprise one or more of the following materials: aluminum oxide, silicon oxide, silicon nitride, silicon oxynitride, or titanium oxide.The passivation layer 5 may make it possible to provide a contact layer 4 with a large contact area, which is large enough for external electrical contacting of the semiconductor chip 100, for example, by means of a solder connection or a bonding wire, while the semiconductor layer sequence is electrically connected in a smaller area by the electrical contact layer 4. The contact area between the contact layer 4 and the semiconductor layer sequence can, in particular, define the area of ​​the active layer in which light generation is desired and can accordingly be formed, for example, in a strip shape.In the case of laser diode chips, the strip-shaped contact region can preferably extend from a front side surface of the semiconductor layer sequence, which forms an outcoupling facet for light emission, to an opposite rear side surface of the semiconductor layer sequence, which forms a reflective rear facet. Suitable layers, such as partially or fully reflective layers and layer combinations, can be applied to the facets according to the desired functionalities.

[0072] Purely by way of example, the first semiconductor layer 1 and preferably the semiconductor layer sequence of the semiconductor chips 100 are based on the III-V compound semiconductor material system InAlGaN described above in the general part. Thus, in the illustrated embodiments and examples, the material composition of the first semiconductor layer 1 can vary in the lateral direction with respect to at least one of the crystal constituents of InAlGaN. Particularly preferably, the material composition varies with respect to the indium content, which is particularly dependent on the growth temperature. Thus, at typical growth temperatures, the incorporated indium content can decrease with increasing growth temperature, so that in regions of the growing first semiconductor layer 1 where a lower growth temperature prevails compared to other regions, greater indium incorporation and thus a resulting higher indium content can be achieved.

[0073] Depending on the lateral variation of the material composition along at least one extension direction, properties of the first semiconductor layer 1 can vary along this extension direction. In the InAlGaN material system, for example, a higher indium content can result in a higher refractive index, a narrower band gap, and an increased optical absorption. Accordingly, a lower indium content can result in a narrower refractive index, an increased band gap, and a reduced optical absorption.

[0074] Particularly preferably, the layer thickness of the first semiconductor layer 1 can be constant in the exemplary embodiments and examples shown, as shown in the figures. In particular, the thickness of the first semiconductor layer 1 can vary by no more than 10%, no more than 5%, or particularly preferably no more than 1%, regardless of the material composition of different regions, as described below.

[0075] The Fig. The semiconductor chip 100 shown in Figure 2A is designed as a so-called single-emitter oxide stripe laser and has a semiconductor layer 1 with regions 11, 12 arranged laterally next to one another, which have a different material composition. Region 11 is strip-shaped, corresponding to the contact region arranged above it between the semiconductor layer sequence and the contact layer 4, and borders regions 12 in a lateral direction transverse to the extension direction of the strip. When viewed from the coupling-out facet or the rear surface of the semiconductor chip 100, regions 12 are thus arranged on both sides, i.e., to the left and right of region 11. Region 11, which, when viewed from the coupling-out facet, can have a width in the range of a few micrometers to a few tens of µm, preferably forms the laser stripe corresponding to the region intended for light generation.This means that the width of region 11 preferably corresponds to the width of the laser stripe, i.e., the light-generating region, the latter being essentially determined by the width of the contact region between contact layer 4 and the semiconductor layer sequence. However, the width of region 11 can also be larger or smaller than the width of the laser stripe, for example, by 50%, 25%, or 10%, or even by values ​​between the specified values.

[0076] Region 11 has a higher indium content than the laterally adjacent regions 12, so that regions 12 have a lower refractive index and a larger band gap than region 11. Due to the smaller band gap, region 11 forming the laser stripe is thus a region with a larger corresponding wavelength than the adjacent regions 12 on either side. Due to the difference in the refractive index and the band gap, index guidance of the light generated in the active layer in the laser stripe can be achieved during operation of the semiconductor chip 100, which is already "built in" after epitaxial growth in the semiconductor chip 100. This may make it possible to achieve index guidance without a ridge waveguide structure common in the prior art, so that the associated etching process is not required.In addition, absorption losses in regions 12 are reduced due to the increased band gap compared to region 11 and the correspondingly reduced wavelength next to the laser stripe. Furthermore, current spreading in the active layer is reduced, especially in the case of a quantum well. Both effects can have a positive impact on the lasing threshold and the characteristic slope.

[0077] For conventional ridge waveguide structures, the etch depth must be maintained with an accuracy of a few nanometers. Etching that is too shallow can cause current spreading and thus weak guidance, which can result in degraded performance, poorer characteristic linearity, and reduced yield. Etching that is too deep can lead to stability problems and nonlinearities in the optical power dependence on the operating current, so-called "kinks." Accordingly, the etching process for producing conventional ridge waveguide structures is a complex manufacturing process. Furthermore, overmolding the conventional ridge waveguide structure with a metallic contact layer can be critical and increase the risk of so-called burn-off.Due to the surface structure formed by a conventional ridge waveguide structure, cooling problems may still occur when mounting the laser diode chip with the ridge side facing down.

[0078] The incorporation of the index guide into the first semiconductor layer 1 in the form of a planar structure during growth can result in improved yield, better laser performance, improved characteristic linearity, and greater component stability for the semiconductor chip 100 produced in this way, with regard to the described problems of ridge etching. Furthermore, the manufacturing process can be simpler than for conventional laser diodes with a ridge waveguide structure. Furthermore, the application of the contact layer 4 and thus the overmolding of the semiconductor layer sequence with a metallic layer is simpler and less error-prone, which can result in increased stability.Furthermore, the planar structure provided for index guidance in the first semiconductor layer 1, which also results in a correspondingly planar structure for the contact layer 4, can result in improved heat dissipation when the semiconductor chip 100 is mounted with the contact layer 4 facing downwards.

[0079] The Fig. The semiconductor chip 100 shown in Figure 2B is designed as a so-called single-emitter broad-area laser and, in comparison to, for example, the Fig. 2A has a wider region 11 with a higher indium content compared to the laterally left and right adjacent regions 12. The wider region 11 essentially corresponds to the Fig. 2A now also wider active region, which forms the laser stripe and is intended for light generation. Due to the larger width of the region intended for light generation, a contact layer 4 that is sufficiently wide for external contacting can be applied to the semiconductor layer sequence without a passivation layer 5 arranged in between. Fig. The semiconductor chip 100 shown in Figure 2B is characterized by very simple processing and, at the same time, by improved laser performance compared to the prior art due to the combination of Fig. 2A already described integrated wave guide.

[0080] In the Fig. 2C to 2E semiconductor chips 100 are shown which, in comparison to the previous examples and in particular in comparison to the example of Fig. 2A have a second semiconductor layer 2 above the first semiconductor layer 1, which additionally has a ridge waveguide structure 21 above the region 11 with the increased indium content. This, in combination with the waveguide already incorporated into the first semiconductor layer 1 by the growth process described, allows for very strong index guidance, improved yield, higher laser performance, and improved far-field properties to be achieved. Compared to conventional laser diodes, which only have a ridge waveguide structure, the semiconductor chips 100 of the examples Fig. 2C to 2E also require a lower etching depth during the manufacture of the bridge, which can result in better aging stability and a lower susceptibility to errors in the manufacturing process.

[0081] By varying the lateral variations of the growth temperature during the growth process for producing the first semiconductor layer 1, the width of the region 11 can be varied in comparison to the width of the ridge waveguide structure 21, whereby different component properties can be produced using the same manufacturing process. As shown in Fig. 2C, the region 11 and the ridge waveguide structure 21 may have the same or at least substantially the same width. As shown in the Fig. 2D and Fig. 2E, the width of the region 11 may also be larger or smaller than the width of the ridge waveguide structure 21.

[0082] As in connection with the examples of Fig. 2A to 2E, either a ridge waveguide structure can be dispensed with or the depth of the ridge etching can be significantly reduced, since both the current limiting and the index guide can be incorporated into the semiconductor chip 100. Furthermore, it may be necessary to partially remove the contact layer 4, as shown in Fig. 2B is shown.

[0083] In Fig. 2F shows a substrate 6, on whose surface 61 the first semiconductor layer can be grown. The substrate 6 is designed as a growth substrate in the form of a wafer with a diameter of, for example, greater than or equal to 2 inches and less than or equal to 12 inches. In particular, the wafer can have a diameter of 2 inches, 4 inches, 6 inches, 8 inches, or 12 inches. With such a substrate 6, a plurality of semiconductor chips can be produced by applying the semiconductor layer sequence and the further layers of the semiconductor chips in the wafer composite and subsequent singulation. The substrate 6 can be used in a conventional coating process in which one or a plurality of such substrates are arranged on a suitable substrate carrier in a coating chamber.

[0084] Purely by way of example and not to scale, the positions of the previously described regions 11 and 12 as well as of some semiconductor chips 100 completed later are indicated on the substrate 6. Fig. Figure 2G shows a corresponding section with only one indicated semiconductor chip 100. The position of the contact layer 4 on the semiconductor chip 100 is also indicated. This can, as shown in the previous figures, be symmetrical to the first region 11 or, as in the Fig. 2F and Fig. 2G, be arranged laterally offset from the first region. The latter arrangement enables bondability of the contact layer 4 next to the laser stripe. Depending on the substrate size and the size of the semiconductor chips 100, the number of regions 11 and 12 and the semiconductor chips 100 can be different from those shown in Fig. 2F shown quantities may vary.

[0085] In connection with the Fig. 2H to 2J show further embodiments of semiconductor chips 100 which, in comparison to the previous embodiments, form multi-emitting laser diode chips in the form of laser bars or laser arrays.

[0086] In Fig. 2H shows an embodiment of a semiconductor chip 100, which is designed as a multi-emitting laser bar with a first semiconductor layer 1 having a plurality of strip-shaped regions 11 with a lower indium content arranged laterally next to one another, which correspond to a plurality of laser stripes and thus to a plurality of regions for light generation and which are separated from one another by regions 12 with a higher indium content. Contacting of the plurality of regions 11 is effected via a common contact layer 4. Particularly in the case of broad-area lasers, it can be advantageous if the laser stripes are located in regions 11 with a higher band gap and thus a correspondingly reduced corresponding wavelength, which are separated from one another by regions 12 with a lower band gap and thus a correspondingly increased corresponding wavelength.The regions 12, which accordingly exhibit increased optical absorption, serve as optical absorbers that can reduce or suppress the propagation of ring modes and / or crosstalk between the laser stripes and neighboring laser stripes. This concept can also be applied accordingly to individual diodes such as the semiconductor chips shown in the previous figures, and to laser arrays in which laser stripes can be controlled either individually, in groups, or jointly.

[0087] In the Fig. 2I and Fig. 2J is, as above in connection with the Fig. 2F and Fig. 2G, a substrate 6 with non-scale and purely exemplary positions and numbers of regions 11 and 12 and semiconductor chips 100 according to the embodiment of the Fig. 2H shown.

[0088] In Fig. Another example is shown in Figure 3. In particular, Fig. 3 again shows a substrate 6 with non-scale and purely exemplary positions and numbers of regions 11 and 12 and semiconductor chips 100. As an alternative to an arrangement of laterally adjacent regions 11, 12 of the first semiconductor layer with different material compositions along the laser ridge, such regions can also be arranged as in Fig. 3 indicated, running transversely to the laser bridge.

[0089] The semiconductor chips 100 according to the example of Fig. 3, in particular, exhibit a lateral variation in the material composition in the first semiconductor layer in a facet region, i.e., in a region of the first semiconductor layer that borders a facet. In other words, the semiconductor chips 100 to be fabricated on the substrate 6 are located primarily in first regions 11 with respect to the first semiconductor layer, while the facets of the semiconductor chips 100 are located in second regions 12 that have a different material composition compared to the first regions 11. In particular, the second regions 12 formed as facet regions have a higher band gap and thus lower absorption compared to the first regions 11 of the first semiconductor layer, which, viewed from the facets, are further away from the facets than the second regions.

[0090] In the InAlGaN material system, the bandgap increase in the second regions 12 can preferably be achieved by reducing the In content, in particular in a first semiconductor layer formed as an active layer. As a result, the first semiconductor layer in the second regions has a wavelength corresponding to the bandgap that is smaller than the corresponding wavelength in the first region 11. Although in Fig. 3 Single-emitter laser diodes are indicated, the shown lateral variation of the material composition of the first semiconductor layer can also be applied for multi-emitter laser diodes such as laser bars or laser arrays.

[0091] By increasing the band gap in the facet regions, the facet loading limit can be increased, thus reducing the risk of COD (catastrophic optical damage) at the facets, as absorption losses at the facets and thus the facet temperature during operation can be reduced. Since this non-absorbing facet technology does not require additional dopants or subsequent temperature processes, neither non-absorbing recombination centers are created nor is the contact layer 4 negatively affected. As a result of the improved facet loading limit, a higher optical output power can be achieved through higher current. Designs with multi-emitter laser diodes, such as in combination with the Fig. 2H to 2J can accordingly manage with fewer laser stripes, which can offer cost advantages.

[0092] It can be particularly advantageous in this context if, as in Fig. 3 as in the previous Fig. 2F, Fig. 2G , Fig. 2I and Fig. 2J, the contact layer 4 is different from the Fig. 2A to 2E and 2H, does not quite reach the facets, so that the semiconductor chips 100 are not energized in the facet regions during operation. This can further increase COD stability.

[0093] In the Fig. 4A to 4E are embodiments and examples of semiconductor chips 100, partially corresponding to the illustrations in the Fig. 2G and Fig. 2J during fabrication on substrates, which have combinations of the previously described lateral variations of the material composition of the first semiconductor layer. Furthermore, the Fig. 4A to 4E, the semiconductor chips 100 described have, purely by way of example, a ridge waveguide structure 21 as described in connection with the Fig. 2C to 2E. Alternatively, in conjunction with the embodiments and examples described below, embodiments are also possible which, like the embodiments and examples in the Fig. 2A, Fig. 2B and Fig. 2H do not have a ridge waveguide structure and / or a plurality of laser stripes.

[0094] The example of Fig. 4A has a combination of the factors associated with the Fig. 2C and Fig. 3, namely an increased band gap and thus a correspondingly reduced corresponding wavelength on both sides of the laser ridge and in the facet area by appropriately designed first and second regions 11, 12. In particular, the laser stripe lies in the first region 11, which is interrupted at the facets by the second region. This allows for low absorption losses and high COD protection.

[0095] The embodiment of the Fig. 4B has a combination of the features associated with the Fig. 2B, Fig. 2H and Fig. 3, namely an increased band gap and thus a correspondingly reduced corresponding wavelength in the region of the laser ridge and in the facet region as well as a reduced band gap and thus a correspondingly increased corresponding wavelength and increased absorption on both sides next to the laser ridge by appropriately formed first and second regions 11, 12. This can prevent the formation of ring modes and optical crosstalk and achieve a high COD protection.

[0096] The example of Fig. 4C has a combination of related to the Fig. 4A and Fig. 4B, namely an increased band gap and thus a correspondingly reduced corresponding wavelength on both sides of the laser ridge by correspondingly formed first and second regions 11, 12, as well as a reduced band gap and thus a correspondingly increased corresponding wavelength and increased absorption on both sides of the laser ridge by third regions 13 of the first semiconductor layer additionally formed on both sides of the second regions 12. The first and third regions 11 and 13 can be identical or at least similar in terms of their material compositions. In addition, a lateral variation of the material composition of the first semiconductor layer can also be present in the facet region. As a result, the previously described in connection with the Fig. 4A and Fig. 4B can be achieved. In particular, the Fig. The combination of regions of the first semiconductor layer with different, laterally varying material compositions shown in Figure 4C is characterized by low absorption losses and improved radiation behavior due to a lower proportion of scattered light.

[0097] The embodiment of the Fig. 4D has, like the embodiment of the Fig. 4B an increased band gap and thus a correspondingly reduced corresponding wavelength in the region of the laser ridge, as well as a reduced band gap and thus a correspondingly increased corresponding wavelength and increased absorption on both sides next to the laser ridge through appropriately designed first and second regions 11, 12. In addition, the first semiconductor layer has a third region 13 on both sides of the laser ridge within the first region 11, in which the material composition is selected such that the band gap is even higher compared to the first and second regions 11, 12. This makes it possible to achieve low absorption losses and improved radiation behavior due to a lower proportion of scattered light. The third region 13 can also be arranged, for example, only on one side of the laser ridge.

[0098] The embodiment of the Fig. 4E is like the embodiment of the Fig. 4B, but additionally has a third region 13 in the facet region, in which the material composition is selected in comparison to the first and second regions 11, 12 such that the band gap is even higher compared to the first and second regions 11, 12, whereby in addition to the advantages associated with the Fig. 4B, the absorption losses in the facet area can be reduced even further.

[0099] In the Fig. 5A to 5C show examples of semiconductor chips 100 formed as light-emitting diode chips. These chips have a contact layer 4 on a semiconductor layer sequence comprising a first semiconductor layer 1, which contact layer is formed at least partially as a bond pad, in the example shown in a corner of the chip top side. Below the bond pad, the first semiconductor layer 1, which may preferably be an active layer, has a lateral variation in the material composition in the form of a first region and, laterally adjacent thereto, a second region 12. The lateral variation in the material composition is designed such that in the second region 12 below the bond pad, the band gap in the material of the first semiconductor layer 1 is increased compared to a first region 11, which corresponds to the region of the first semiconductor layer 1 not covered by the bond pad.The second region 12 can, in particular, be a non-energized region of the first semiconductor layer 1 that is not intended for light generation. This can reduce or even prevent absorption in the non-energized region of the first semiconductor layer 1. For example, an electrically insulating layer, such as the passivation layer described above in connection with laser diodes, can be arranged between the bond pad and the semiconductor layer sequence.

[0100] Compared to, for example, the Fig. 5A shows the contact layer 4 of the semiconductor chip 100 according to the example of Fig. 5B, in addition to a bond pad, also has current-carrying bridges for current distribution. Below the current-carrying bridges, the material composition of the first semiconductor layer 1 can be varied accordingly in second regions 12 compared to the first regions 11, which correspond to the regions of the first semiconductor layer 1 not covered by the contact layer 4. This can prevent absorption losses below the current-carrying bridges.

[0101] In the example of Fig. 5C, the material composition of the first semiconductor layer 1, which is preferably formed as an active layer, is varied toward a lateral edge of the semiconductor chip such that the band edge of the quantum wells, and thus the band gap, of the first semiconductor layer 1 is increased toward the edge. For this purpose, the first semiconductor layer 1 has a second region 12 that laterally surrounds a first region 11. The second region 12 borders the edge of the semiconductor chip 100 all the way around and has a material composition that is correspondingly different from the first region 11. By increasing the band gap at the edge, leakage currents at the edge of the semiconductor chip 100 formed by the edge can be reduced, thereby increasing the performance and aging stability of the semiconductor chip 100.

[0102] In the Fig. 6A to 6D show exemplary band gap profiles of different regions of the first semiconductor layer according to the laterally varying material compositions. The profiles shown can be present alone or in combination in the previously shown embodiments. The vertical axis corresponds to a profile along an extension direction X of the first semiconductor layer in the lateral direction, while the vertical axis represents the band gap BG and thus the material composition variation.

[0103] As in Fig. As shown in Figure 6A, the transition between the regions with different material compositions can be sharply defined and, for example, step-like. Furthermore, the transition can also be continuous, for example, ramp-like, as shown in Fig. 6B is shown. In Fig. 6C shows a smooth transition, while in Fig. 6D shows a multi-step transition.

[0104] In addition to varying the material composition, the variations in the band gap in the different regions can be achieved additionally or alternatively by mixing heterointerfaces, a so-called quantum well intermixing.

[0105] In conjunction with the following figures, possibilities for generating inhomogeneous lateral temperature distributions for growing the first semiconductor layer are described. The inhomogeneous lateral temperature distribution is specifically generated during the growth of the first semiconductor layer by locally thermally influencing predetermined and specifically selected regions. In particular, the inhomogeneous lateral temperature distribution can be generated at least partially by a temperature distribution structure and / or by locally varying light irradiation, as described below. If a temperature distribution structure is used, it can remain in the semiconductor chip depending on the arrangement. Accordingly, the semiconductor chips described above can additionally have temperature distribution structures according to the following exemplary embodiments.

[0106] In the Fig. 7A to 7D show exemplary embodiments of a substrate 6, on whose surface 61 the first semiconductor layer can be grown. The substrate 6 is designed as a growth substrate in the form of a wafer with a diameter of, for example, greater than or equal to 2 inches and less than or equal to 12 inches. In particular, the wafer can have a diameter of 2 inches, 4 inches, 6 inches, 8 inches, or 12 inches. With such a substrate 6, a plurality of semiconductor chips can be produced by applying the semiconductor layer sequence and the further layers of the semiconductor chips in the wafer composite and subsequent singulation. The substrate 6 can be used in a conventional coating process in which one or a plurality of such substrates are arranged on a suitable substrate carrier in a coating chamber.

[0107] For example, in the Fig. 7A and Fig. 7C, the substrate 6 has a temperature distribution structure 7, which can specifically generate an inhomogeneous lateral temperature distribution along at least one extension direction of the first semiconductor layer to be grown. The temperature distribution structure 7 has temperature distribution structure elements 70, which are suitable and intended to influence the local temperature distribution on the surface 61 during the growth process. These can be heat-conducting elements, heating elements and / or heat barrier elements, as described below in connection with the Fig. 8A to 8K. Depending on the desired temperature-changing effect of the temperature distribution structure 7, it can comprise or be made of a dielectric material, a semiconducting material, a metal, or a plurality or combination of these materials. Dielectric materials can, for example, locally influence the thermal conductivity and thus, through improved or reduced thermal conduction, cause a local increase or decrease in the temperature on the surface 61 and thus in the growing first semiconductor layer.Semiconducting and metallic materials can also influence thermal conductivity and / or be specifically heated by irradiation with light or other suitable electromagnetic radiation, such as microwave radiation, so that more heat is generated in the region of the temperature distribution structure elements 70 and thus a higher temperature can be generated than in the neighboring regions. As described above, in the case of InAlGaN, for example, the indium content of the first semiconductor layer, which depends heavily on the growth temperature, can be adjusted and varied. Accordingly, properties of the first semiconductor layer, such as the refractive index, the band gap, and thus, if applicable, the emission wavelength and the absorption behavior, can be laterally varied.

[0108] In particular, the temperature distribution structure 7 comprises a plurality of temperature distribution structure elements 70, which are arranged regularly and / or periodically in the lateral direction according to the intended inhomogeneous lateral temperature distribution profile. The temperature distribution structure elements can, as shown, be designed, for example, in the form of separate islands and / or linear structures.

[0109] In the exemplary embodiment shown, the temperature distribution structure elements 70 have a lateral extent along the arrangement direction, i.e. in the exemplary embodiment shown in the lateral direction perpendicular to the main extension direction of the linear structures, which is smaller than a corresponding lateral extent of the semiconductor chips to be produced, so that the local temperature change of each of the temperature distribution structure elements 70 can be generated in a respective partial region of a subsequent semiconductor chip. By means of temperature distribution structure elements 70, the width of which along the arrangement direction is smaller than corresponding dimensions of the semiconductor chips, for example, the Fig. 2A to 2H described regions of the first semiconductor layer are produced.

[0110] Purely as an example, in the Fig. 7A to 7D, for the sake of clarity, only three strip-shaped temperature distribution structure elements 70 are shown, which are located on a rear side of the substrate 6 facing away from the surface 61. The resulting lateral inhomogeneous temperature distribution, which in the case of InAlGaN also corresponds to the indium distribution on the substrate 6, is shown in Fig. 7B. Depending on the size of the substrate 6 and the size of the semiconductor chips to be manufactured, which, for example, in the case of laser diode chips, can have lateral dimensions of less than 100 µm up to several 100 µm for single-emitter chips and up to one or more centimeters for laser bars and laser arrays, the number of semiconductor chips manufactured in the wafer assembly and thus also the number and dimensions of the temperature distribution structure elements 70 can vary considerably.

[0111] Due to the clearly visible temperature distribution structural elements 70, the chip manufacturing process can be very precisely adjusted to the areas with different material compositions. The temperature distribution structural elements 70 can be manufactured in any shape and arrangement using lithographic methods, for example, which enables a material composition tailored to the subsequent semiconductor chips and thus a corresponding variation of the desired properties on the substrate 6.

[0112] As described above, the temperature distribution structure 7 can preferably be arranged on the back side of the substrate 6, which is opposite the surface 61 provided for the growth process, so that the growth process on the surface 61 can proceed undisturbed by the temperature distribution structure 7. As shown in the Fig. 7A and Fig. 7C, the temperature distribution structure 7 can be arranged directly on the back of the substrate. Alternatively, it is also possible for the temperature distribution structure 7 to be covered by at least one protective layer, for example made of a dielectric material, or, as shown in Fig. 7D, is embedded between two such protective layers 8, 9 in order to prevent the growth process from being influenced by outgassing and / or evaporation of material from the temperature distribution structure 7. In the embodiment of the Fig. 7D, a first protective layer 8 is arranged between the temperature distribution structure 7 and the substrate 6, while a second protective layer 9 covers the temperature distribution structure 7. The protective layers 8, 9 can be made of the same or different materials.

[0113] Further features and embodiments of the temperature distribution structure 7 are described in the Fig. 8A to 8K, wherein in each case only a section of the substrate 6 and the semiconductor material 10 grown thereon and thus also of the temperature distribution structure 7 and the temperature distribution structure elements 70 is shown.

[0114] In particular, the temperature distribution structure 7 can have a plurality and / or a combination of the temperature distribution structure elements 70 described below. The temperature distribution structure elements 70 can, in particular, have a width in the lateral direction, which corresponds to a horizontal direction in the plane of the drawing, that is smaller than a width of the semiconductor chip to be manufactured above it. Furthermore, it can also be possible for a plurality of temperature distribution structure elements 70 to be located in the region of a semiconductor chip in order to produce a larger number of regions with different material compositions in the first semiconductor layer. The semiconductor material 10 can, for example, have one or more semiconductor layers grown on the substrate 6.

[0115] In Fig. 8A shows a temperature distribution structure 7 with a temperature distribution structure element 70, which is arranged directly on the rear side of the substrate 6 facing away from the surface 61. In particular, in the exemplary embodiment shown, the temperature distribution structure element 70 can comprise a different material than the substrate 6 and can be designed as a heating element that can be heated by irradiation with suitable electromagnetic radiation, so that the substrate 6 and thus also the semiconductor material 10 grown thereon can be heated to a higher temperature in the region above the temperature distribution structure element 70 than in the adjacent regions that are not arranged above the temperature distribution structure element 70.For example, the temperature distribution structure element 70 shown can comprise a semiconducting material such as silicon, which can be heated, for example, by irradiating it with light having a wavelength that lies within the absorption spectrum of the semiconducting material. Alternatively, the temperature distribution structure element 70 can also comprise, for example, a metal that can be heated by irradiating it with suitable electromagnetic radiation, such as microwave radiation.

[0116] The substrate 6 can rest on a substrate carrier during the growth of the semiconductor layer sequence with the temperature distribution structure 7, so that the temperature distribution structure 7 can simultaneously influence heat conduction between the substrate carrier and the substrate 6.

[0117] The substrate 6 can, for example, have a typical thickness in the range of 100 µm up to several 100 µm, for example 300 µm, so that the heat spread in the lateral direction in the substrate 6 can be kept low and a desired temperature profile can be generated on the surface 61. The fact that the temperature distribution structure 7 is arranged on the back of the substrate 6 results in little chemical influence from the temperature distribution structure 7 during the growth of the semiconductor material 10. Depending on whether the substrate 6 remains after the growth of the semiconductor material 10, is thinned, or is removed entirely, the temperature distribution structure 7 can also remain or be removed in the subsequently completed semiconductor chip. In particular, for example in the case of light-emitting diode chips, it may be possible for the temperature distribution structure 7 to remain in the chip.

[0118] In Fig. 8B shows an embodiment in which, in comparison to the previous embodiment, the temperature distribution structure 7 is arranged directly on the surface 61 of the substrate 6 provided for the growth process of the semiconductor material 10. The temperature distribution structure 7, which can be formed, for example, as in the previous starting example, is overgrown by the semiconductor material 10 during growth, for example by means of a so-called ELOG process (ELOG: "epitaxial lateral overgrowth"). For this purpose, the temperature distribution structure 7 preferably has a thickness in the growth direction of greater than or equal to 10 nm and less than or equal to 500 nm, or less than or equal to 300 nm, or less than or equal to 200 nm, or, particularly preferably, less than or equal to 100 nm.By arranging the temperature distribution structure 7 on the surface 61 intended for growth, and thus on the side of the substrate 6 facing the semiconductor material 10, heat spreading in the substrate 6 can be avoided, thereby achieving a sharper temperature profile. If the substrate 6 is not removed or only thinned after the semiconductor layer sequence has been grown, the temperature distribution structure 7 can remain in the subsequently completed semiconductor chip.

[0119] In order to protect the semiconductor material 10 from possible chemical impairments by the temperature distribution structure 7 and yet to avoid a temperature spread in the substrate 6, as in Fig. 8C, a protective layer 8 made of a preferably dielectric material, for example an oxide, nitride, or oxynitride described above in the general part, is applied over the temperature distribution structure 7. This protective layer 8, together with the substrate 6, encapsulates the temperature distribution structure element 70. For example, the protective layer 8 can be applied using an application method such as atomic layer deposition, which allows for the most hermetically sealed layer formation possible while simultaneously maintaining the smallest possible layer thickness. The protective layer 8 preferably does not extend over the entire surface 61 of the substrate 6, but rather, if possible, only covers the elements of the temperature distribution structure 7.

[0120] In Fig. 8D shows a further embodiment in which the temperature distribution structure 7 arranged on the back of the substrate 6, which as in Fig. 8A, also with a protective layer 8, as in connection with Fig. 8C. The protective layer 8 can cover the entire back of the substrate 6 or, alternatively to the embodiment shown, only the temperature distribution structure element 70. In addition to avoiding chemical influences on the growth process, a suitable protective layer 8 can also prevent, for example, undesirable possible adhesion or sticking to the substrate carrier.

[0121] As in Fig. 8E, the temperature distribution structure element 70 can also be surrounded on all sides by a protective layer 8 and thus embedded in it. In this case, the temperature distribution structure 7 is not arranged directly on the substrate 6. Instead of the shown formation of an embedding protective layer 8, alternatively, as described above in connection with Fig. 7D, two protective layers may also be used, between which the temperature distribution structure element 70 is arranged.

[0122] As in connection with the Fig. 8F and Fig. 8G, the temperature distribution structure 7 can also be embedded in the semiconductor material 10 or in the substrate 6. For this purpose, a semiconductor material with a small band gap can particularly preferably be used to produce corresponding temperature distribution structure elements 70 designed as heating elements. Alternatively, the temperature distribution structure 7 can also have a different thermal conductivity than the surrounding substrate material 6 or semiconductor material 10, so that the temperature distribution structure element 70 can be designed as a heat-conducting element or heat barrier element integrated into the substrate 6 or the semiconductor material 10. The Fig. 8F and Fig. The temperature distribution structures 7 shown in Figure 8G can be produced, for example, by implantation. Furthermore, it is also possible for the substrate 6 or the semiconductor material 10 together with the substrate 6 to form a quasi-substrate with overgrown temperature distribution structures 7 and a subsequently planarized surface.

[0123] In connection with the Fig. 8H to 8K show temperature distribution structures 7 with temperature distribution structure elements 70, which have or consist of one or more elevations and / or depressions. For example, a surface structure with elevations and depressions, which form temperature distribution structure elements 70, can be formed in the rear side of the substrate 6 facing away from the surface 61. Because the substrate 6 rests on a substrate carrier only with the elevations, the temperature coupling is better there and, as a result, the temperature is higher locally in the regions above the elevations than in the regions above the adjacent depressions. This enables a different thermal coupling of the substrate 6 to a substrate carrier. In this case, the temperature distribution structure elements 70 formed as elevations can have the same material as the substrate 6 and, particularly preferably, can be formed integrally with the substrate 6.

[0124] As in Fig. As shown in Fig. 8I, the elevations and depressions formed by the temperature distribution structure 7 can also be formed by a material different from the substrate 6.

[0125] In Fig. 8J shows a temperature distribution structure 7 which is a combination of the Fig. 8A and Fig. 8H. Firstly, a temperature distribution structure element 70 configured as a heating element is arranged on the back of the substrate. Additionally, temperature distribution structure elements 70 configured as depressions are provided in the back of the substrate, forming separating trenches that act as a thermal barrier, thereby reducing heat spread in the substrate 6 and thus allowing a sharper temperature profile to be generated.

[0126] As in Fig. 8K, a material with a lower thermal conductivity than the substrate 6 can additionally be arranged in the recesses on the substrate backside in order to increase the thermal barrier function of the temperature distribution structure elements 70 thus formed.

[0127] In Fig. 9A schematically shows a typical temperature profile on the surface 61 of a wafer, which can be used as substrate 6 for the method described here, in a conventional substrate carrier. It can be seen that the temperature distribution over the substrate surface 61 is not homogeneous, but varies on a length scale and in lateral directions that are independent of the arrangement of the semiconductor chips to be produced in the wafer assembly. A corresponding temperature distribution can, for example, also be present during the growth of the first semiconductor layer. This temperature profile affects, as previously described, the material composition of the semiconductor layers of the semiconductor chips, so that the semiconductor chips manufactured in the wafer assembly can have different properties from one another. To avoid this, in an additional method step, as in Fig. 9B, the temperature profile on the surface 61 intended for the growth process can be homogenized and, starting from this, as shown in Fig. 9C, can be adjusted according to the desired inhomogeneous lateral temperature distribution.

[0128] As in the embodiments according to the following Fig. 10A to 10F, in conventional coating systems, a plurality of substrates 6 are usually arranged on a substrate carrier 200 in order to be able to coat them simultaneously. In order to achieve the most homogeneous coating possible, the substrate carrier 200 rotates, as shown by the arrow indicating the direction of rotation 201. The substrates 6 are heated to the desired growth temperature via the substrate carrier 200, whereby inhomogeneous temperature distributions such as those shown exemplarily in Fig. 9A may be present. In order to homogenize the respective temperature profile on the surface 61 of the substrates 6, which may be different for each substrate 6, it can first be measured, for example, using an infrared detector.

[0129] Furthermore, each of the substrates 6 is heated in specific areas in order to generate the most homogeneous temperature profile possible on their respective surface 61. Such heating can, for example, as in Fig. 10A, by means of locally varying light irradiation, i.e. by irradiating a suitably variable light beam 300, which can be absorbed, for example, in the substrate material or a semiconductor material applied to the substrates 6. The light beam can, for example, be a single or multiple beam from one or more laser sources and can be directed onto selected partial areas of the surfaces 61 of the substrates 6 by means of a suitable light deflection device 400, for example with a mirror or another suitable device. Alternatively, as in Fig. 10B, a plurality of light sources 301, for example, a plurality of laser sources in a laser array, can also be used, which can preferably radiate light onto the surface 61 of a substrate 6 independently of one another. This preferably allows the entire surface 61 of the substrates 6 to be covered, wherein the light irradiation takes into account the rotational movement of the substrate carrier 200 and the determined individual temperature profiles of the substrates 6.

[0130] The inhomogeneous lateral temperature profile desired for growing the first semiconductor layer can be generated using an additional temperature distribution structure as described above. Alternatively, it may also be possible to generate it using the described light irradiation, whereby the heating profile to be implemented by the light heating is adjusted accordingly compared to a pure homogenization of the temperature profile. Furthermore, it may also be possible to use the light heating formed by locally varying light irradiation solely to generate a desired inhomogeneous temperature profile, without an additional homogenization step.

[0131] The locally varying light irradiation during the growth of the first semiconductor layer can, as described above, comprise irradiation with a laser that irradiates one or more light beams 300 onto the growing first semiconductor layer in predetermined and specifically selected regions. This light beam 300, through absorption in the growing first semiconductor layer or an underlying layer, such as an already grown layer and / or the substrate 6, leads to local and inhomogeneous heating in these regions, so that different effective growth temperatures prevail for the growing first semiconductor layer in different regions. The locally varying light irradiation can, in particular, be designed such that one or more regions whose areal dimensions are smaller than those of the semiconductor chips can be irradiated simultaneously or sequentially on the substrate 6.In this case, the light irradiation can also be pulsed. The described light deflection device 400 and / or the use of a plurality of light sources 301 can make it possible to scan the area on which the first semiconductor layer is grown.

[0132] As in the Fig. 10A to 10F, the substrates 6 or alternatively the substrate carrier 200 can be formed with at least two markings 62, which serve as reflectors or alignment marks in order to be able to synchronize the light beam 300. As shown in the Fig. 10C and Fig. 10D is shown by way of example, for example, at a time T1 the light beam 300 designated by A can strike a marking 62 and be reflected by it ( Fig. 10C), while at the same or later time T2 the light beam 300 designated B hits a marking 62 and is reflected by it ( Fig. 10D). The reflected signals from the markings 62 can be used, on the one hand, to enable precise synchronization of the light beam 300 onto a substrate 6. Additionally, it may be possible to calculate a rotation of the substrate 6 in the substrate carrier 200 based on the possibly time-shifted signals from the at least two markings 62 and thus align the desired temperature profile to match the markings 62. The markings 62 can be used both during homogenization of the temperature profile and later in the chip process to adjust the chip structures to match the temperature profile.

[0133] It is also possible to have multiple light sources in the form of several individual light sources or, as in Fig. 10B, in the form of several pluralities of light sources 301 for simultaneously heating several substrates 6.

[0134] This may make it possible to achieve a more uniform temperature distribution during the rotation of the substrate carrier 200. Furthermore, more power can be applied locally, since multiple light sources can illuminate the same area on a substrate 6, thus enabling stronger temperature gradients. By staggering the arrangement, for example, of several laser arrays formed by a plurality of light sources 301, the spatial resolution can also be improved.

[0135] As in Fig. 10F, the plurality of light sources 301 can also illuminate only partial areas of the substrates 6. This can, for example, simplify the assignment of reflected signals from the markings 62. Furthermore, detectors 500 can be arranged on the substrate carrier 200 or in its vicinity in order to be able to directly detect the signals reflected from the markings 62. List of reference symbols 1 first semiconductor layer 2 second semiconductor layer 3 third layer 4 Contact layer 5 Passivation layer 6 Substrat 7 Temperature distribution structure 8, 9 protective layer 10 Semiconductor material 11, 12, 13 area 21 rib waveguide structure 61 Surface 62 Marking 70 Temperature distribution structure element 100 semiconductor chips 200 carriers 201 Direction of rotation 300 light beam 301 Plurality of light sources 400 light deflection device 500 detector 1000, 2000, 3000 process step

Claims

[1] Semiconductor chip (100) with a semiconductor layer sequence with a first semiconductor layer (1) which has a lateral variation of a material composition and a constant thickness along at least one extension direction, wherein - the semiconductor chip (100) is designed as a laser diode chip and has a laser strip in which light is generated during operation and a facet via which light is emitted during operation, - the first semiconductor layer (1) has at least a first region (11) and second regions (12) laterally adjacent thereto, - the first region (11) and the second regions (12) have the same material system, - the material composition of the first region (11) is different from the material composition of the second regions (12), wherein the first region (11) and the second regions (12) have the same thickness, - the first region (11) is strip-shaped in the region of the laser strip, - the second regions (12) are formed in the lateral direction transverse to the direction of extension of the laser strip on both sides next to the first region (11), - the material composition in the first and second regions (11, 12) is selected such that a band gap in the second regions (12) is smaller than a band gap in the first region (11), and - the first semiconductor layer (1) is at least part of an active layer. [2] Semiconductor chip (100) according to the preceding claim, wherein a second region (12) is formed as a facet region adjacent to the facet (11). [3] Semiconductor chip (100) according to one of the preceding claims, wherein the laser stripe has a width which is predetermined by the width of a contact region between a contact layer (4) and the semiconductor layer sequence and / or by a ridge waveguide structure (21) in a second semiconductor layer (2) of the semiconductor layer sequence. [4] Semiconductor chip (100) according to claim 3, wherein the first region (11) has a width corresponding to a width of the laser stripe and / or a width of the ridge waveguide structure. [5] Semiconductor chip (100) according to claim 3, wherein the first region (11) has a width that is greater than a width of the laser stripe and / or a width of the ridge waveguide structure (21). [6] Semiconductor chip (100) according to claim 3, wherein the first region (11) has a width which is smaller than a width of the laser stripe and / or a width of the ridge waveguide structure (21). [7] Semiconductor chip (100) according to one of the preceding claims, wherein the semiconductor chip has a ridge waveguide structure (21). [8] Semiconductor chip (100) according to one of claims 1 to 6, wherein the semiconductor chip does not have a ridge waveguide structure (21). [9] Semiconductor chip (100) according to one of the preceding claims, wherein the semiconductor chip has a plurality of laser stripes and a plurality of strip-shaped first regions (11) separated from one another by second regions (12). [10] Semiconductor chip (100) according to one of the preceding claims, wherein the first semiconductor layer (1) is based on the material system InAlGaN and an In content is varied for lateral variation of the material composition. [11] Semiconductor chip (100) according to one of the preceding claims, wherein the lateral variation of the material composition at least partially has a step-like course. [12] Semiconductor chip (100) according to one of the preceding claims, wherein the lateral variation of the material composition has at least partially a continuous course.

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