Power converter device with a power converter and a control device
The power converter design with strategic switch connections and material selection, along with controlled switching sequences, effectively minimizes electrical switching losses in ANPC converters by optimizing the operation of silicon carbide and silicon semiconductor switches.
Patent Information
- Application Number
- DE102022119531
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2021-08-13
- Filing Date
- 2022-08-04
- Publication Date
- 2025-08-28
- Estimated Expiration
- 2042-08-04
AI Technical Summary
Existing power converters experience high electrical switching losses due to the synchronization of certain power semiconductor switches, particularly in three-phase active neutral point clamped (ANPC) converters with silicon carbide (SiC) elements.
A power converter design with specific connections and control strategies for power semiconductor switches, utilizing silicon carbide or gallium nitride for some switches and silicon for others, along with snubber capacitors to reduce switching losses by controlling the switching sequence and frequency of the switches.
Significantly reduces electrical switching losses by optimizing the switching sequence and material choice of semiconductor switches, enhancing efficiency and reducing undesired high-frequency oscillations.
Smart Images
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Abstract
Description
[0001] The invention relates to a power converter device comprising a power converter having a first, second, third, fourth, fifth and sixth power semiconductor switch, each having a first and a second load current connection, and comprising a control device designed to control the power semiconductor switch, wherein the second load current connection of the first power semiconductor switch is electrically conductively connected to the first load current connection of the fifth power semiconductor switch and to the first load current connection of the second power semiconductor switch, wherein the second load current connection of the fifth power semiconductor switch is electrically conductively connected to the first load current connection of the sixth power semiconductor switch,wherein the second load current terminal of the sixth power semiconductor switch is electrically connected to the first load current terminal of the fourth power semiconductor switch and to the second load current terminal of the third power semiconductor switch, wherein the second load current terminal of the second power semiconductor switch is electrically connected to the first load current terminal of the third power semiconductor switch, wherein the power converter comprises a first diode electrically connected in anti-parallel to the first power semiconductor switch, a second diode electrically connected in anti-parallel to the second power semiconductor switch, a third diode electrically connected in anti-parallel to the third power semiconductor switch, a fourth diode electrically connected in anti-parallel to the fourth power semiconductor switch, a fifth diode electrically connected in anti-parallel to the fifth power semiconductor switch,a sixth diode electrically connected antiparallel to the sixth power semiconductor switch and an alternating potential terminal which is electrically connected at a center circuit node to the second load current terminal of the second power semiconductor switch and to the first load current terminal of the third power semiconductor switch.
[0002] Such a converter device is known from EP 3 301 804 A1. To reduce switching losses, Fig. 14 and the corresponding description of EP 3 301 804 A1, both possible neutral current paths of the converter are used to conduct the output current of the converter. According to Fig. 14 and the associated description of EP 3 301 804 A1, the power semiconductor switches S3 and S5 as well as S2 and S6 switch synchronously with each other, which causes greater switching losses to occur in them.
[0003] CN 1 12 202 353 A describes a doubly fed frequency converter and a modulation method therefor. The doubly fed frequency converter comprises a three-phase bridge arm and a control unit. Each bridge arm comprises a first, a second, a third, a fourth, a fifth, and a sixth switching module. The control unit controls the switching on and off of the first, second, third, fourth, fifth, and sixth switching modules, thus enabling the transition of each phase of the bridge arm into a state with a positive half-wave period, a state with a positive dead band, a state with a positive zero, a state with a zero, a state with a negative zero, a state with a negative dead band, and a state with a negative half-wave period.
[0004] In the published master's thesis M. Troost (2019): "Investigation of different control strategies for three-phase ANPC battery and solar inverters with SiC semiconductor switching elements", Furtwangen University, different control strategies for the operation of three-phase active-neutral-point-clamped (ANPC) medium-voltage grid converters with silicon carbide (SiC) semiconductor switching elements are investigated.
[0005] It is an object of the invention to provide a power converter device with a power semiconductor switch and a control device in which electrical switching losses occurring in the power converter are reduced.
[0006] This object is achieved by a power converter device having a power converter which has a first, second, third, fourth, fifth and sixth power semiconductor switch, each having a first and a second load current connection, and having a control device which is designed to control the power semiconductor switch, wherein the second load current connection of the first power semiconductor switch is electrically conductively connected to the first load current connection of the fifth power semiconductor switch and to the first load current connection of the second power semiconductor switch, wherein the second load current connection of the fifth power semiconductor switch is electrically conductively connected to the first load current connection of the sixth power semiconductor switch,wherein the second load current terminal of the sixth power semiconductor switch is electrically connected to the first load current terminal of the fourth power semiconductor switch and to the second load current terminal of the third power semiconductor switch, wherein the second load current terminal of the second power semiconductor switch is electrically connected to the first load current terminal of the third power semiconductor switch, wherein the power converter comprises a first diode electrically connected in anti-parallel to the first power semiconductor switch, a second diode electrically connected in anti-parallel to the second power semiconductor switch, a third diode electrically connected in anti-parallel to the third power semiconductor switch, a fourth diode electrically connected in anti-parallel to the fourth power semiconductor switch, a fifth diode electrically connected in anti-parallel to the fifth power semiconductor switch,a sixth diode electrically connected anti-parallel to the sixth power semiconductor switch and an alternating potential terminal which is electrically conductively connected at a middle circuit node to the second load current terminal of the second power semiconductor switch and to the first load current terminal of the third power semiconductor switch, wherein during operation of the power converter the middle circuit node has an output voltage with respect to the second load current terminal of the fifth power semiconductor switch and an output current flows in the current counting direction from the middle circuit node to the alternating potential terminal, wherein the control device is designed to control the power semiconductor switches in such a way that, - the first, fifth, sixth and fourth power semiconductor switches are switched on and off at a higher frequency than the second and third power semiconductor switches, - wherein the control device is designed, starting from a first basic power converter switching state in which the output voltage is positive, the output current is negative and the output current flows through the first and second diodes, to transfer the power converter by at least switching on the fifth power semiconductor switch and by subsequently switching on the sixth power semiconductor switch and by subsequently switching on the third power semiconductor switch, into a second basic power converter switching state in which the fifth, sixth and third power semiconductor switches are switched on and a first part of the output current flows through the second diode and through the fifth power semiconductor switch and a second part of the output current flows through the sixth diode and through the third power semiconductor switch. - wherein the control device is designed to transfer the power converter, starting from the second power converter basic switching state, into the first power converter basic switching state by switching off the third power semiconductor switch and subsequently switching off at least the fifth power semiconductor switch.
[0007] It proves advantageous if the control device is designed to transition the power converter, starting from the first basic switching state, into a second basic switching state by at least switching on the fifth power semiconductor switch, by subsequently switching on the sixth power semiconductor switch, and by subsequently switching on the third power semiconductor switch. In this second basic switching state, the fifth, sixth, and third power semiconductor switches are switched on and a first portion of the output current flows through the second diode and through the fifth power semiconductor switch, and a second portion of the output current flows through the sixth diode and through the third power semiconductor switch. This further reduces electrical switching losses occurring in the power converter.
[0008] In this context, it proves advantageous if the control device is designed to transition the power converter, starting from the second basic switching state, to the first basic switching state by switching off the third power semiconductor switch, by subsequently switching off the sixth power semiconductor switch, and by subsequently switching off at least the fifth power semiconductor switch. This further reduces electrical switching losses occurring in the power converter.
[0009] Furthermore, it proves advantageous if the first, fifth, sixth, and fourth power semiconductor switches, due to their design, have lower switching losses than the second and third power semiconductor switches. This further reduces the electrical switching losses occurring in the power converter.
[0010] Furthermore, it proves advantageous if the semiconductor material from which the first, fifth, sixth, and fourth power semiconductor switches are formed is made of silicon carbide or gallium nitride, and the semiconductor material from which the second and third power semiconductor switches are formed is made of silicon. This further reduces electrical switching losses occurring in the power converter.
[0011] Furthermore, it proves advantageous if the semiconductor material from which the first, fifth, sixth, and fourth diodes are formed is made of silicon carbide or gallium nitride, and the semiconductor material from which the second and third diodes are formed is made of silicon. This further reduces electrical switching losses occurring in the power converter.
[0012] Furthermore, it proves advantageous if the first, fifth, sixth, and fourth power semiconductor switches are designed as MOSFETs, and the second and third power semiconductor switches are designed as IGBTs. This further reduces electrical switching losses occurring in the power converter.
[0013] Furthermore, it proves advantageous if the power converter has a first and a second snubber capacitor, wherein a first terminal of the first snubber capacitor is electrically connected to the first load current terminal of the first power semiconductor switch and a second terminal of the first snubber capacitor is electrically connected to the second load current terminal of the fifth power semiconductor switch, wherein a first terminal of the second snubber capacitor is electrically connected to the first load current terminal of the sixth power semiconductor switch and a second terminal of the second snubber capacitor is electrically connected to the second load current terminal of the fourth power semiconductor switch. This makes it possible to reduce unwanted high-frequency electrical oscillations and / or overvoltages occurring during operation of the power converter.
[0014] Furthermore, this object is achieved by a power converter device having a power converter which has a first, second, third, fourth, fifth and sixth power semiconductor switch, each having a first and a second load current connection, and having a control device which is designed to control the power semiconductor switches, wherein the second load current connection of the first power semiconductor switch is electrically connected to the first load current connection of the fifth power semiconductor switch and to the first load current connection of the second power semiconductor switch, wherein the second load current connection of the fifth power semiconductor switch is electrically connected to the first load current connection of the sixth power semiconductor switch,wherein the second load current terminal of the sixth power semiconductor switch is electrically connected to the first load current terminal of the fourth power semiconductor switch and to the second load current terminal of the third power semiconductor switch, wherein the second load current terminal of the second power semiconductor switch is electrically connected to the first load current terminal of the third power semiconductor switch, wherein the power converter comprises a first diode electrically connected in anti-parallel to the first power semiconductor switch, a second diode electrically connected in anti-parallel to the second power semiconductor switch, a third diode electrically connected in anti-parallel to the third power semiconductor switch, a fourth diode electrically connected in anti-parallel to the fourth power semiconductor switch, a fifth diode electrically connected in anti-parallel to the fifth power semiconductor switch,a sixth diode electrically connected in anti-parallel to the sixth power semiconductor switch and an alternating potential terminal which is electrically conductively connected at a middle circuit node to the second load current terminal of the second power semiconductor switch and to the first load current terminal of the third power semiconductor switch, wherein, during operation of the power converter, the middle circuit node has an output voltage with respect to the second load current terminal of the fifth power semiconductor switch and an output current flows in the current counting direction from the middle circuit node to the alternating potential terminal, wherein the control device is designed to control the power semiconductor switches such that - the second and third power semiconductor switches are switched on and off at a higher frequency than the first, fifth, sixth and fourth power semiconductor switches, - wherein the control device is designed, starting from a first basic power converter switching state in which the output voltage is positive, the output current is negative and the output current flows through the first and second diodes, to transfer the power converter by at least switching on the third power semiconductor switch and by subsequently switching on the second power switch and by subsequently switching on the fifth power semiconductor switch at a later time, into a second basic power converter switching state in which the second, fifth and third power semiconductor switches are switched on and a first part of the output current flows through the second diode and through the fifth power semiconductor switch and a second part of the output current flows through the sixth diode and through the third power semiconductor switch. - wherein the control device is designed to transfer the power converter, starting from the second power converter basic switching state, into the first power converter basic switching state by switching off the fifth power semiconductor switch and by at least temporally subsequently switching off the third power semiconductor switch.
[0015] It proves advantageous if the control device is designed, starting from the first power converter basic switching state, to transfer the power converter into a second power converter basic switching state by at least switching on the third power semiconductor switch, by subsequently switching on the second power semiconductor switch, and by subsequently switching on the fifth power semiconductor switch. In this second power converter basic switching state, the second, fifth, and third power semiconductor switches are switched on, and a first portion of the output current flows through the second diode and through the fifth power semiconductor switch, and a second portion of the output current flows through the sixth diode and through the third power semiconductor switch. This further reduces electrical switching losses occurring in the power converter.
[0016] In this context, it proves advantageous if the control device is designed to transition the power converter, starting from the second basic switching state, to the first basic switching state by switching off the fifth power semiconductor switch, by subsequently switching off the second power semiconductor switch, and by at least subsequently switching off the third power semiconductor switch. This further reduces electrical switching losses occurring in the power converter.
[0017] Furthermore, it proves advantageous if the second and third power semiconductor switches have lower switching losses than the first, fifth, sixth, and fourth power semiconductor switches. This further reduces electrical switching losses occurring in the power converter.
[0018] Furthermore, it proves advantageous if the semiconductor material from which the second and third power semiconductor switches are formed is made of silicon carbide or gallium nitride, and the semiconductor material from which the first, fifth, sixth, and fourth power semiconductor switches are formed is made of silicon. This further reduces electrical switching losses occurring in the power converter.
[0019] Furthermore, it proves advantageous if the semiconductor material from which the second and third diodes are formed is made of silicon carbide or gallium nitride, and the semiconductor material from which the first, fifth, sixth, and fourth diodes are formed is made of silicon. This further reduces electrical switching losses occurring in the power converter.
[0020] Furthermore, it proves advantageous if the first, fifth, sixth, and fourth power semiconductor switches are designed as IGBTs, and the second and third power semiconductor switches are designed as MOSFETs. This further reduces electrical switching losses occurring in the power converter.
[0021] The respective first, second, third, fourth, fifth, and sixth diodes can, as in the exemplary embodiments, be designed as discrete components or can be integrated into the semiconductor body of the respective power semiconductor switch connected in antiparallel to the respective diode. If the respective power semiconductor switch is designed, for example, as a MOSFET, the respective diode can thus also be designed as an intrinsic diode of the MOSFET.
[0022] It should be noted that the semiconductor material from which the first, second, third, fourth, fifth and sixth power semiconductor switches are formed may be formed, for example, from silicon, silicon carbide or gallium nitride and that the semiconductor material from which the first, second, third, fourth, fifth and sixth diodes are formed may be formed, for example, from silicon, silicon carbide or gallium nitride.
[0023] It should also be noted that snubber capacitors, in contrast to DC link capacitors, which serve to temporarily store energy, serve to reduce unwanted high-frequency electrical oscillations and / or overvoltages and generally have a much lower capacitance than DC link capacitors.
[0024] Embodiments of the invention are explained below with reference to the figures below. Fig. 1 a power converter device according to the invention with a power converter and a control device, Fig. 2 curves of an output voltage and an output current of a power converter of a power converter device according to the invention, Fig. 3 a switching state of the power converter according to Fig. 1, Fig. 4 another switching state of the power converter according to Fig. 1, Fig. 5 another switching state of the power converter according to Fig. 1, Fig. 6 another switching state of the power converter according to Fig. 1, Fig. 7 another switching state of the power converter according to Fig. 1, Fig. 8 another switching state of the power converter according to Fig. 1, Fig. 9 shows a further converter device according to the invention with a converter and a control device, Fig. 10 a switching state of the power converter according to Fig. 9, Fig. 11 another switching state of the power converter according to Fig. 9, Fig. 12 another switching state of the power converter according to Fig. 9, Fig. 13 another switching state of the power converter according to Fig. 9, Fig. 14 another switching state of the power converter according to Fig. 9, Fig. 15 another switching state of the power converter according to Fig. 9, Fig. 16 another switching state of the power converter according to Fig. 9 and Fig. 17 another switching state of the power converter according to Fig. 9.
[0025] In Fig. 1 shows a power converter device 1 according to the invention with a power converter 2 and with a control device 3.
[0026] The power converter 2 has first, second, third, fourth, fifth, and sixth power semiconductor switches T1, T2, T3, T4, T5, and T6, each having a first and a second load current terminal L1 and L2. The second load current terminal L2 of the first power semiconductor switch T1 is electrically connected to the first load current terminal L1 of the fifth power semiconductor switch T5 and to the first load current terminal L1 of the second power semiconductor switch T2. The second load current terminal L2 of the fifth power semiconductor switch T5 is electrically connected to the first load current terminal L1 of the sixth power semiconductor switch T6. The second load current terminal L2 of the sixth power semiconductor switch T6 is electrically connected to the first load current terminal L1 of the fourth power semiconductor switch T4 and to the second load current terminal L2 of the third power semiconductor switch T3.The second load current terminal L2 of the second power semiconductor switch T2 is electrically connected to the first load current terminal L1 of the third power semiconductor switch T3.
[0027] The power converter 2 further comprises a first diode D1 electrically connected in anti-parallel to the first power semiconductor switch T1, a second diode D2 electrically connected in anti-parallel to the second power semiconductor switch T2, a third diode D3 electrically connected in anti-parallel to the third power semiconductor switch T3, a fourth diode D4 electrically connected in anti-parallel to the fourth power semiconductor switch T4, a fifth diode D5 electrically connected in anti-parallel to the fifth power semiconductor switch T5, a sixth diode D6 electrically connected in anti-parallel to the sixth power semiconductor switch T6 and an alternating potential terminal AC which is electrically conductively connected at a center circuit node M1 to the second load current terminal L2 of the second power semiconductor switch T2 and to the first load current terminal L1 of the third power semiconductor switch T3.
[0028] During operation of the power converter 2, the center circuit node M1 has an output voltage Ua with respect to the second load current terminal L2 of the fifth power semiconductor switch T5, and an output current Ia flows in the current counting direction from the center circuit node M1 to the alternating potential terminal AC.
[0029] The power converter 2 further comprises a positive potential terminal DC+, which is electrically connected to the first load current terminal L1 of the first power semiconductor switch T1, a negative potential terminal DC-, which is electrically connected to the second load current terminal L2 of the fourth power semiconductor switch T4, and a neutral potential terminal N, which is electrically connected at a further center circuit node M2 to the second load current terminal L2 of the fifth power semiconductor switch T5 and to the first load current terminal L1 of the sixth power semiconductor switch T6. The power converter 2 thus has an ANPC circuit topology.
[0030] During operation of the power converter 2, a first DC voltage Udc1 is present between the positive potential connection DC+ or the first load current connection L1 of the first power semiconductor switch T1 and the neutral potential connection N or the second load current connection L2 of the fifth power semiconductor switch T5, and a second DC voltage Udc2 is present between the neutral potential connection N or the first load current connection L1 of the sixth power semiconductor switch T6 and the second load current connection L2 of the fourth power semiconductor switch T4. By switching the power semiconductor switches T1, T2, T3, T4, T5, and T6 on and off accordingly, the AC potential connection AC can be electrically connected to the first or second DC voltage connection DC+ or DC- or to the neutral potential connection N.
[0031] The first, fifth, sixth and fourth power semiconductor switches T1, T5, T6 and T4 preferably have smaller switching losses than the second and third power semiconductor switches T2 and T3 due to their design.
[0032] The semiconductor material from which the first, fifth, sixth and fourth power semiconductor switches T1, T5, T6 and T4 are formed is preferably formed from silicon carbide or gallium nitride and the semiconductor material from which the second and third power semiconductor switches T2 and T3 are formed is preferably formed from silicon.
[0033] The semiconductor material from which the first, fifth, sixth and fourth diodes D1, D5, D6 and D4 are formed is preferably formed of silicon carbide or gallium nitride and the semiconductor material from which the second and third diodes D2 and D3 are formed is preferably formed of silicon.
[0034] The first, fifth, sixth and fourth power semiconductor switches T1, T5, T6 and T4 are preferably designed as MOSFETs and the second and third power semiconductor switches T2 and T3 are preferably designed as IGBTs.
[0035] In the embodiments, the respective T1, T2, T3, T4, T5 and T6 is designed as an IGBT, wherein the respective first load current terminal L1 is designed as a collector terminal and the respective second load current terminal L2 is designed as an emitter terminal and the respective control terminal G1, G2, G3, G4, G5 and G6 is designed as a gate terminal.
[0036] The power converter 2 preferably has a first and a second snubber capacitor C1 and C2. A first terminal of the first snubber capacitor C1 is electrically connected to the first load current terminal L1 of the first power semiconductor switch T1, and a second terminal of the first snubber capacitor C1 is electrically connected to the second load current terminal L2 of the fifth power semiconductor switch T5. A first terminal of the second snubber capacitor C2 is electrically connected to the first load current terminal L1 of the sixth power semiconductor switch T6, and a second terminal of the second snubber capacitor C2 is electrically connected to the second load current terminal L2 of the fourth power semiconductor switch T4.
[0037] The control device 3 is designed to control the power semiconductor switches T1, T2, T3, T4, T5, and T6. For this purpose, the control device 3 has outputs that are electrically connected to control terminals G1, G2, G3, G4, G5, and G6 of the power semiconductor switches T1, T2, T3, T4, T5, and T6. The control device 3 generates control signals for controlling the power semiconductor switches T1, T2, T3, T4, T5, and T6, or more precisely, for switching the power semiconductor switches T1, T2, T3, T4, T5, and T6 on and off.
[0038] The control device 3 is designed to control the power semiconductor switches T1, T2, T3, T4, T5 and T6 in such a way that - the first, fifth, sixth and fourth power semiconductor switches T1, T5, T6, T4 are switched on and off at a higher frequency than the second and third power semiconductor switches T2 and T3.
[0039] In Fig. 2, the time profiles of the output voltage Ua and the output current la occurring within the scope of the exemplary embodiments are shown over a period of the idealized sinusoidal output current la, where the time is denoted by t, the voltage by U, and the current by I. An inductive load, such as an electric motor, is connected to the alternating potential terminal AC. The power semiconductor switches T1, T2, T3, T4, T5, and T6 are controlled by the control device 3 and 3', respectively (see Fig. 1 and Fig. 9) is controlled by pulse-width modulation. This results in four squares Q1, Q2, Q3, and Q4, whose dash-dotted boundaries lie at the two current zero crossings and at the current maximum and minimum of the output current Ia.
[0040] In the Fig. 3 to 8 and 10 to 17 show the switching states of the power semiconductor switches T1, T2, T3, T4, T5 and T6 which occur in the first quadrant Q1, wherein the circuit symbols of the power semiconductor switches T1, T2, T3, T4, T5 and T6 which are switched on in the respective switching state are shown with thick lines and the power semiconductor switches T1, T2, T3, T4, T5 and T6 which are optionally switched on in the respective switching state are shown with circles. The circuit symbol of a power semiconductor switch which is additionally switched on in the respective switching state as part of an advantageous embodiment of the invention is also shown with thick lines. Furthermore, the power supplied by the power converter 2 or2', the through-passage curve 4 of the output current la is shown. When the through-passage curve 4 intersects the thick circuit symbol of the currently switched-on power semiconductor switch, the output current la flows through this power semiconductor switch. When the through-passage curve 4 is shown passing between the reference symbol of the diode and the circuit symbol of the diode, the output current la flows through this diode. The output current la flows in the first quadrant Q1 in the opposite direction to the current counting direction, so that the output current la is negative.
[0041] The Fig. The switching state shown in Figure 3 is a first basic converter switching state, which is present in the first square Q1 in the time periods S1 (output voltage Ua has a high positive value) and which is Fig. The switching state shown in Figure 6 is a second basic converter switching state, which is present in the first quadrature Q1 in the time periods S2 (output voltage Ua has an idealized value of zero or approximately zero). Fig. 4 and Fig. The switching states shown in Figure 5 are transition states that occur during the transition from the first to the second basic converter switching state. Fig. 7 and Fig. The switching states shown in Figure 8 are transitional switching states that occur during the transition from the second to the first basic converter switching state. The durations of the basic converter switching states are generally much longer than the durations of the transitional switching states, so that the durations of the transitional switching states in Fig. 2 are not shown.
[0042] The control device 3 is designed to, starting from a first basic converter switching state (see switching state according to Fig. 3) in which the output voltage (Ua) is positive, the output current la is negative and the output current la flows through the first and second diode, the power converter 2 by at least switching on the fifth power semiconductor switch T5 (the switching state results according to Fig. 4) and subsequent switching on of the third power semiconductor switch T3 into a second converter basic switching state (see switching state according to Fig. 6), in which the fifth and third power semiconductor switches T5 and T3 are switched on and a first part (4') of the output current Ia flows through the second diode D2 and through the fifth power semiconductor switch T5 and a second part 4" of the output current Ia flows through the sixth diode D6 and through the third power semiconductor switch T3.
[0043] In the first basic converter switching state, the first and second power semiconductor switches T1 and T2 can optionally be switched on. In this case, the first power semiconductor switch T1 is also switched off immediately before the fifth power semiconductor switch T5 is switched on.
[0044] In contrast to EP 3 301 804 A1, in which the third and fifth power semiconductor switches S3 and S5 switch synchronously and are thus switched on simultaneously, in the invention the fifth power semiconductor switch T5 is switched on first by the control device 3 and only then the third power semiconductor switch T3. For this purpose, the control device 3 generates the control signal for the control terminal G3 for switching on the third power semiconductor switch T3 after the control signal for the control terminal G5 for switching on the fifth power semiconductor switch T5. This reduces the switching losses occurring during the transition from the first to the second basic converter switching state.
[0045] Switching losses occurring during the transition from the first to the second converter basic switching state can be further reduced by the control device 3 being designed to, starting from the first converter basic switching state (see Fig. 3) the power converter 2 by at least switching on the fifth power semiconductor switch T5 (the switching state results according to Fig. 4), by subsequently switching on the sixth power semiconductor switch (T6) (the switching state results according to Fig. 5) and by subsequently switching on the third power semiconductor switch (T3) into a second converter basic switching state (see Fig. 6), in which the fifth, sixth and third power semiconductor switches T5, T6, T3 are switched on and a first part 4' of the output current Ia flows through the second diode D2 and through the fifth power semiconductor switch T5 and a second part 4" of the output current Ia flows through the sixth diode D6 and through the third power semiconductor switch T3.
[0046] In this advantageous embodiment of the invention, after the fifth power semiconductor switch T5 has been switched on, the sixth power semiconductor switch T6 is switched on, and then the third power semiconductor switch T3 is switched on. The switching on of the sixth power semiconductor switch T6 occurs with virtually no switching losses, since no current flows through the sixth power semiconductor switch T6 other than the small and brief charging current that flows through the sixth power semiconductor switch T6 when charging the junction capacitance of the fourth power semiconductor switch T4. After the sixth power semiconductor switch T6 has been switched on, only a small voltage is present across the third power semiconductor switch T3, so that the subsequent switching on of the third power semiconductor switch T3 also occurs with virtually no switching losses.
[0047] The control device 3 is further designed to, starting from the second converter basic switching state (see Fig. 6), the power converter 2 by switching off the third power semiconductor switch T3 (the switching state results according to Fig. 7), by subsequently switching off the sixth power semiconductor switch T6 (the switching state results according to Fig. 8) and by subsequently switching off at least the fifth power semiconductor switch T5 into the first basic converter switching state (see Fig. 3). If the first power semiconductor switch T1 is switched on in the first basic converter switching state, the first power semiconductor switch T1 is additionally switched on by the control device 3 immediately after the fifth power semiconductor switch T5 is switched off.
[0048] In contrast to EP 3 301 804 A1, in which the third and fifth power semiconductor switches S3 and S5 switch synchronously and are thus switched off simultaneously, in the invention the third power semiconductor switch T3 is switched off first by the control device 3 and then the fifth power semiconductor switch T5. For this purpose, the control device 3 generates the control signal for the control terminal G3 for switching off the third power semiconductor switch T3 before the control signal for the control terminal G5 for switching off the fifth power semiconductor switch T5. This reduces switching losses occurring during the transition from the second to the first basic converter switching state.
[0049] Switching losses occurring during the transition from the second to the first converter basic switching state can be reduced even further if the sixth power semiconductor switch T6 was switched on as described above during the transition from the first to the second converter basic switching state, in that the control device 3 is designed to, starting from the second converter basic switching state (see Fig. 6), the power converter 2 by switching off the third power semiconductor switch T3 (the switching state results according to Fig. 7), by subsequently switching off the sixth power semiconductor switch T6 (the switching state results according to Fig. 8) and by switching off the fifth power semiconductor switch T5 at least in time to the first basic converter switching state (see Fig. 3) to be transferred.
[0050] In this advantageous embodiment of the invention, after the third power semiconductor switch T3 has been switched off, the sixth power semiconductor switch T6 is switched off and then the fifth power semiconductor switch T5 is switched off. The third power semiconductor switch T3 is switched off with almost no switching losses because almost no voltage is present across the third power semiconductor switch T3 when it is switched off. The sixth power semiconductor switch T6 is switched off with almost no switching losses because no current flows through the sixth power semiconductor switch T6 when it is switched off. Furthermore, the sixth diode D6 switches off with almost no electrical losses because the sixth power semiconductor switch T6 keeps the voltage across the sixth diode D6 almost at zero, while the third power semiconductor switch T3 switches off the current flowing through the sixth diode D6.
[0051] The switching operations in the remaining quadrants, ie in the second, third and fourth quadrants Q2, Q3 and Q4 from the respective first converter basic switching state to the respective second converter basic switching state and back, are carried out in an analogous manner as described above with regard to the first quadrant Q1, so that in the following the respective switching operations according to the invention for the second, third and fourth quadrants Q2, Q3 and Q4 are described only in abbreviated form and without figures.
[0052] The control device 3 is also designed with respect to the second, third and fourth quadrants Q2, Q3 and Q4 to control the power semiconductor switches T1, T2, T3, T4, T5 and T6 in such a way that - the first, fifth, sixth and fourth power semiconductor switches T1, T5, T6, T4 are switched on and off at a higher frequency than the second and third power semiconductor switches T2 and T3.
[0053] The control device 3 is designed to transfer the power converter 2, starting from a first basic switching state in which the output voltage Ua is positive, the output current la is positive, the first and second power semiconductor switches T1 and T2 are switched on and the output current la flows through the first and second power semiconductor switches T1 and T2, into a second basic switching state in which the second and sixth power semiconductor switches T2 and T6 are switched on and a first part of the output current la flows through the fifth diode D5 and through the second power semiconductor switch T2 and a second part of the output current la flows through the third diode D3 and through the sixth power semiconductor switch T6.Preferably, in order to reduce the switching losses in the sixth power semiconductor switch T6, after the first power semiconductor switch T1 is switched off, the third power semiconductor switch T3 is switched on before the sixth power semiconductor switch T6 is switched on. Optionally, the fifth power semiconductor switch T5 can also be switched on immediately after the first power semiconductor switch T1 is switched off. The control device 3 is further designed to transfer the power converter 2, starting from the second power converter basic switching state, into the first power converter basic switching state by switching off the sixth power semiconductor switch T6 and subsequently at least switching on the first power semiconductor switch T1. If the fifth power semiconductor switch T5 is switched on, it is switched off immediately before the first power semiconductor switch T1 is switched on.If the third power semiconductor switch T3 has been switched on during the transition from the first power converter basic switching state to the second power converter basic switching state, as described above, in order to reduce switching losses, the third power semiconductor switch T3 is preferably switched off after the sixth power semiconductor switch T6 has been switched off and before the first power semiconductor switch T1 has been switched on and in particular before the fifth power semiconductor switch T5 has been switched off.
[0054] The design of the control device 3 and the switching states for the third quadrant Q3, in which the output voltage Ua is negative and the output current Ia is positive, correspond in a mirror image and analogously to the design of the control device 3 and the switching states for the first quadrant Q1, in which the output voltage Ua is positive and the output current Ia is negative. In the description given above regarding the design of the control device 3 and the switching states for the first quadrant Q1, only the first power semiconductor switch T1 and the first diode D1 are to be replaced by the fourth power semiconductor switch T4 and the fourth diode D4, the fifth power semiconductor switch T5 and the fifth diode D5 are to be replaced by the sixth power semiconductor switch T6 and the sixth diode D6, and the second power semiconductor switch T2 and the second diode D2 are to be replaced by the third power semiconductor switch T3 and the third diode D3.With regard to the description of the design of the control device 3 and the switching states for the third quadrant Q3, reference is made to the description of the design of the control device 3 and the switching states for the first quadrant Q1 in order to avoid analogous duplicate descriptions.
[0055] The design of the control device 3 and the switching states for the fourth quadrant Q4, in which the output voltage Ua is negative and the output current Ia is negative, correspond in a mirror image and analogously to the design of the control device 3 and the switching states for the second quadrant Q2, in which the output voltage Ua is positive and the output current Ia is positive. In the description given above regarding the design of the control device 3 and the switching states for the second quadrant Q2, only the first power semiconductor switch T1 and the first diode D1 are to be replaced by the fourth power semiconductor switch T4 and the fourth diode D4, the fifth power semiconductor switch T5 and the fifth diode D5 are to be replaced by the sixth power semiconductor switch T6 and the sixth diode D6, and the second power semiconductor switch T2 and the second diode D2 are to be replaced by the third power semiconductor switch T3 and the third diode D3.With regard to the description of the design of the control device 3 and the switching states for the fourth quadrant Q4, reference is made to the description of the design of the control device 3 and the switching states for the second quadrant Q2 in order to avoid analogous duplicate descriptions.
[0056] In Fig. 9 shows a further power converter device 1' according to the invention with a power converter 2' and with a control device 3'.
[0057] The circuit topology of the power converter 2' according to Fig. 9 corresponds to the circuit topology of the power converter 2 according to Fig. 1 except for the feature of the two snubber capacitors C1 and C2 which is preferably present in the power converter 2, so that with regard to the circuit topology of the power converter 2', reference is made to the description of the circuit topology of the power converter 2.
[0058] During operation of the power converter 2', a first DC voltage Udc1 is present between the positive potential connection DC+ or the first load current connection L1 of the first power semiconductor switch T1 and the neutral potential connection N or the second load current connection L2 of the fifth power semiconductor switch T5, and a second DC voltage Udc2 is present between the neutral potential connection N or the first load current connection L1 of the sixth power semiconductor switch T6 and the second load current connection L2 of the fourth power semiconductor switch T4. By switching the power semiconductor switches T1, T2, T3, T4, T5, and T6 on and off accordingly, the AC potential connection AC can be electrically connected to the first or second DC voltage connection DC+ or DC- or to the neutral potential connection N.
[0059] The second and third power semiconductor switches T2 and T3 preferably have smaller switching losses than the first, fifth, sixth and fourth power semiconductor switches T1, T5, T6, and T4.
[0060] The semiconductor material from which the second and third power semiconductor switches T2 and T3 are formed is preferably formed from silicon carbide or gallium nitride and the semiconductor material from which the first, fifth, sixth and fourth power semiconductor switches T1, T5, T6 and T4 are formed is preferably formed from silicon.
[0061] The semiconductor material from which the second and third diodes D2 and D3 are formed is preferably formed of silicon carbide or gallium nitride and the semiconductor material from which the first, fifth, sixth and fourth diodes D1, D5, D6 and D4 are formed is preferably formed of silicon.
[0062] The first, fifth, sixth and fourth power semiconductor switches T1, T5, T6 and T4 are preferably designed as IGBTs and the second and third power semiconductor switches T2 and T3 are preferably designed as MOSFETs.
[0063] In the exemplary embodiment, the respective T1, T2, T3, T4, T5 or T6 is designed as an IGBT, wherein the respective first load current connection L1 is designed as a collector connection and the respective second load current connection L2 is designed as an emitter connection.
[0064] The control device 3' is designed to control the power semiconductor switches T1, T2, T3, T4, T5, and T6. For this purpose, the control device 3' has outputs that are electrically connected to control terminals G1, G2, G3, G4, G5, and G6 of the power semiconductor switches T1, T2, T3, T4, T5, and T6, which are designed here as gate terminals. The control device 3' generates control signals for controlling the power semiconductor switches T1, T2, T3, T4, T5, and T6, or more precisely, for switching the power semiconductor switches T1, T2, T3, T4, T5, and T6 on and off.
[0065] In contrast to the control device 3, the control device 3' is designed to control the power semiconductor switches T1, T2, T3, T4, T5 and T6 such that the second and third power semiconductor switches T2 and T3 are switched on and off at a higher frequency than the first, fifth, sixth and fourth power semiconductor switches T1, T5, T6 and T4.
[0066] The Fig. 10 is a first basic converter switching state, which is present in the first square Q1 in the time periods S1 (output voltage Ua has a high positive value) and which is present in Fig. The switching state shown in Figure 14 is a second basic converter switching state, which is present in the first quadrature Q1 in the time periods S2 (output voltage Ua has an idealized value of zero or approximately zero). Fig. 11, Fig. 12 and Fig. 13 are transition states that occur during the transition from the first to the second basic converter switching state. Fig. 15, Fig. 16 and Fig. The switching states shown in Figure 17 are transitional switching states that occur during the transition from the second to the first basic converter switching state. The durations of the basic converter switching states are generally much longer than the durations of the transitional switching states, so that the durations of the transitional switching states in Fig. 2 are not shown.
[0067] The control device 3' is designed to, starting from a first basic converter switching state (see switching state according to Fig. 10) in which the output voltage Ua is positive, the output current la is negative and the output current la flows through the first and second diodes D1 and D2, the power converter 2' by at least switching on the third power semiconductor switch T3 and subsequently switching on the fifth power semiconductor switch T5 into a second power converter basic switching state (see switching state according to Fig. 14), in which the fifth and third power semiconductor switches T5 and T3 are switched on and a first part 4' of the output current Ia flows through the second diode D2 and through the fifth power semiconductor switch T5 and a second part 4" of the output current Ia flows through the sixth diode D6 and through the third power semiconductor switch T3.
[0068] In the first basic converter switching state, the first, second, and sixth power semiconductor switches T1, T2, and T6 can optionally be switched on. In this case, the second power semiconductor switch T2 is also switched off immediately before the third power semiconductor switch T3 is switched on. Furthermore, in this case, the first power semiconductor switch T1 is preferably switched off immediately after the third power semiconductor switch T3 is switched on (see transition from the switching state according to Fig. 11 into the switching state according to Fig. 12).
[0069] In contrast to EP 3 301 804 A1, in which the third and fifth power semiconductor switches S3 and S5 switch synchronously and are thus switched on simultaneously, in the invention, the third power semiconductor switch T3 is switched on first by the control device 3' and only then the fifth power semiconductor switch T5. For this purpose, the control device 3' generates the control signal for the control terminal G3 for switching on the third power semiconductor switch T3 before the control signal for the control terminal G5 for switching on the fifth power semiconductor switch T5. This reduces switching losses occurring during the transition from the first to the second basic converter switching state.
[0070] Switching losses occurring during the transition from the first to the second converter basic switching state can be further reduced by the control device 3' being designed to, starting from the first converter basic switching state (see switching state according to Fig. 10), the power converter 2' by at least switching on the third power semiconductor switch T3 (the switching state results according to Fig. 12), by subsequently switching on the second power semiconductor switch T2 (the switching state results according to Fig. 13) and by subsequently switching on the fifth power semiconductor switch T5 into a second converter basic switching state (see switching state according to Fig. 14), in which the second, fifth and third power semiconductor switches T2, T5 and T3 are switched on and a first part 4' of the output current Ia flows through the second diode D2 and through the fifth power semiconductor switch T5 and a second part 4" of the output current Ia flows through the sixth diode D6 and through the third power semiconductor switch T3.
[0071] In this advantageous embodiment of the invention, after the third power semiconductor switch T3 has been switched on, the second power semiconductor switch T2 is switched on, and then the fifth power semiconductor switch T5 is switched on. The second power semiconductor switch T2 is switched on with virtually no switching losses, since no current flows through the second power semiconductor switch T2 other than the small and brief charging current that flows through the second power semiconductor switch T2 when charging the junction capacitance of the first power semiconductor switch T1. After the second power semiconductor switch T2 has been switched on, only a small voltage is present across the fifth power semiconductor switch T5, so that the subsequent switching on of the fifth power semiconductor switch T5 also occurs with virtually no switching losses.
[0072] The control device 3 is further designed to, starting from the second converter basic switching state (see Fig. 14), the power converter 2' by switching off the fifth power semiconductor switch T5 (the switching state results according to Fig. 16) and by at least temporally subsequent switching off of the third power semiconductor switch T3 into the first converter basic switching state (see Fig. 10). If in the first basic converter switching state the first power semiconductor switch T1 and the second power semiconductor switch T2 are switched on, the first power semiconductor switch T1 is additionally switched on by the control device 3, preferably immediately after the fifth power semiconductor switch T5 is switched off (the switching state according to Fig. 17) and immediately after the third power semiconductor switch T3 is switched off, the second power semiconductor switch T2 is switched on (see Fig. 10).
[0073] In contrast to EP 3 301 804 A1, in which the third and fifth power semiconductor switches S3 and S5 switch synchronously and are thus switched off simultaneously, in the invention the fifth power semiconductor switch T5 is switched off first by the control device 3 and then the third power semiconductor switch T3. For this purpose, the control device 3 generates the control signal for the control terminal G5 for switching off the fifth power semiconductor switch T5 before the control signal for the control terminal G3 for switching off the third power semiconductor switch T3. This reduces switching losses occurring during the transition from the second to the first basic converter switching state.
[0074] Switching losses occurring during the transition from the second to the first converter basic switching state can be reduced even further if the second power semiconductor switch T2 was switched on as described above during the transition from the first to the second converter basic switching state, in that the control device 3' is designed to, starting from the second converter basic switching state (see Fig. 14), the power converter 2' by switching off the fifth power semiconductor switch T5 (the switching state results according to Fig. 15), by subsequently switching off the second power semiconductor switch T2 (the switching state results according to Fig. 16) and by at least subsequently switching off the third power semiconductor switch T3 into the first converter basic switching state (see Fig. 10).
[0075] In this advantageous embodiment of the invention, after the fifth power semiconductor switch T5 has been switched off, the second power semiconductor switch T2 is switched off, and then the third power semiconductor switch T3 is switched off. The fifth power semiconductor switch T5 is switched off with virtually no switching losses, since virtually no voltage is present across the fifth power semiconductor switch T5 when it is switched off. The second power semiconductor switch T2 is switched off with virtually no switching losses, since no current flows through the second power semiconductor switch T2 when it is switched off.
[0076] The switching operations for the remaining quadrants, ie for the second, third and fourth quadrants Q2, Q3 and Q4 from the respective first converter basic switching state to the respective second converter basic switching state and back, are carried out in an analogous manner as described above with regard to the first quadrant Q1, so that in the following the respective switching operations according to the invention for the second, third and fourth quadrants Q2, Q3 and Q4 are described only in abbreviated form and without figures.
[0077] The control device 3' is also designed with respect to the second, third and fourth quadrants Q2, Q3 and Q4 to control the power semiconductor switches T1, T2, T3, T4, T5 and T6 such that the second and third power semiconductor switches T2 and T3 are switched on and off at a higher frequency than the first, fifth, sixth and fourth power semiconductor switches T1, T5, T6 and T4.
[0078] The control device 3' is designed, starting from a first basic converter switching state in which the output voltage Ua is positive, the output current Ia is positive, the first and second and sixth power semiconductor switches T1, T2 and T6 are switched on and the output current Ia flows through the first and second power semiconductor switches T1 and T2, to transfer the power converter 2' by switching off the first and second power semiconductor switches T1 and T2 and subsequently switching on the second power semiconductor switch T2 into a second basic converter switching state in which the second and sixth power semiconductor switches T2 and T6 are switched on and a first part of the output current Ia flows through the fifth diode D5 and through the second power semiconductor switch T2 and a second part of the output current Ia flows through the third diode D3 and through the sixth power semiconductor switch T6.Preferably, immediately after the second power semiconductor switch T2 is switched off, the third power semiconductor switch T3 is switched on, and subsequently the first power semiconductor switch T1 is switched off. Preferably, in order to reduce the switching losses in the second power semiconductor switch T2, the fifth power semiconductor switch T5 is switched on before the second power semiconductor switch T2 is switched on. The control device 3' is further designed to transfer the power converter 2', starting from the second power converter basic switching state, into the first power converter basic switching state by switching off the second power semiconductor switch T2 and subsequently switching on at least the first and second power semiconductor switches T1 and T2. If the third power semiconductor switch T3 is switched on, it is switched off immediately before the second power semiconductor switch T2 is switched on.
[0079] If the fifth power semiconductor switch T5 has been switched on during the transition from the first power converter basic switching state to the second power converter basic switching state as described above, the fifth power semiconductor switch T5 is switched off immediately after the second power semiconductor switch T2 is switched off in order to reduce switching losses.
[0080] The design of the control device 3' and the switching states for the third quadrant Q3, in which the output voltage Ua is negative and the output current Ia is positive, correspond in a mirror image and analogously to the design of the control device 3' and the switching states for the first quadrant Q1, in which the output voltage Ua is positive and the output current Ia is negative. In the description given above regarding the design of the control device 3 and the switching states for the first quadrant Q1, only the first power semiconductor switch T1 and the first diode D1 are to be replaced by the fourth power semiconductor switch T4 and the fourth diode D4, the fifth power semiconductor switch T5 and the fifth diode D5 are to be replaced by the sixth power semiconductor switch T6 and the sixth diode D6, and the second power semiconductor switch T2 and the second diode D2 are to be replaced by the third power semiconductor switch T3 and the third diode D3.With regard to the description of the design of the control device 3' and the switching states for the third quadrant Q3, reference is made to the description of the design of the control device 3' and the switching states for the first quadrant Q1 in order to avoid analogous duplicate descriptions.
[0081] The design of the control device 3' and the switching states for the fourth quadrant Q4, in which the output voltage Ua is negative and the output current Ia is negative, correspond in a mirror image and analogously to the design of the control device 3' and the switching states for the second quadrant Q2, in which the output voltage Ua is positive and the output current Ia is positive. In the description given above regarding the design of the control device 3' and the switching states for the second quadrant Q2, only the first power semiconductor switch T1 and the first diode D1 are to be replaced by the fourth power semiconductor switch T4 and the fourth diode D4, the fifth power semiconductor switch T5 and the fifth diode D5 are to be replaced by the sixth power semiconductor switch T6 and the sixth diode D6, and the second power semiconductor switch T2 and the second diode D2 are to be replaced by the third power semiconductor switch T3 and the third diode D3.With regard to the description of the design of the control device 3' and the switching states for the fourth quadrant Q4, reference is made to the description of the design of the control device 3' and the switching states for the second quadrant Q2 in order to avoid analogous duplicate descriptions.
Claims
[1] Power converter device with a power converter (2) having a first, second, third, fourth, fifth and sixth power semiconductor switch (T1, T2, T3, T4, T5, T6), each having a first and a second load current connection (L1, L2), and with a control device (3) designed to control the power semiconductor switches (T1, T2, T3, T4, T5, T6), wherein the second load current connection (L2) of the first power semiconductor switch (T1) is electrically conductively connected to the first load current connection (L1) of the fifth power semiconductor switch (T5) and to the first load current connection (L1) of the second power semiconductor switch (T2), wherein the second load current connection (L2) of the fifth power semiconductor switch (T5) is electrically conductively connected to the first load current connection (L1) of the sixth power semiconductor switch (T6),wherein the second load current terminal (L2) of the sixth power semiconductor switch (T6) is electrically conductively connected to the first load current terminal (L1) of the fourth power semiconductor switch (T4) and to the second load current terminal (L2) of the third power semiconductor switch (T3), wherein the second load current terminal (L2) of the second power semiconductor switch (T2) is electrically conductively connected to the first load current terminal (L1) of the third power semiconductor switch (T3), wherein the power converter (2) comprises a first diode (D1) electrically connected in anti-parallel to the first power semiconductor switch (T1), a second diode (D2) electrically connected in anti-parallel to the second power semiconductor switch (T2), a third diode (D3) electrically connected in anti-parallel to the third power semiconductor switch (T3), a fourth diode (D4) electrically connected in anti-parallel to the fourth power semiconductor switch (T4),a fifth diode (D5) electrically connected in anti-parallel to the fifth power semiconductor switch (T5), a sixth diode (D6) electrically connected in anti-parallel to the sixth power semiconductor switch (T6), and an alternating potential connection (AC) which is electrically conductively connected at a middle circuit node (M1) to the second load current connection (L2) of the second power semiconductor switch (T2) and to the first load current connection (L1) of the third power semiconductor switch (T3), wherein during operation of the power converter (2), the middle circuit node (M1) has an output voltage (Ua) with respect to the second load current connection (L2) of the fifth power semiconductor switch (T5), and an output current (Ia) flows in the current counting direction from the middle circuit node (M1) to the alternating potential connection (AC), wherein the control device (3) is designed to control the power semiconductor switches (T1, T2, T3, T4, T5, T6) in such a way to aim that, - the first, fifth, sixth and fourth power semiconductor switches (T1, T5, T6, T4) are switched on and off at a higher frequency than the second and third power semiconductor switches (T2, T3), -wherein the control device (3) is designed, starting from a first basic converter switching state in which the output voltage (Ua) is positive, the output current (Ia) is negative and the output current (Ia) flows through the first and second diodes, to transfer the converter (2) into a second basic converter switching state by at least switching on the fifth power semiconductor switch (T5) and by subsequently switching on the sixth power semiconductor switch (T6) and by subsequently switching on the third power semiconductor switch (T3), in which the fifth, sixth and third power semiconductor switches (T5, T6, T3) are switched on and a first part (4') of the output current (Ia) flows through the second diode (D2) and through the fifth power semiconductor switch (T5) and a second part (4") (of the output current (Ia) flows through the sixth diode D6) and through the third power semiconductor switch (T3). -wherein the control device (3) is designed to transfer the power converter (2) from the second basic power converter switching state to the first basic power converter switching state by switching off the third power semiconductor switch (T3) and subsequently switching off at least the fifth power semiconductor switch (T5). [2] Power converter device according to claim 1, characterized by in that the control device (3) is designed, starting from the second power converter basic switching state, to transfer the power converter (2) into the first power converter basic switching state by switching off the third power semiconductor switch (T3), by subsequently switching off the sixth power semiconductor switch (T6) and by subsequently switching off at least the fifth power semiconductor switch (T5). [3] Power converter device according to one of the preceding claims, characterized bythat the first, fifth, sixth and fourth power semiconductor switches (T1,T5,T6,T4) have, due to their design, smaller switching losses than the second and third power semiconductor switches (T2,T3). [4] Power converter device according to one of the preceding claims, characterized by that the semiconductor material from which the first, fifth, sixth and fourth power semiconductor switches (T1,T5,T6,T4) are formed is made of silicon carbide or gallium nitride and the semiconductor material from which the second and third power semiconductor switches (T2,T3) are formed is made of silicon. [5] Power converter device according to one of the preceding claims, characterized bythat the semiconductor material from which the first, fifth, sixth and fourth diodes (D1,D5,D6,D4) are formed is made of silicon carbide or gallium nitride and the semiconductor material from which the second and third diodes (D2,D3) are formed is made of silicon. [6] Power converter device according to one of the preceding claims, characterized by that the first, fifth, sixth and fourth power semiconductor switches (T1,T5,T6,T4) are designed as MOSFETs and the second and third power semiconductor switches (T2,T3) are designed as IGBTs. [7] Power converter device according to one of the preceding claims, characterized byin that the power converter (2) has a first and a second snubber capacitor (C1, C2), wherein a first terminal of the first snubber capacitor (C1) is electrically conductively connected to the first load current terminal (L1) of the first power semiconductor switch (T1) and a second terminal of the first snubber capacitor (C1) is electrically conductively connected to the second load current terminal (L2) of the fifth power semiconductor switch (T5), wherein a first terminal of the second snubber capacitor (C2) is electrically conductively connected to the first load current terminal (L1) of the sixth power semiconductor switch (T6) and a second terminal of the second snubber capacitor (C2) is electrically conductively connected to the second load current terminal (L2) of the fourth power semiconductor switch (T4). [8] Power converter device with a power converter (2') having a first, second, third, fourth, fifth and sixth power semiconductor switch (T1, T2, T3, T4, T5, T6), each having a first and a second load current connection (L1, L2), and with a control device (3') designed to control the power semiconductor switches (T1, T2, T3, T4, T5, T6), wherein the second load current connection (L2) of the first power semiconductor switch (T1) is electrically conductively connected to the first load current connection (L1) of the fifth power semiconductor switch (T5) and to the first load current connection (L1) of the second power semiconductor switch (T2), wherein the second load current connection (L2) of the fifth power semiconductor switch (T5) is electrically conductively connected to the first load current connection (L1) of the sixth power semiconductor switch (T6),wherein the second load current terminal (L2) of the sixth power semiconductor switch (T6) is electrically conductively connected to the first load current terminal (L1) of the fourth power semiconductor switch (T4) and to the second load current terminal (L2) of the third power semiconductor switch (T3), wherein the second load current terminal (L2) of the second power semiconductor switch (T2) is electrically conductively connected to the first load current terminal (L1) of the third power semiconductor switch (T3), wherein the power converter (2') comprises a first diode (D1) electrically connected in anti-parallel to the first power semiconductor switch (T1), a second diode (D2) electrically connected in anti-parallel to the second power semiconductor switch (T2), a third diode (D3) electrically connected in anti-parallel to the third power semiconductor switch (T3), a fourth diode (D4) electrically connected in anti-parallel to the fourth power semiconductor switch (T4),a fifth diode (D5) electrically connected in anti-parallel to the fifth power semiconductor switch (T5), a sixth diode (D6) electrically connected in anti-parallel to the sixth power semiconductor switch (T6), and an alternating potential connection (AC) which is electrically conductively connected at a middle circuit node (M1) to the second load current connection (L2) of the second power semiconductor switch (T2) and to the first load current connection (L1) of the third power semiconductor switch (T3), wherein, during operation of the power converter (2'), the middle circuit node (M1) has an output voltage (Ua) with respect to the second load current connection (L2) of the fifth power semiconductor switch (T5), and an output current (Ia) flows in the current counting direction from the middle circuit node (M1) to the alternating potential connection (AC), wherein the control device (3') is designed to control the power semiconductor switches (T1, T2, T3, T4, T5, T6) in such a way that, - the second and third power semiconductor switches (T2, T3) are switched on and off at a higher frequency than the first, fifth, sixth and fourth power semiconductor switches (T1, T5, T6, T4), -wherein the control device (3') is designed, starting from a first basic converter switching state in which the output voltage (Ua) is positive, the output current (Ia) is negative and the output current (Ia) flows through the first and second diodes (D1, D2), to transfer the converter (2') by at least switching on the third power semiconductor switch (T3), and by subsequently switching on a second power semiconductor switch (T2) and by subsequently switching on the fifth power semiconductor switch (T5) in a temporally successive manner, into a second basic converter switching state in which the second, fifth and third power semiconductor switches (T2, T5, T3) are switched on and a first part (4') of the output current (Ia) flows through the second diode (D2) and through the fifth power semiconductor switch (T5) and a second part (4") of the output current (Ia) flows through the sixth diode (D6) and through the third power semiconductor switch (T3). -wherein the control device (3') is designed to transfer the power converter (2') from the second power converter basic switching state to the first power converter basic switching state by switching off the fifth power semiconductor switch (T5) and by at least temporally subsequently switching off the third power semiconductor switch (T3). [9] Power converter device according to claim 8 characterized by that the control device (3') is designed, starting from the second power converter basic switching state, to transfer the power converter (2') into the first power converter basic switching state by switching off the fifth power semiconductor switch (T5), by subsequently switching off the second power semiconductor switch (T2) and by at least subsequently switching off the third power semiconductor switch (T3). [10] Power converter device according to one of claims 8 to 9, characterized bythat the second and third power semiconductor switches (T2,T3) have smaller switching losses than the first, fifth, sixth and fourth power semiconductor switches (T1,T5,T6,T4). [11] Power converter device according to one of claims 8 to 10, characterized by that the semiconductor material from which the second and third power semiconductor switches (T2,T3) are formed is made of silicon carbide or gallium nitride and the semiconductor material from which the first, fifth, sixth and fourth power semiconductor switches (T1,T5,T6,T4) are formed is made of silicon. [12] Power converter device according to one of claims 8 to 11, characterized by that the semiconductor material from which the second and third diodes (D2, D3) are formed is made of silicon carbide or gallium nitride and the semiconductor material from which the first, fifth, sixth and fourth diodes (D1, D5, D6, D4) are formed is made of silicon. [13] Power converter device according to one of claims 8 to 12, characterized by that the first, fifth, sixth and fourth power semiconductor switches (T1,T5,T6,T4) are designed as IGBTs and the second and third power semiconductor switches (T2,T3) are designed as MOSFETs. [14] Power converter device according to one of the preceding claims, characterized by that the respective first, second, third, fourth, fifth and sixth diodes (D1,D2,D3,D4,D5,D6) are designed as discrete components or are integrated into the semiconductor body of the respective power semiconductor switch (T1,T2,T3,T4,T5,T6) connected antiparallel to the respective diode (D1,D2,D3,D4,D5,D6).
Citation Information
Patent Citations
CN000112202353A