METHOD FOR EMBEDDING A NAKED CHIP IN A SUPPORT LAMINATE

Abstract

A method for embedding a naked chip (220) in a carrier laminate (102), comprising the method: Providing the naked chip (220) which has a metal layer (204, 206) on a front (FS) of the naked chip (220) or on a back (BS) of the naked chip (220) opposite the front (FS) (1210); Forming a layer (210) over the metal layer (204, 206) (1220); Mounting the bare chip (220) in a recess (108) of the carrier laminate (102), wherein the layer (210) faces an opening of the recess (108) (1230); Filling the recess (108) with a dielectric material (330) (1240); Removing part of the dielectric material (330) located on the layer (210) (1250); Deposition of a metal structure (880) over at least part of the layer (210) and at least a part of the carrier laminate (102) (1260).

Description

Technical field

[0001] Various embodiments generally refer to a method for embedding a naked chip in a carrier laminate. background

[0002] In current methods for embedding a bare chip into a substrate laminate, the back side of the chip is opened by dry etching (in a vacuum). This process is not well mastered by many printed circuit board manufacturers and requires specialized manufacturing equipment. Today, dry etching, as shown in the example for chip embedding, is used to remove organic material and expose the back side of the chip for further processing on the printed circuit board.

[0003] Laser drilling is another technique used to access the backside metallization of the chip, but it does not offer the possibility of a full-surface opening like dry plasma etching. Therefore, for the subsequent thermal and electrical behavior of the product, an embedded chip whose backside metallization has been partially exposed by laser is expected to operate less efficiently than a full-surface contact, such as one formed from a metal compound by copper plating.

[0004] DE 10 2016 203 453 A1 discloses a method for manufacturing a semiconductor device, which includes providing a planar support with a top and a bottom surface, wherein the support has a continuous recess extending between the top and bottom surfaces. In a further step, a semiconductor assembly is provided. The semiconductor assembly comprises a semiconductor chip that includes electrically and / or optically active areas on one bottom surface. Subsequently, the semiconductor assembly is positioned in the recess such that one bottom surface of the semiconductor assembly and the bottom surface of the support are in a common plane. The semiconductor assembly is then encapsulated with a potting compound in such a way that the semiconductor assembly is metallurgically bonded to the support. The semiconductor assembly, together with the support and the potting compound, forms a semiconductor system.The semiconductor system is then thinned by grinding from above so that a top surface of the support and a top surface of the semiconductor arrangement lie in a common plane.

[0005] US 6,423,570 B1 discloses a microelectronic package containing a microelectronic chip with an active surface and at least one face. An encapsulation material is placed adjacent to the face(s) of the microelectronic chip. A portion of the encapsulation material is removed to expose a back face of the microelectronic chip on which a metallization layer is applied. Prior to encapsulation, a protective layer is applied to the metallization layer so that the protective layer prevents damage to the metallization layer when the portion of the encapsulation material is removed. After the portion of the encapsulation material is removed, the protective layer is removed, and the metallization layer is exposed. Subsequently, a heat spreader can be attached to the microelectronic chip by placing the heat spreader against the metallization layer and melting the metallization layer.

[0006] DE 10 2021 101 0 10 A1 discloses a pre-packaged chip comprising a chip with at least one electrical upper contact on a top side of the chip and at least one electrical lower contact on a bottom side opposite the top side, a first laminate layer on the top side, a second laminate layer on the bottom side, wherein the first laminate layer and the second laminate layer are laminated together to sandwich the chip between them, a first metal layer on the first laminate layer which is in electrical contact with the at least one electrical upper contact via at least one upper contact hole through the first laminate layer, and a second metal layer on the second laminate layer which is in electrical contact with the at least one electrical lower contact via at least one lower contact hole through the second laminate layer, wherein the pre-packaged chip is free of any contact hole.extending from the first metal layer to the second metal layer. Brief description

[0007] A method for embedding a naked chip in a substrate laminate is provided. The method comprises providing the naked chip, which has a metal layer on a front side of the naked chip or on a back side of the naked chip opposite the front side, forming a layer over the metal layer, placing the naked chip in a recess of the substrate laminate, the layer facing an opening of the recess, filling the recess with a dielectric material, removing a portion of the dielectric material located on the layer, and depositing (e.g., by electroless coating, sputtering, or atomic layer deposition (ALD)) a metal structure over at least a portion of the layer and at least a portion of the substrate laminate. Brief description of the drawings

[0008] In the drawings, identical reference numerals generally refer to identical parts in the different views. The drawings are not necessarily to scale, with the emphasis generally being on illustrating the principles of the invention. The following description details various embodiments of the invention with reference to the following drawings, in which: Fig. Figures 1A to 10A illustrate a method for embedding a naked chip in a carrier laminate according to various embodiments; Fig. Figures 1B to 10B illustrate a method for embedding a naked chip in a carrier laminate according to various embodiments; Fig. Figures 1C to 10C illustrate a method for embedding a naked chip in a carrier laminate according to various embodiments; Fig. Figures 1D to 10D illustrate a method for embedding a naked chip in a carrier laminate according to a prior art; Fig. Figure 11A shows alternative configurations of the naked chip for use in the procedure of Fig. 1A to 10A; Fig. 11B shows alternative configurations of the naked chip for use in the procedure of Fig. 1B to 10B; Fig. Figure 11C shows alternative configurations of the naked chip for use in the procedure of Fig. 1°C to 10°C; Fig. Figure 12 shows a flowchart of a method for embedding a naked chip in a carrier laminate according to various embodiments; and Fig. Figure 13 shows a chip embedded in a carrier according to various embodiments. Description

[0009] The following detailed description refers to the attached drawings, which show specific details and embodiments of the invention for illustrative purposes.

[0010] The word "exemplary" is used here in the sense of "serving as an example, instance, or illustration." Each embodiment or design described here as "exemplary" is not necessarily to be interpreted as preferable or advantageous over other embodiments or designs.

[0011] The word "over" in reference to a deposited material formed "over" a side or surface can be used here to mean that the deposited material can form "directly on," for example, in direct contact with the indicated side or surface. The word "over" in reference to a deposited material formed "over" a side or surface can also be used here to mean that the deposited material can form "indirectly on" the indicated side or surface, with one or more additional layers arranged between the indicated side or surface and the deposited material.

[0012] Various aspects of the revelation relate to devices, and various aspects of the revelation relate to processes. It is understood that fundamental properties of the devices also apply to the processes, and vice versa. For the sake of brevity, therefore, duplicate descriptions of such properties have been omitted.

[0013] In various embodiments, bare chips (short: dies or chips) can be supplied with a dielectric material, e.g. a resist, that covers the back and / or front metal layer (also referred to as metallization or contact pad), or with a thick back and / or front metallization that can be achieved by means of an additional metal layer over (e.g. on) the back and / or front metal layer.

[0014] In this context, "thick" refers at least to the thickness of the metal layer that is typically present on a chip surface, e.g., as a chip contact pad.

[0015] The dielectric or metal layer can be at least as thick as the metal layer. The thick dielectric or metallic layer can be up to about 15 times as thick as the metal layer.

[0016] In various embodiments, the bare chips can be coated with a thin metal layer, e.g., a layer of sputtered material, a thin film, or a nanocoating, to create a pre-seed layer on the chip surface. The thin layer can cover the entire surface or be applied selectively, e.g., only to the metal layer(s), such as the front and / or backside metallization.

[0017] The layer (e.g., the thick dielectric layer, the thick metal layer, or the thin metal layer) can be formed during a front-end-of-line process, such as wafer processing. In other words, the layer may already be present on the bare chip when the chip is prepared for PCB assembly / processing.

[0018] The thin layer of seeds can be flattened to form a thicker layer.

[0019] In various embodiments, the use of standard printed circuit board (PCB) manufacturing processes such as grinding or wet embedding can be advantageous compared to the prior art. This can lead to significantly faster, simpler, and more cost-effective chip or inlay embedding processing at a PCB manufacturer. In particular, time-consuming and / or expensive non-standard techniques such as vacuum plasma etching, sputtering, and / or high-density microvia laser drilling can be avoided or minimized.

[0020] In various embodiments, particularly with the additional thick dielectric or metal layer, the chip would be better protected against mechanical damage during handling, e.g., when placing the chip.

[0021] Furthermore, the tolerances in positioning the naked chip can be smaller, since the area removed for contact with the naked chip is defined by the naked chip itself.

[0022] A first method for embedding a naked chip in a carrier laminate according to various embodiments is described in Fig. 1A to 10A are shown.

[0023] A second method for embedding a naked chip in a carrier laminate according to various embodiments is described in Fig. 1B to 10B are shown.

[0024] A third method for embedding a naked chip in a carrier laminate according to various embodiments is described in the Fig. 1°C to 10°C are shown.

[0025] These methods, in particular their similarities and differences, are explained below. Whenever appropriate, the methods according to the embodiments are compared with a prior art method for embedding a naked chip in a carrier laminate, as described in Fig. Displayed in 1D to 10D.

[0026] In each of the Fig. Figures 1A to 10D show the lower figure as a schematic top view of a chip 1300 embedded in a substrate at various processing stages, and the upper figure schematically shows a horizontal cross-section through the center of the chip 1300 embedded in a substrate. The position of the cross-section is only shown in Fig. 1A is indicated as a dotted horizontal line.

[0027] A carrier laminate 102 with a recess 108 can be provided. Examples of this are in Fig. Figures 1A to 1C are shown. The carrier laminate 102 and the recess 108 formed therein can be similar to or identical with the prior art.

[0028] The carrier laminate 102 can, for example, have or consist of any type of carrier material typically used for a carrier laminate 102, such as a printed circuit board laminate (e.g., FR4, BT laminate). The carrier laminate 102 can have or consist of a dielectric material that is either fully cured (e.g., copper-clad laminate, CCL) or B-stage cured (prepreg). The carrier laminate 102 can be pre-cut to form the cavity into which the object (i.e., a bare chip 220) is to be embedded, in order to obtain a better topological fit for lamination and further processing of the laminate substrate.

[0029] The recess 108 can be formed as a through-hole. To enable the insertion of the bare chip 220 into the recess 108, particularly in the case of a through-hole, a temporary support 106 can be attached to the underside of the support laminate 102. In other embodiments, the recess 108 may extend only partially through the support laminate 102 (not shown). In such a case, machining of both sides of the support laminate 102 may be necessary if the bare chip 220 has contact pads on both opposite sides (for details on the bare chip, see the description in connection with the Fig. 2A to 2C).

[0030] Through-holes 104, extending through the substrate laminate 102 from a top side to a bottom side, can be formed in various embodiments, e.g., vias or other types of through-holes 104. However, even if all figures show the through-hole 104, the substrate laminate 102 of various embodiments can be free of the through-hole 104.

[0031] The method for embedding the naked chip 220 in the carrier laminate 102 according to various embodiments includes providing the naked chip 220, which has a metal layer 206 or 204 on a front side FS of the naked chip 220 or on a back side BS of the naked chip 220 opposite the front side FS.

[0032] The bare chip 220 can be a semiconductor chip that forms an electronic component or incorporates an integrated circuit. The bare chip 220 can be provided with a plurality of die contacts for electrically contacting the electronic component or integrated circuit. In a case where a plurality of die contacts 204 or 206 are provided on the same side (such as the plurality of die contacts on the front side FS of the in Fig. In the chips 220 shown in Figures 2A to 2C, an electrically insulating material 208 can be provided between the respective die contacts 204 and 206. The metal layer(s) 204, 206 can form the die contacts or make electrical contact and are therefore also referred to as chip contact pads, die contact pads, or contact pads. Another term for the metal layer(s) 204, 206 is chip metallization. In a case where the chip 220 has a control chip contact and at least one controlled chip contact, the front side FS can be defined as the side with the control contact.

[0033] In various embodiments, a passivation layer 1150 (shown only by way of example) can be placed between the semiconductor material and the metal layer 204, 206. Fig. 11C is represented and is essentially formed as is known in the art).

[0034] The method for embedding the naked chip 220 in the carrier laminate 102 according to various embodiments further comprises the formation of a layer 210 over the metal layer 204, 206.

[0035] According to various embodiments, three different types of layers 210 are provided:

[0036] Option A (shown in Fig. 1A to 10A) has a (thick) dielectric layer 210, 210a. In the exemplary embodiment of Fig. In layers 2A to 10A, layer 210, 210a is formed above the metal layer 204 on the back side BS of the bare chip 220, 220a. As shown in Fig. As shown in 11A, other embodiments may also have the dielectric layer 210, 210a only on the front side FS of the chip 220, 220a (on the left side of Fig. 11A shown) or both on the front FS and on the back BS of the chip 220, 220a (on the right side of Fig. 11A) show.

[0037] The dielectric layer 210, 210a may, for example, have or consist of a resist material (which can be easily removed by means of photoprocessing, e.g. light development and decomposition) or another dielectric material suitable for printed circuit board processing and which can be easily removed by wet etching and / or laser ablation.

[0038] The dielectric layer 210, 210a can have a thickness in a range of about 2 µm to about 30 µm, for example from about 5 µm to about 25 µm, for example from about 10 µm to about 20 µm.

[0039] Option B (shown in Fig. 1B to 10B) has a (thick) metal layer 210, 210b. In the exemplary embodiment of Fig. Layers 2B to 10B are formed above the metal layer 204 on the back side BS of the bare chip 220, 220b. As shown in Fig. As shown in 11B, other embodiments may also have the metal layer 210, 210b only on the front side FS of the bare chip 220, 220b (on the left side of Fig. 11B shown) or both on the front FS and on the back BS of the naked chip 220, 220b (on the right side of Fig. 11B) show.

[0040] The metal layer 210, 201b may, for example, contain or consist of copper or a copper alloy, aluminium or an aluminium alloy, or any other metal suitable for printed circuit board processing.

[0041] The thick metal layer 210, 210b can have a thickness in a range of about 2 µm to about 30 µm, for example from about 5 µm to about 25 µm, for example from about 10 µm to about 20 µm.

[0042] Option C (shown in Fig. 1C to 10C) has a (thin) metal layer 210, 210c. To visually distinguish it from the thick metal layer 210, 210b, the thin metal layer 210, 210c is shown in the Fig. Temperatures from 1C to 10C are represented as a shaded "glow" that has no physical meaning.

[0043] The (thin) metal layer 210, 210c can, for example, be formed from or have a sputtered material, a thin film, or a nanocoating to create a pre-seed layer on the surface of the metal layer 210, 210c and optionally also on a surface of the semiconductor material of the chip 220, 220c and on the surface of the insulating material 208. In other words, the (thin) metal layer 210, 210c can be applied either in such a way that it completely covers the surface of the front side FS and / or the back side BS of the chip, or in such a way that it selectively covers only the metal layer(s) 210, 210c.

[0044] The thin metal layer 210, 210c, which may be a pre-seeding layer, can have a thickness in the range of about 1 nm to about 2 µm, for example from about 5 nm to about 10 µm, for example from about 10 nm to about 1 µm.

[0045] The in Fig. A 2D representation of the naked chip 200 according to the state of the art can only have at least one metal layer 204 without layer 210.

[0046] In the exemplary embodiment of Fig. Layers 2C to 10C form layer 210, 210c over the metal layer 204 on the back side BS of the bare chip 220, 220c. As shown in Fig. As shown in 11C, other embodiments may also have the metal layer 210, 210c only on the front side FS of the bare chip 220, 220b (on the left side of Fig. 11C shown) or both on the front FS and on the back BS of the naked chip 220, 220b (on the right side of Fig. 11C shown).

[0047] In various embodiments, the naked chip 210 can be arranged in the recess 108 of the carrier laminate 102 such that the layer 210 faces an opening of the recess 108 (in other words, away from the temporary carrier 106).

[0048] In a case where both sides (FS and BS) of the naked chip 220 can form layer 210, the side of the naked chip 220 to be placed on the temporary support 106 can be selected as suitable for the application, and further processing can be carried out in addition to the processes described below, which focus on processing the naked chip embedded in the support from above, as in Fig. Figures 2A to 10C show processing from the underside of the naked chip embedded in the carrier (e.g., after removal of the temporary carrier 106). In such a case, if appropriate, the processing can be carried out simultaneously from both sides of the naked chip embedded in the carrier. Alternatively, the top and bottom (or vice versa) can be processed sequentially.

[0049] In the Fig. 2A and Fig. In the embodiments shown in Figure 2B, the total thickness of the bare chip 220, which has the layer 210, can be greater than the depth of the recess or than the thickness of the carrier laminate 102. As a result, the layer 210 can protrude from the recess.

[0050] In the Fig. 2A and Fig. In the embodiments shown in Figure 2B, the total thickness of the bare chip 220, 220a, 220b, which has the layer 210, 210a or 210b respectively, can be greater than the depth of the recess 108 and greater than the thickness of the carrier laminate 102. As a result, the layer 210 can protrude from the recess 108.

[0051] In the Fig. In the embodiment shown in Figure 2C, the total thickness of the bare chip 220, 220c, which has the layer 210, 210c, can be approximately equal to (for example, slightly less than) the depth of the recess 108 and approximately equal to (for example, slightly less than) the thickness of the carrier laminate 102. As a result, a surface of the layer 210 can be more or less flush with a surface of the carrier laminate 102 adjacent to an opening of the recess 108 (optionally slightly lower than it).

[0052] According to the current state of the art, the naked chip 200 is usually significantly thinner than the depth of the recess 108.

[0053] The method for embedding the bare chip 220 in the carrier laminate 102 according to various embodiments further comprises filling the recess 108 with a dielectric material 330. The dielectric material 330 can, for example, comprise or consist of a resin, an adhesive, or another encapsulation material used in the art for encapsulating bare chips. The dielectric material 330 can be used for encapsulating and fixing the bare chip in the carrier laminate 102, e.g., the PCB core layer, and in particular for fixing the bare chip 220 in the recess 108 in the carrier laminate 102.

[0054] The dielectric material 330 can, for example, be applied, produced by screen or stencil printing or laminated (e.g. an Ajinomoto Boding Film (ABF)) and can, for example, be a Photo-Imageable Dielectric (PID) or a liquid polyimide, which can then be cured.

[0055] The dielectric material 330 can be applied in various embodiments such that it extends outside the recess 108. The dielectric material 330 can at least partially (e.g., completely) cover the top surface of the bare chip 220 (the side facing away from the temporary support laminate 106), for example, layer 210, and / or a top surface of the support laminate 106. Corresponding exemplary embodiments are described in the Fig. 3A and Fig. Figure 3B shows embodiments having the thick dielectric layer 210, 210a and the thick metal layer 210, 210b respectively.

[0056] In various embodiments, the dielectric material 330 can be arranged essentially only within the recess 108. For example, an upper surface of the dielectric material can be essentially flush with the upper surface of the support laminate 102. In a case where the bare chip 220, 220c is somewhat smaller than the depth of the recess 108, the layer 210, 210c can be partially or completely covered by a thin layer of dielectric material 330. A corresponding embodiment is described in Fig. 3C shown.

[0057] According to the current state of the art, as in Fig. 3D shown, a relatively large part of the dielectric material 330 is stacked over the bare chip 200.

[0058] In various embodiments, the temporary support 106 can be removed at this stage of the process. Corresponding exemplary embodiments are described in the Fig. Figures 4A to 4C are shown. According to the state of the art, the temporary support 106 can also be removed at this stage, as shown in Fig. Illustrated in 4D. Alternatively, the temporary support 106 can also be removed at a later time.

[0059] The method for embedding the naked chip 220 in the carrier laminate 102 according to various embodiments further includes the removal of a part of the dielectric material 330 located on layer 210.

[0060] The ablation process can include, for example, mechanical grinding, wet chemical processes (e.g., etching), laser ablation, and / or optically assisted ablation (e.g., light generation and decomposition). Optically assisted removal can be used in conjunction with any type of layer 330 (e.g., the dielectric layer 330, 330a, the thick metal layer 330, 330b, and / or the thin metal layer 330, 330c), provided that a photoimaginable dielectric (PID) is used as the dielectric material 330. In this case, lithography can be used to open the chip backside BS.

[0061] Fig. Figures 5A to 5C show some of the exemplary embodiments.

[0062] To remove the relatively thick dielectric material 330 together with part of the (in this case dielectric) layer 310, 310a, which is in Fig. As shown in Figure 5A, mechanical grinding with a grinding machine 550, 550a may be suitable. However, in various embodiments, laser ablation (not shown) may be chosen, for example, to remove the relatively thick dielectric material 330. After removal, a portion of the dielectric layer 310, 310a may remain and be exposed on the top side of the embedded chip 1300.

[0063] For the removal of the relatively thick dielectric material 330 together with part of the (in this case metallic) layer 310, 310b, which in Fig. As shown in Figure 5B, mechanical grinding with a grinding machine 550, 550a may be suitable. However, in various embodiments, laser ablation (not shown) may be chosen, for example, to remove the relatively thick dielectric material 330. After the ablation process, a portion of the metal layer 310, 310a may remain and be exposed on the top side of the embedded bare chip 1300.

[0064] For the removal of the relatively thin dielectric material 330, which is in Fig. As shown in Figure 5C, laser ablation may be suitable. Since the dielectric material 330 forms, if anything, only a thin layer on the thin metal layer 310, 310c, the metal layer 310, 310c can be exposed on the top side of the embedded bare chip 1300 after removal of the dielectric material 330. Plasma etching can also be used if it is considered advantageous, as it requires only a short processing time for the thin dielectric material layer 330.

[0065] In the state of the art, as in Fig. 5D representation, laser processing using, for example, a 550 or 550b laser.

[0066] In various embodiments, as above in connection with Fig. As described in section 5A, grinding (or optionally laser processing) may not have resulted in electrically conductive access to a chip contact exposed on the outer surface of the embedded bare chip 1300. Therefore, further processing may be necessary.

[0067] As in Fig. Figure 6A shows that wet etching can be performed, as indicated by the wave symbols 662, which represent a liquid, in this case the etchant 662. Alternatively, dry etching or plasma etching, for example, can also be used.

[0068] The etchant 662 can be selected for the selective etching of the (dielectric) layer 610, 610a. The etching process can be continued until the metal layer 204 is exposed.

[0069] The in Fig. The 2D method shown according to the prior art does not allow such treatment, since the entire top surface is covered with the same material. Instead, as shown in Fig. 6D shown and indicated by the arrows 664, a dry etching process is used which is expensive and time-consuming.

[0070] The results of the procedures are in the Fig. 7A to 7D are shown.

[0071] The method for embedding the naked chip 220 in the carrier laminate 102 according to various embodiments further comprises the deposition (e.g. by electroless plating, sputtering or ALD) of a metal structure 880, 880a over at least a part of the layer 310 and at least a part of the carrier laminate 102.

[0072] In various embodiments, the metal structure 880, 880a can include copper, for example, a copper seed layer. The metal structure 880, 880a can, for example, cover the entire surface of layer 310 and the support laminate 102 or be pre-structured by a masking process (not shown).

[0073] Corresponding embodiments are described in the Fig. 8A to 8C are shown.

[0074] At the in Fig. In the prior art method shown in Figure 8D, the metal structure 880, 880b is applied using a sputtering process, which, compared to the electroless deposition process used in various embodiments, is a non-standardized, time-consuming and expensive PCB process.

[0075] The subsequent processing is essentially carried out as is known in the technology. Thus, the characteristics that occur during the process are... Fig. The features added to the embodiments shown in Figures 9A to 10A, 9B to 10B and 9C to 10C are similar to or identical with the features added according to the prior art, as shown in the Fig. Displayed in 9D to 10D.

[0076] In various embodiments, a further metal layer 992 can be applied to the seed layer, for example using a standard electrolytic copper process. The further metal layer 992 can be formed as a structured layer, for example using a mask 990.

[0077] The coating process is in the Fig. 9A to 9C for the embodiments and in Fig. 9D representation of the state of the art.

[0078] It should be noted that the processing may result in a slight dent or indentation in the Fig. 9A and Fig. 9C embodiments shown and in the embodiment shown Fig. The state of the art is shown in 9D. This is indicated by the white shaded rectangle in the Fig. 9A, Fig. 9C and Fig. 9D indicated. In contrast, the further metal layer 992 of the in Fig. In the embodiment shown in 9B, where layer 310, 310b is the metal layer, the dent is not on, but on a flat surface.

[0079] The additional metal layer 992 can have a thickness of at least 5 µm.

[0080] In various embodiments, the metal structure 880, 880a in areas outside the further metal layer 992 can be removed by standard methods, e.g., etching. Similarly, the metal structure 880, 880b of the prior art is also removed.

[0081] Exemplary embodiments are shown in the Fig. 10A to 10C are shown. They may be similar to or identical to the one in Fig. The distance method shown in 10D represents the state of the art.

[0082] Further processing can be carried out in known ways, e.g. by adding a surface finish, cutting, forming a redistribution layer, etc.

[0083] An exemplary embodiment of a finished naked chip 1300 embedded in a carrier is shown in Fig. 13 shown.

[0084] In addition to the features described above in connection with the method of various embodiments, the chip 1300 embedded in the carrier has a redistribution layer 1306 placed over a dielectric material 1302, which is in contact with the chip 202 or with the further metal layer 992 via vias 1304.

[0085] Fig. Figure 12 shows a flowchart 1200 of a method for embedding a naked chip in a carrier laminate according to various embodiments.

[0086] The method comprises providing a naked chip having a metal layer on a front side of the naked chip or on a back side of the naked chip opposite the front side (1210), forming a layer over the metal layer (1220), placing the naked chip in a recess of the carrier laminate, the layer being opposite an opening of the recess (1230), filling the recess with a dielectric material (1240), removing part of the dielectric material located on the layer (1250), and electroless coating of a metal structure over at least part of the layer and at least part of the carrier laminate (1260).

[0087] In summary, additional pre-applied material (e.g., plated, laminated, printed, coated) can be applied to the embeddable object (e.g., the embeddable chip), and the pre-applied material is later exposed during printed circuit board manufacturing, allowing the use of more traditional or robust printed circuit board processes familiar to manufacturers.

[0088] The process can also be used for open cast housings.

[0089] The following are several examples:

[0090] Example 1 is a method for embedding a naked chip in a carrier laminate, wherein the method comprises providing the naked chip, which has a metal layer on a front side of the naked chip or on a back side of the naked chip opposite the front side, forming a layer over the metal layer, placing the naked chip in a recess of the carrier laminate, the layer facing an opening of the recess, filling the recess with a dielectric material, removing part of the dielectric material located on the layer, and depositing a metal structure over at least part of the layer and at least part of the carrier laminate.

[0091] According to Example 1a, the item of Example 1 may optionally feature that the deposition process includes electroless coating, sputtering or Atomic Layer Deposition (ALD).

[0092] In Example 2, the object of Example 1 may optionally have a layer that is either a dielectric layer or an electrically conductive layer, or that consists of such a layer.

[0093] In Example 3, the subject of Example 1 or 2 may optionally have the layer or dielectric material comprising or consisting of a photoresist material.

[0094] In Example 4, the object according to one of Examples 1 to 3 may optionally further have the feature that, after the removal of a part of the dielectric material located on the layer, the layer is removed.

[0095] In Example 5, the subject of Example 4 may optionally include or consist of wet etching, dry etching, plasma etching or photodegradation.

[0096] In Example 6, the object from Example 1 or 2 may optionally have a layer of metal, optionally copper, or consist of it.

[0097] In Example 7, the item according to one of Examples 1 to 6 may optionally have the total thickness of the bare chip including the layer being thicker than the depth of the recess.

[0098] In Example 8, the object of one of Examples 1 to 7 may optionally have the thickness of the layer greater than the thickness of the metal layer.

[0099] In Example 9, the object according to one of Examples 1 to 8 may optionally have a layer thickness in a range of about 2 µm to about 30 µm.

[0100] In Example 10, the item according to any one of Examples 1 to 9 may optionally include the formation of the layer over the metal layer comprising or consisting of plating, laminating, printing and / or coating.

[0101] In Example 11, the object of one of Examples 1 to 10 may optionally have the support being a printed circuit board.

[0102] In Example 12, the object according to any one of Examples 1 to 11 may optionally have the arrangement of the dielectric material filling the recess such that it extends beyond the layer and at least partially covers the layer.

[0103] In Example 13, the item according to any one of Examples 1 to 12 may optionally feature the removal of part of the dielectric material located on the layer by grinding, laser ablation or photodegradation.

[0104] In Example 14, the item from any of Examples 1 to 13 may optionally include the placement of the naked chip in the recess, which involves arranging the naked chip on a temporary support.

[0105] According to Example 15, the object of Example 14 may optionally also feature the removal of the temporary support after the dielectric has been applied.

[0106] In Example 16, the item according to one of Examples 1 to 15 may optionally have that the naked chip further comprises an additional metal layer on the other side of the naked chip opposite the metal layer.

[0107] According to Example 17, the object of Example 16 may also optionally include the arrangement of another layer above the other metal layer.

[0108] According to Example 18, the object of Example 17 may optionally have the further layer be made of or composed of the same material as the layer.

[0109] According to Example 19, the subject of Example 1 may optionally have the layer forming or consisting of an electrically conductive layer of sputtered material, a thin film or a nanocoating.

[0110] According to Example 20, the object of Example 19 may optionally have that the thickness of the layer is less than the thickness of the metal layer.

[0111] According to Example 21, the subject of Example 19 or 20 may optionally have a layer thickness in the range of about 1 nm to about 2 µm.

[0112] In Example 22, the object of one of Examples 19 to 21 may optionally have an atomic layer deposition (ALD) layer.

[0113] According to Example 23, the subject of Example 22 may optionally have the ALD layer covering a plurality of sides of the naked chip and optionally encapsulating the naked chip.

[0114] In Example 24, the object according to one of Examples 1 to 23 may optionally also include the application of a thick metal layer over the metal layer.

[0115] According to Example 25, the object of Example 24 may optionally have the arrangement of the thick metal layer having or consisting of electroless coating.

[0116] In Example 26, the object of one of Examples 1 to 25 may optionally have a metal layer that contains or consists of copper or aluminum.

[0117] In Example 27, the object of one of Examples 1 to 26 may optionally have the dielectric material being a photosensitive resin.

Claims

[1] A method for embedding a naked chip (220) in a carrier laminate (102), comprising the method: Providing the naked chip (220) which has a metal layer (204, 206) on a front (FS) of the naked chip (220) or on a back (BS) of the naked chip (220) opposite the front (FS) (1210); Forming a layer (210) over the metal layer (204, 206) (1220); Mounting the bare chip (220) in a recess (108) of the carrier laminate (102), wherein the layer (210) faces an opening of the recess (108) (1230); Filling the recess (108) with a dielectric material (330) (1240); Removing part of the dielectric material (330) located on the layer (210) (1250); Deposition of a metal structure (880) over at least part of the layer (210) and at least a part of the carrier laminate (102) (1260). [2] Method according to claim 1, wherein the layer (210) has or consists of a dielectric layer or an electrically conductive layer. [3] Method according to claim 1 or 2, wherein the layer (210) or the dielectric material (330) comprises or consists of a photoresist material. [4] Method according to claim 1 or 2, wherein the layer (210) comprises or consists of a metal, optionally copper. [5] Method according to any one of claims 1 to 4, wherein the total thickness of the naked chip (220) having the layer is thicker than the depth of the recess (108). [6] Method according to any one of claims 1 to 5, wherein the thickness of the layer (210) is greater than the thickness of the metal layer (204, 206). [7] Method according to any one of claims 1 to 6, wherein the thickness of the layer (210) is in a range of about 2 µm to about 30 µm. [8] Method according to any one of claims 1 to 7, wherein forming the layer (210) over the metal layer (204, 206) comprises or consists of plating, laminating, printing and / or coating. [9] Method according to any one of claims 1 to 8, wherein the carrier (102) is a printed circuit board. [10] Method according to any one of claims 1 to 9, wherein the arrangement of the dielectric material (330) filling the recess (108) comprises the arrangement of the dielectric material (330) such that it extends beyond the layer (210) and at least partially covers the layer (210). [11] Method according to any one of claims 1 to 10, wherein the removal of a part of the dielectric material (330) located on the layer (210) comprises grinding, laser ablation or photodegradation. [12] Method according to any one of claims 1 to 11, wherein mounting the naked chip (220) in the recess (108) comprises arranging the naked chip (220) on a temporary carrier (106). [13] Method according to claim 12, further comprising: after applying the dielectric, removing the temporary support (106). [14] Method according to any one of claims 1 to 13, wherein the naked chip (220) further comprises a further metal layer (992) on the other side of the naked chip (220) opposite the metal layer (204, 206). [15] Method according to claim 14, further comprising: Applying another layer over the other metal layer (992). [16] Method according to claim 15, wherein the further layer has or consists of the same material as layer (210). [17] Method according to claim 1, wherein the layer (210) comprises or consists of an electrically conductive layer formed from sputtered material, a thin film or a nanocoating. [18] Method according to claim 17, wherein the thickness of the layer (210) is less than the thickness of the metal layer (204, 206). [19] Method according to claim 17 or 18, wherein the thickness of the layer (210) is in a range of about 1 nm to about 2 µm. [20] Method according to any one of claims 17 to 19, wherein the layer (210) is an atomic layer deposition (ALD) layer. [21] Method according to claim 20, wherein the ALD layer covers a plurality of sides of the naked chip (220) and optionally encapsulates the naked chip (220). [22] Method according to any one of claims 1 to 21, further comprising: Applying a thick metal layer over the metal layer (204, 206). [23] Method according to claim 22, wherein the application of the thick metal layer comprises or consists of a currentless coating. [24] Method according to any one of claims 1 to 23, wherein the metal layer (204, 206) comprises or consists of copper or aluminium. [25] Method according to any one of claims 1 to 24, wherein the dielectric material is a photosensitive resin.

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