Semiconductor module arrangement

Abstract

A semiconductor module arrangement comprises a first substrate with a first plurality of semiconductor bodies; a second substrate with a second plurality of semiconductor bodies; and a third substrate with a third plurality of semiconductor bodies. The first, second, and third plurality of semiconductor bodies together form a semiconductor arrangement comprising a first node and a second node. The first, second, and third substrates are arranged side-by-side in a plane, with the first substrate positioned between the second and third substrates. A layout of the third substrate is identical to a layout of the second substrate. The first substrate is configured to connect to both the first and second nodes, and each of the second and third substrates is configured to connect to a third node.A first current path, between the first node and the third node via the first and second substrates, offers identical voltage and current transmission properties as a second current path, between the first node and the third node via the first and third substrates, and a third current path, between the second node and the third node via the first and second substrates, offers identical voltage and current transmission properties as a fourth current path, between the second node and the third node via the first and third substrates.

Claims

[1] A semiconductor module arrangement (100) comprising: a first substrate (101) having a first plurality of semiconductor bodies (20) arranged thereon; a second substrate (10 21 ) with a second plurality of semiconductor bodies (20) arranged thereon; and a third substrate (10 22 ) with a third plurality of semiconductor bodies (20) arranged thereon, wherein the first, second and third plurality of semiconductor bodies (20) together form a semiconductor arrangement, the semiconductor arrangement comprising a first node (ND1) configured to be operatively coupled to a first electrical potential and a second node (ND2) configured to be operatively coupled to a second electrical potential different from the first electrical potential, the first substrate (101), the second substrate (10 21) and the third substrate (10 22 ) are arranged side by side in a plane, wherein the first substrate (101) is arranged between the second substrate (10 21 ) and the third substrate (10 22 ) is arranged, a layout of the third substrate (10 22 ) with the third plurality of semiconductor bodies (20) arranged thereon, equal to a layout of the second substrate (10 21 ) with the second plurality of semiconductor bodies (20) arranged thereon, the first substrate (101) is adapted to be connected to the first node (ND1) and the second node (ND2), from the second substrate (10 21 ) and the third substrate (10 22 ) each adapted to be connected to a third node (ND3), a first current path (80 11 ) extending between the first node (ND1) and the third node (ND3) via the first substrate (101) and the second substrate (1021 ) has identical voltage and current transfer properties as a second current path (80 12 ) extending between the first node (ND1) and the third node (ND3) via the first substrate (101) and the third substrate (10 22 ) extends, offers, and a third current path (80 13 ) extending between the second node (ND2) and the third node (ND3) via the first substrate (101) and the second substrate (10 21 ) has identical voltage and current transfer properties as a fourth current path (80 14 ) extending between the second node (ND2) and the third node (ND3) via the first substrate (101) and the third substrate (10 22 ) extends. [2] Semiconductor module arrangement (100) according to claim 1, wherein the semiconductor bodies (20) of the first plurality of semiconductor bodies (20) are slow-switching semiconductor bodies; and the semiconductor bodies (20) of the second plurality of semiconductor bodies (20) and the semiconductor bodies (20) of the third plurality of semiconductor bodies (20) are fast-switching semiconductor bodies, where a fast-switching semiconductor body is a semiconductor body that switches between different switching states faster than a defined threshold speed, and a slow-switching semiconductor body is a semiconductor body that switches between different switching states slower than the defined threshold speed. [3] Semiconductor module arrangement (100) according to claim 1 or 2, wherein the semiconductor arrangement formed by the first, second and third plurality of semiconductor bodies (20) has an input stage (IPS) and an output stage (OPS), the input stage (IPS) is formed by the first plurality of semiconductor bodies (20), the second plurality of semiconductor bodies (20) forms a first output sub-stage (OPS1) and the third plurality of semiconductor bodies (20) forms an identical second output sub-stage (OPS2), and the first output sub-stage (OPS1) and the second output sub-stage (OPS2) can be operated in parallel or separately. [4] Semiconductor module arrangement (100) according to one of claims 1 to 3, wherein the second plurality of semiconductor bodies (20) and the third plurality of semiconductor bodies (20) each form a half-bridge arrangement. [5] Semiconductor module arrangement (100) according to one of claims 1 to 4, wherein the semiconductor arrangement formed by the first, second and third plurality of semiconductor bodies (20) further comprises: a fourth node (NP) adapted to be operatively connected to a third electrical potential different from the first electrical potential and the second electrical potential, a first controllable semiconductor element (T1) and a second controllable semiconductor element (T2), each having a control electrode (G1, G2) and a controllable load path between two load electrodes, wherein the first and second controllable semiconductor elements (T1, T2) are connected to one another such that their respective load paths form a series circuit between the first node (ND1) and the fourth node (NP), wherein the first controllable semiconductor element (T1) and the second controllable semiconductor element (T2) are connected to one another via a first common node (P), a third controllable semiconductor element (T3) and a fourth controllable semiconductor element (T4), each having a control electrode (G3, G4) and a controllable load path between two load electrodes, wherein the third and fourth controllable semiconductor elements (T3, T4) are connected to one another such that their respective load paths form a series circuit between the fourth node (NP) and the second node (ND2), wherein the third controllable semiconductor element (T3) and the fourth controllable semiconductor element (T4) are connected to one another via a second common node (N), a fifth controllable semiconductor element (T51) and a sixth controllable semiconductor element (T61), each having a control electrode (G51, G61) and a controllable load path between two load electrodes, wherein the fifth and sixth controllable semiconductor elements (T5, T6) are connected to one another such that their respective load paths form a series circuit between the first common node (P) and the second common node (N), wherein the fifth controllable semiconductor element (T51) and the sixth controllable semiconductor element (T61) are connected to one another via the third node (ND3), a seventh controllable semiconductor element (T52) and an eighth controllable semiconductor element (T62), each having a control electrode (G52, G62) and a controllable load path between two load electrodes, wherein the seventh and the eighth controllable semiconductor element (T7, T8) are connected to one another such that their respective load paths form a series circuit between the first common node (P) and the second common node (N), wherein the seventh controllable semiconductor element (T52) and the eighth controllable semiconductor element (T62) are connected to one another via the third node (ND3). [6] Semiconductor module arrangement (100) according to claim 5, wherein the first plurality of semiconductor bodies (20) comprises at least one semiconductor body (20) forming the first controllable semiconductor element (T1), at least one semiconductor body (20) forming the second controllable semiconductor element (T2), at least one semiconductor body (20) forming the third controllable semiconductor element (T3), and at least one semiconductor body (20) forming the fourth controllable semiconductor element (T4), the second plurality of semiconductor bodies (20) comprises at least one semiconductor body (20) forming the fifth controllable semiconductor element (T51) and at least one semiconductor body (20) forming the sixth controllable semiconductor element (T61), and the third plurality of semiconductor bodies (20) comprises at least one semiconductor body (20) forming the seventh controllable semiconductor element (T52) and at least one semiconductor body (20) forming the eighth controllable semiconductor element (T62). [7] Semiconductor module arrangement (100) according to one of the preceding claims, wherein the second substrate (10 21 ) and the third substrate (10 22 ) each has: a dielectric insulation layer (11) and a first metallization layer (111) arranged on a surface of the dielectric insulation layer (11), wherein the first metallization layer (111) has a first section (1111), a second section (1112), a third section (111 31 ) and a fourth section (111 32 ), wherein the second section (1112) is separated from the third section (111 31 ) and the fourth section (111 32 ) surrounds each horizontally; and first, second, third and fourth semiconductor bodies (201, 202, 203, 204) arranged on the first metallization layer (111), wherein each of the first semiconductor body (201), the second semiconductor body (202), the third semiconductor body (203) and the fourth semiconductor body (204) has a first contact pad, a second contact pad and a third contact pad, wherein the third contact pad of the first semiconductor body (201) by a first electrical connecting element (3 21 ) with the third section (111 31 ) of the first metallization layer (111) is electrically coupled, the third contact pad of the second semiconductor body (202) by a second electrical connecting element (3 22 ) with the third section (111 31 ) of the first metallization layer (111) is electrically coupled, the third contact pad of the third semiconductor body (203) by a third electrical connecting element (3 23 ) with the fourth section (111 32 ) of the first metallization layer (111) is electrically coupled, the third contact pad of the fourth semiconductor body (204) by a fourth electrical connecting element (3 24 ) with the fourth section (111 32 ) of the first metallization layer (111) is electrically coupled, and from the first, second, third and fourth electrical connecting element (3 21 , 3 22 , 3 23 , 3 24 ) each having one or more bonding wires, one or more bonding strips or a connecting bar. [8] Semiconductor module assembly (100) according to claim 7, wherein one of the following applies the first, second, third and fourth semiconductor bodies (201, 202, 203, 204) are identical to one another; or the first and second semiconductor bodies (201, 202) are identical to each other, the third and fourth semiconductor bodies (203, 204) are identical to each other, and the first and second semiconductor bodies (201, 202) differ from the third and fourth semiconductor bodies (203, 204). [9] Semiconductor module arrangement (100) according to claim 7 or 8, wherein the second substrate (10 21 ) and the third substrate (10 22 ) each further comprises: at least one on the third section (111 31 ) arranged third connection element (40 31 ), and at least one on the fourth section (111 32 ) arranged fourth connection element (40 32 ), where a fifth current path between the third contact pad of the first semiconductor body (201) and the at least one third connection element (40 31) identical voltage and current transmission properties as a sixth current path between the third contact pad of the second semiconductor body (202) and the at least one third connection element (40 31 ) offers, and a seventh current path between the third contact pad of the third semiconductor body (203) and the at least one fourth connection element (40 32 ) identical voltage and current transmission properties as an eighth current path between the third contact pad of the fourth semiconductor body (204) and the at least one fourth connection element (40 32 ) offers. [10] Semiconductor module arrangement (100) according to claim 7, 8 or 9, wherein the second substrate (10 21 ) and the third substrate (10 22 ) each further includes a fifth section (111 33 ) of the first metallization layer (11), wherein the second section (1112) comprises the fifth section (111 33 ) horizontally, where the fifth section (111 33 ) by an electrical connecting element (3) to the third section (111 31 ) is electrically coupled, the fifth section (111 33 ) by an electrical connecting element (3) to the fourth section (111 32 ) is electrically coupled. [11] Semiconductor module arrangement (100) according to claim 10, wherein the second substrate (10 21 ) and the third substrate (10 22 ) each further comprises: at least one on the fifth section (111 33 ) the first metallization layer (111) arranged fifth connection element, wherein a current path between the at least one fifth connection element and the third contact pad of the first semiconductor body (201) offers identical voltage and current transmission properties as each of a current path between the at least one fifth connection element and the third contact pad of the second semiconductor body (202), a current path between the at least one fifth connection element and the third contact pad of the third semiconductor body (203) and a current path between the at least one fifth connection element and the third contact pad of the fourth semiconductor body (204). [12] Semiconductor module arrangement (100) according to one of claims 7 to 11, wherein the first, second, third and fourth semiconductor bodies (201, 202, 203, 204) which are formed on the first metallization layer (111) of the second substrate (10 21 ) are arranged, form the fifth controllable semiconductor element (T51), and the first, second, third and fourth semiconductor bodies (201, 202, 203, 204) which are formed on the first metallization layer (111) of the third substrate (10 22 ) are arranged, form the seventh controllable semiconductor element (T52). [13] Semiconductor module arrangement (100) according to one of claims 7 to 12, wherein the second substrate (10 21 ) and the third substrate (10 22 ) each further comprises: a sixth section (1114), a seventh section (111 34 ) and an eighth section (111 35 ) of the first metallization layer (111), wherein the first section (1111) is separated from the seventh section (111 34 ) and the eighth section (111 35 ) surrounds each horizontally; and fifth, sixth, seventh and eighth semiconductor bodies (205, 206, 207, 208) arranged on the first metallization layer (111), wherein the fifth semiconductor body (205), the sixth semiconductor body (206), the seventh semiconductor body (207) and the eighth semiconductor body (208) each have a first contact pad, a second contact pad and a third contact pad, wherein the third contact pad of the fifth semiconductor body (205) by a fifth electrical connecting element (3 25 ) with the seventh section (111 34 ) of the first metallization layer (111) is electrically coupled, the third contact pad of the sixth semiconductor body (206) by a sixth electrical connecting element (3 26 ) with the seventh section (111 34 ) of the first metallization layer (111) is electrically coupled, the third contact pad of the seventh semiconductor body (207) by a seventh electrical connecting element (3 27 ) with the eighth section (111 35 ) of the first metallization layer (111) is electrically coupled, the third contact pad of the eighth semiconductor body (208) by an eighth electrical connecting element (3 28 ) with the eighth section (111 35 ) of the first metallization layer (111) is electrically coupled, from the fifth, sixth, seventh and eighth electrical connecting element (3 25 , 3 26 , 3 27 , 3 28 ) each having one or more bonding wires, one or more bonding strips or a connecting bar. [14] Semiconductor module arrangement (100) according to claim 13, wherein the second substrate (10 21 ) and the third substrate (10 22 ) each further comprises: at least one on the seventh section (111 34) arranged sixth connection element (40 34 ), and at least one on the eighth section (111 35 ) arranged seventh connection element (40 35 ), where a ninth current path between the third contact pad of the fifth semiconductor body (205) and the at least one sixth connection element (40 34 ) identical voltage and current transmission properties as a tenth current path between the third contact pad of the sixth semiconductor body (206) and the at least one sixth connection element (40 34 ) offers, and an eleventh current path between the third contact pad of the seventh semiconductor body (207) and the at least one seventh connection element (40 35 ) identical voltage and current transmission properties as a twelfth current path between the third contact pad of the eighth semiconductor body (208) and the at least one seventh connection element (40 35 ) offers. [15] Semiconductor module arrangement (100) according to one of the preceding claims, wherein at least one of the following applies: the first plurality of semiconductor bodies (20) is arranged on the first substrate (101) symmetrically about a first axis of symmetry (S1); and the second plurality of semiconductor bodies (20) is on the second substrate (10 21 ) arranged symmetrically about a second axis of symmetry (S2) and the third plurality of semiconductor bodies (20) is on the third substrate (10 22 ) arranged symmetrically around a third axis of symmetry (S3). [16] Semiconductor module arrangement (100) according to claim 15, wherein the first, second and third axes of symmetry (S 1, S2, S3) are parallel to each other. [17] Semiconductor module arrangement comprising: a first semiconductor module arrangement (100) according to one of claims 1 to 16; and an identical second semiconductor module arrangement (100) according to one of claims 1 to 16, wherein the first semiconductor module arrangement (100) and the second semiconductor module arrangement (100) are arranged side by side in a plane and symmetrically about a fourth axis of symmetry (S4). [18] Semiconductor module arrangement according to claim 17, wherein the first semiconductor module arrangement (100) and the second semiconductor module arrangement (100) are electrically coupled in parallel to each other.

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