Transistor and method for producing such a transistor

Abstract

The invention relates to a transistor comprising a top side with V-shaped trenches, wherein the V-shaped trenches arranged on the inside are at least partially conductive, characterized in that the V-shaped trenches arranged on the outside are at least partially non-conductive. Furthermore, the invention relates to methods for producing such a transistor.

Description

State of the art

[0001] The invention relates to a transistor and a method for producing such a transistor.

[0002] Transistors made of the semiconductor gallium nitride (GaN) offer the possibility of realizing components with low on-resistances and simultaneously high breakdown voltages.

[0003] One possible design of a GaN transistor is the so-called V-shaped gate high electron mobility transistor (VHEMT) or the trench current aperture vertical electron transistor (CAVET).

[0004] State-of-the-art transistors typically consist of a highly doped, conductive current spreading layer made of gallium nitride (GaN), above which a lightly n-doped GaN drift layer is applied. Above the lightly n-doped GaN drift layer is a p-doped GaN layer, and above that, an insulating aluminum gallium nitride (AlGaN) or GaN layer. The p-doped GaN layer and the insulating GaN or AlGaN layer are pierced by V-shaped trenches, over which extend an undoped GaN layer and an AlGaN layer. At the interface between the undoped GaN layer and the AlGaN layer, a two-dimensional electron gas (2DEG) forms in the region of the undoped GaN layer. A p-doped GaN layer is optionally incorporated into the V-shaped trenches to ensure normally-off operation of the component. A gate electrode contacts the p-doped GaN layer.A source contact is connected to the 2DEG. Furthermore, a source contact region can be provided, which additionally contacts the 2DEG from the side. In this case, the lower part of the source contact can also be designed as a p-contact, through which the p-layer is connected.

[0005] Without applying a gate voltage, such transistors are normally off because the 2DEG beneath the p-doped GaN layer is depleted. Applying a positive voltage to the gate electrode fills the entire 2DEG with electrons, and the electrons flow from the source contact across the trench sidewall to the trench bottom, and from there further down through the GaN drift layer and the current spreading layer into a drain electrode, which is typically located on the backside of the substrate.

[0006] Such or similar transistor structures are known, for example, from US 10,050,138 B2, US 7,592,647 B2 and US 8,729,562 B2.

[0007] The threshold voltage of the VHEMTs depends significantly on the flank angle of the V-shaped trenches, as this influences the polarization charge at the GaN-AlGaN interface.

[0008] The trenches are patterned using a dry-chemical process. The flank angle of the outermost trench in a pattern field typically differs from the flank angle of the other trenches due to the process. In the transistor, this angular deviation causes a shift in the threshold voltage in the region of the outer trenches. This results in an inhomogeneous current flow in the component, which in turn poses a problem for the reliability and performance of the transistor.

[0009] The choice of flank angle is a trade-off between the highest possible charge carrier density and the highest possible threshold voltage. For the former, shallow angles are advantageous, while for the latter, steep angles are preferable. Therefore, an angle close to 45 degrees is typically used. The inclined etching flanks are achieved using a masking layer with beveled edges, which is partially consumed during the etching process, creating an inclined structure of the GaN material. One suitable approach for this is to use a resist mask whose edges are rounded by thermal reflow. Following structuring of the resist mask using photolithography, the edges are rounded by thermal reflow. The shape of the edges depends on the width of the resist lands between the future trenches, which is why the outer edge of the surrounding resist layer deviates from the edges within the structure field.During a dry etching step, the mask is partially consumed, resulting in the formation of sloped flanks in the GaN material. The flank angle of the outer trench(es) differs from the flank angle within the structure field, i.e., the inner trenches.

[0010] The object of the present invention is to overcome the disadvantages described above. Disclosure of the invention

[0011] This object is achieved according to the invention by the transistor having the features of patent claim 1, the method having the features of patent claim 8 and the method having the features of patent claim 11.

[0012] According to the invention, a transistor is therefore provided which comprises a top side with V-shaped trenches. A conductive transistor channel which can be controlled by a control electrode is formed at least partially along V-shaped trenches arranged on the inside, i.e. along trenches which are surrounded laterally, in particular on all sides and / or on two opposite sides, by further trenches. The V-shaped trenches arranged on the inside are therefore at least partially conductive or have a conductive region. V-shaped trenches arranged on the outside, i.e. trenches which are not adjoined by another trench on at least one side, are at least partially non-conductive, i.e. in such a way that they prevent a current flow. The V-shaped trenches arranged on the outside are therefore at least partially free of a conductive transistor channel which can be controlled by a control electrode.

[0013] The core of the invention is therefore to design a transistor with V-shaped trenches such that the externally arranged V-shaped trenches, or at least their outer flanks, do not contribute to the current flow. This means that the transistor according to the invention consists of a plurality of identical, lined-up unit cells, each having a V-shaped trench. At least the outermost unit cells differ from the inner unit cells in that they do not contribute to the current flow or only contribute in one, particularly inner, sub-region. Thus, they form a conductive transistor channel controllable by a control electrode at most in an inner sub-region.

[0014] This prevents process-related deviations in the flank angle of the externally arranged V-shaped trenches from negatively affecting the electrical properties of the transistor. Furthermore, the transistor according to the invention enables the externally arranged V-shaped trenches to be used as part of an edge termination strategy.

[0015] For example, the conductive transistor channel, which can be controlled by a control electrode, forms the conductive region.

[0016] The transistor channel, for example, is a HEMT channel.

[0017] In a preferred embodiment of the transistor according to the invention, the internally arranged V-shaped trenches are completely conductive or only non-conductive at the ends and otherwise conductive.

[0018] In an exemplary embodiment of the transistor according to the invention, the externally arranged V-shaped trenches are completely non-conductive or only an outer flank of each of the externally arranged V-shaped trenches is non-conductive.

[0019] The transistor is, for example, a HEMT, in particular a VHEMT.

[0020] The transistor can be a vertical transistor, i.e. have a plate-like shape.

[0021] Alternatively, the transistor can be a quasi-vertical transistor, i.e. a transistor that is contacted from above at a lateral trench.

[0022] For example, the lateral trench borders laterally on an active transistor region of the transistor.

[0023] The trench, for example, is deeply etched.

[0024] In a preferred embodiment, the transistor according to the invention comprises a substrate layer, a highly doped conductive GaN current spreading layer arranged on the substrate layer, a weakly n-doped GaN drift layer arranged on the highly doped conductive GaN current spreading layer, a p-doped GaN layer arranged on the weakly n-doped GaN drift layer and an insulating GaN or AlGaN layer arranged on the p-doped GaN layer.

[0025] The V-shaped trenches can extend through the p-doped GaN layer and the insulating GaN or AlGaN layer, in particular interrupting them.

[0026] In a preferred embodiment of the transistor according to the invention, the V-shaped trenches each extend linearly or form a closed hexagonal shape.

[0027] Furthermore, the invention relates to a method for producing the transistor described above, comprising deep etching the top side of the transistor to form the V-shaped trenches, at least partially, in particular completely, covering the externally arranged V-shaped trenches and / or end regions of the internally arranged V-shaped trenches with an amorphous protective layer, epitaxially overgrowing the top side of the transistor, in particular the internally arranged V-shaped trenches, with a, in particular low-doped or undoped, GaN layer, an insulating GaN or AlGaN layer and optionally a p-doped GaN cap layer and subsequently removing the amorphous protective layer by etching.

[0028] In a preferred embodiment of the method according to the invention, the amorphous protective layer is an oxide or a nitride layer, in particular consisting of silicon dioxide (SiO2) or silicon nitride (SiN).

[0029] In an exemplary embodiment of the method according to the invention, the amorphous protective layer is etched wet-chemically.

[0030] Furthermore, the invention relates to a further method for producing the transistor described above, comprising epitaxial overgrowth of the top side of the transistor, in particular the internally arranged V-shaped trenches, with a, in particular low-doped or undoped, GaN layer, an insulating GaN or AlGaN layer and optionally a p-doped GaN cover layer, covering the internally arranged V-shaped trenches and / or a partial region of the externally arranged V-shaped trenches with a protective layer to protect against damage, so that at least one uncovered region is created, removing at least the uppermost layer of the transistor in the uncovered region, in particular at least the insulating GaN or AlGaN layer, by means of etching or destroying the conductivity of the transistor in the uncovered region by means of ion implantation and subsequently removing the protective layer.

[0031] When covering, for example, the V-shaped trenches arranged inside are completely covered.

[0032] Alternatively, the internally arranged V-shaped trenches can be covered only in a central area, while end areas of the internally arranged V-shaped trenches adjacent to the central area remain uncovered.

[0033] The V-shaped trenches arranged on the outside can be partially covered during the covering process.

[0034] For example, inner walls of the externally arranged V-shaped trenches and / or a portion of the externally arranged V-shaped trenches which adjoin internally arranged trenches are covered during the covering.

[0035] The etching can be a dry chemical etching.

[0036] For example, inductively coupled plasma reactive ion etching (ICP RIE) is used, particularly using chlorine-containing process gases.

[0037] In an exemplary embodiment of the further method according to the invention, the protective layer comprises a lacquer, a metal and / or an amorphous material, in particular a nitride or an oxide, in particular SiO2, or is formed therefrom.

[0038] In a preferred embodiment of the further method according to the invention, nitrogen and / or argon ions are used in the ion implantation.

[0039] Further advantages emerge from the following description of embodiments and the dependent claims. Short description of the drawing

[0040] The present invention is explained in more detail below with reference to exemplary embodiments illustrated in the drawing. It shows: Fig. 1 is a plan view of a schematic representation of a first transistor according to the invention together with a source contact, source electrodes and a gate contact; Fig. 2 shows an edge region of a sectional view through the first transistor Fig. 1 in an intermediate state during production; Fig. 3 shows an edge region of a sectional view through a second transistor according to the invention in an intermediate state during manufacture; Fig. 4 shows an inner portion of a sectional view through the second transistor according to the invention in a finished state; Fig. 5 shows an edge region of a sectional view through a third transistor according to the invention in an intermediate state during manufacture; and Fig. 6 a plan view of a fourth transistor according to the invention together with source electrodes.

[0041] In the Fig. 1 and Fig. Figure 2 shows a first transistor 1 according to the invention. Transistor 1 is a GaN-based VHEMT. Transistor 1 is plate-shaped.

[0042] Source electrodes 31, which comprise a planar-grown 2DEG AlGaN-GaN layer stack, are arranged on surrounding plateaus. Furthermore, contact pads are provided for supplying a source contact 32 and a gate contact 35 (see Fig. 1).

[0043] As in Fig. As shown in Figure 2, transistor 1 has a highly doped, conductive GaN current spreading layer 11, above which a lightly n-doped GaN drift layer 12 is applied. A p-doped GaN layer 13 is located on the GaN drift layer 12, on which, in turn, an insulating GaN or AlGaN layer 14 is arranged.

[0044] The p-doped GaN layer 13 and the insulating GaN or AlGaN layer 14 are pierced by V-shaped trenches 33 and 34. The V-shaped trenches 33 and 34 extend parallel to each other. The inner V-shaped trenches 33 contribute to the current flow of the VHEMT, while the outer V-shaped trenches 34 prevent current flow.

[0045] The internally arranged V-shaped trenches 33, i.e. trenches which are laterally surrounded by further V-shaped trenches 33, 34, comprise an electrically conductive region 37, to which a non-conductive region 36 adjoins at each end in the longitudinal extension of the trench, i.e. a region which prevents a current flow.

[0046] The electrically conductive regions 37 are conductive transistor channels formed along the V-shaped trenches 33 and controllable by a control electrode.

[0047] The externally arranged V-shaped trenches 34 are not adjacent to any further V-shaped trenches 33, 34 on at least one side. The externally arranged V-shaped trenches 34 are arranged, particularly in a plan view, in an edge region of the transistor 1.

[0048] An undoped GaN layer 15 and an AlGaN layer 16 extend in a vertically inner region of the transistor 1, which comprises the electrically conductive regions 37 of the internally arranged V-shaped trenches 33. At the interface between the undoped GaN layer 15 and the AlGaN layer 16, the 2DEG forms in the region of the undoped GaN layer 15.

[0049] In the electrically conductive regions 37 of the inner trenches 33, a p-doped GaN layer can also be applied to the AlGaN layer 16 to ensure normally-off operation. The gate electrode 18 can contact the p-doped GaN layer.

[0050] The design of the non-conductive regions 36 of the internally arranged V-shaped trenches 33 corresponds to the design of the externally arranged V-shaped trenches 34.

[0051] The externally arranged V-shaped trenches 34 and the non-conductive regions 36 of the internally arranged V-shaped trenches 33 are covered with an amorphous protective layer 22 before overgrowth with the undoped GaN layer 15, the AlGaN layer 16, and optionally the p-doped GaN layer. The amorphous protective layer 22 prevents epitaxial growth in the covered regions.

[0052] Suitable amorphous protective layers 22 are, in particular, oxide and nitride layers, preferably made of SiO2 or SiN. The use of the amorphous protective layer 22 to spatially restrict epitaxial growth is known, among other things, from selective growth processes for three-dimensional GaN nanostructures (Selective Area Growth).

[0053] The amorphous protective layer 22 suppresses the nucleation of gallium and nitrogen atoms and / or enhances the desorption of atoms adsorbed on the mask surface and their lateral diffusion. As a result, no 2DEG forms in the outer V-shaped trenches 34 and the non-conductive regions 36 of the inner V-shaped trenches 33, preventing any contribution to current flow in these regions, thus rendering them non-conductive.

[0054] After applying the undoped GaN layer 15, the AlGaN layer 16, and optionally the p-doped GaN layer, the amorphous protective layer 22 is removed by etching. Wet-chemical etching is particularly suitable for this purpose.

[0055] In the Fig. 3 and Fig. 4 shows a second transistor 2 according to the invention.

[0056] The second transistor 2 essentially corresponds to the one shown in the Fig. 1 and Fig. 2. Therefore, only the distinguishing features are explained below. Regarding the further features, reference is made to the above explanations regarding the first transistor 1, whereby in the Fig. 3 and Fig. 4 elements, which correspond to elements of the first transistor 1, with the same, in the Fig. 1 and Fig. 2 are provided with the reference symbols used.

[0057] The second transistor 2 differs from the first transistor 1 in that the externally arranged V-shaped trenches 34 and the non-conductive end regions 36 of the internally arranged V-shaped trenches 33 are also overgrown with the undoped GaN layer 15 and the AlGaN layer 16, as well as optionally the p-doped GaN layer 17. Therefore, no amorphous protective layer is used during the epitaxial overgrowth in the fabrication of the second transistor 2.

[0058] After epitaxial overgrowth, the conductivity of the outer trenches 34 and the non-conductive end regions 36 of the inner trenches 33 is locally destroyed by ion implantation, resulting in damaged regions 24. No 2DEG forms in the damaged region 24.

[0059] The timing of the implantation step in the process sequence is variable. For example, implantation occurs after the completion of the gate and source contacts.

[0060] To limit damage to the semiconductor material caused by ion bombardment of the conductive region 37 of the internally arranged trenches 33, the conductive region 37 is covered with a protective mask 23 or protective layer that prevents ions from penetrating the covered region. The protective mask 23 is removed after ion implantation.

[0061] Suitable protective masks include lacquer, metal or amorphous layers, especially lacquer, nitrides or oxides, especially SiN or SiO2.

[0062] Suitable ions for damage include nitrogen or argon ions.

[0063] In the electrically conductive regions 37 of the internally arranged V-shaped trenches 33, a p-doped GaN layer 17 is deposited on the AlGaN layer 16 to ensure normally-off operation of the component. The gate electrode 18 is in contact with the p-doped GaN layer 17.

[0064] The source contact 19 contacts the 2DEG from above.

[0065] Furthermore, a source contact region 20 is optionally provided, which additionally contacts the 2DEG from the side. The lower part of the source contact region 20 is designed as a p-contact, via which the p-doped GaN layer 13 is connected.

[0066] On the back of the substrate 10 there is a drain electrode 21.

[0067] Fig. Figure 5 shows a third transistor 3 according to the invention. The third transistor 3 essentially corresponds to the transistor shown in Fig. 1 and Fig. 2. Therefore, only the distinguishing features are explained below. Regarding the further features, reference is made to the above description regarding the first transistor 1. Elements of the Fig. 5, which correspond to elements of the first transistor 1, are provided with the same reference numerals.

[0068] In order to make the externally arranged V-shaped trenches 34 and the non-conductive end regions 36 of the internally arranged V-shaped trenches 33 non-conductive, the upper semiconductor layers, in particular the (not shown) p-doped GaN layer 17, the AlGaN layer 16, the undoped GaN layer 15, the AlGaN layer 14, the p-doped GaN layer 13 and / or the GaN drift layer 12 in the region of the externally arranged V-shaped trenches 34 and in the region of the non-conductive end regions 36 of the internally arranged V-shaped trenches 33 are partially removed locally with an etching step, but at least until the AlGaN layer 16 is completely removed, so that no 2DEG forms in these regions.

[0069] Etching is carried out, for example, by dry chemical etching, in particular by reactive ion etching with inductively coupled plasma (ICP RIE), preferably using Cl-containing process gases.

[0070] In order to prevent damage to the conductive regions 37 of the inner V-shaped trenches 33 due to the etching process, these are covered with a protective mask 25 or protective layer before etching.

[0071] Possible materials for the protective mask include paints, metals or amorphous materials, especially nitrides or oxides, especially SiO2.

[0072] Etching is preferably carried out either directly after overgrowth or after processing of the source contact 19.

[0073] In Fig. 6 shows a fourth transistor 4 according to the invention.

[0074] The fourth transistor 4 essentially corresponds to the one shown in the Fig. 1 and Fig. 2. Therefore, only the distinguishing features are explained below. Regarding the further features, reference is made to the above explanations regarding the first transistor 1, where Fig. 6 elements, which correspond to elements of the first transistor 1, with the same, in the Fig. 1 and Fig. 2 are provided with the reference symbols used.

[0075] The fourth transistor 4 is different from the one in Fig. 1 in that the V-shaped trenches 33, 34 are not linear and extend parallel to each other, but each form a hexagonal shape in plan view.

[0076] The inner V-shaped trenches 33 of the fourth transistor 4 are fully conductive, while the outer V-shaped trenches 34 have a conductive region and a non-conductive region. The non-conductive regions are arranged such that they together form a non-conductive outer region of the transistor 4.

[0077] The concrete design of the non-conductive regions and the conductive regions may correspond to the embodiments shown in the preceding figures.

[0078] The embodiments described and shown in the figures are chosen only as examples. Different embodiments can be combined with one another, either completely or with regard to individual features. An embodiment can also be supplemented by features of another embodiment. Furthermore, described method steps can be repeated and performed in a different order than the one described. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 10,050,138 B2

[0006] US 7,592,647 B2

[0006] US 8,729,562 B2

[0006]

Claims

[1] Transistor comprising a top side with V-shaped trenches (33, 34), wherein a conductive transistor channel controllable by a control electrode is formed at least partially along internally arranged V-shaped trenches (33), characterized by that externally arranged V-shaped trenches (34) are at least partially non-conductive. [2] Transistor according to claim 1, characterized by that the internally arranged V-shaped trenches (33) are completely conductive or only end regions (36) thereof are non-conductive. [3] Transistor according to claim 1 or 2, characterized by that the externally arranged V-shaped trenches (34) are completely non-conductive or only their outer flanks are non-conductive. [4] Transistor according to one of claims 1 to 3, characterized bya substrate layer (10), a highly doped conductive gallium nitride current spreading layer (11), a weakly n-doped gallium nitride drift layer (12), a p-doped gallium nitride layer and / or an insulating gallium nitride or aluminum gallium nitride layer (14). [5] Transistor according to claim 4, characterized by that the V-shaped trenches (33, 34) extend through the p-doped gallium nitride layer (13) and / or through the insulating gallium nitride or aluminum gallium nitride layer (14). [6] Transistor according to one of claims 1 to 5, characterized by that the V-shaped trenches (33, 34) each extend linearly or each form a closed hexagonal shape. [7] Transistor according to one of claims 1 to 6, characterized by that the transistor (1, 2, 3) is a vertical gallium nitride transistor. [8] A method for manufacturing the transistor (1, 2, 3, 4) according to any one of claims 1 to 7, comprising the following steps: i. deep etching a top side of the transistor (1, 2, 3, 4) to form V-shaped trenches (33, 34); ii. at least partially, in particular completely, covering externally arranged V-shaped trenches (34) and / or end regions (36) of internally arranged V-shaped trenches (33) with an amorphous protective layer (22); iii. epitaxially overgrowing the top side of the transistor (1, 2, 3, 4) with a gallium nitride layer (13), and an insulating gallium nitride or aluminum gallium nitride layer (14); and iv. Removing the amorphous protective layer (22) by etching. [9] Method according to claim 8, characterized by that the amorphous protective layer (22) is an oxide or a nitride layer, in particular consists of silicon dioxide or silicon nitride. [10] Method according to claim 8 or 9, characterized bythat in step iv. wet chemical etching is carried out. [11] A method for manufacturing the transistor (1, 2, 3, 4) according to any one of claims 1 to 7, comprising the following steps: v. epitaxially overgrowing a top side of the transistor (1, 2, 3, 4) with a gallium nitride layer (13) and an insulating gallium nitride or aluminum gallium nitride layer (14); vi. at least partially, in particular completely, covering internally arranged V-shaped trenches (33) and / or a partial area, in particular inner flanks, of externally arranged V-shaped trenches (34) with a protective layer (23, 25), so that at least one uncovered area is created, vii. removing at least the uppermost layer (15, 16) in the uncovered region by etching or destroying the conductivity of the transistor (1, 2, 3, 4) in the uncovered region by ion implantation; and viii. Removal of the protective layer (23, 25). [12] Method according to claim 11, characterized by that in step iii. dry chemical etching is carried out, in particular reactive ion etching is carried out with inductively coupled plasma, in particular using chlorine-containing process gases. [13] Method according to claim 11 or 12, characterized by that the protective layer (23, 25) comprises a lacquer, a metal and / or an amorphous material, in particular a nitride and / or an oxide, in particular silicon dioxide. [14] Method according to one of claims 11 to 13, characterized by that nitrogen and / or argon ions are used in ion implantation.

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