Manufacturing process for semiconductor silicon wafers

Abstract

Method for producing a semiconductor silicon wafer comprising a silicon wafer substrate and a monocrystalline silicon epitaxial layer thereon, wherein the silicon wafer substrate is cut from a phosphorus-doped monocrystalline silicon ingot (5) drawn by the Czochralski method at a drawing speed of at least 0.5 mm / min and at most 1.0 mm / min under the influence of a magnetic field of at least 2000 G and at most 4000 G, and the silicon wafer substrate has a resistivity of at most 1.05 mΩ·cm and a solid solution oxygen concentration of 0.9 × 10 18 atoms / cm² 3 and Si-P defects, which are essentially P aggregation defects produced by forced cooling of the grown crystal with a water cooler (3) installed in the drawing furnace (2), wherein the method comprises: a step (S5) of mirror polishing a front surface of the silicon wafer substrate; a step (S7, S8, S9) of heat treatment of the silicon wafer substrate after mirror polishing, wherein in the heat treatment step the substrate is held at a constant temperature between at least 700 °C and at most 850 °C for at least 30 minutes and at most 120 minutes, wherein subsequently, after increasing the temperature, the silicon wafer substrate is held at a temperature between at least 1100 °C and at most 1250 °C for at least 30 minutes and at most 120 minutes, and wherein thereafter a period of less than 10 minutes for the silicon wafer substrate to experience temperatures between 700 °C and 450 °C during temperature cooling, wherein following the heat treatment, the furnace atmosphere is a mixed gas composed of hydrogen and argon; and after the heat treatment step (S9), a step (S11) of depositing a monocrystalline silicon epitaxial layer with a thickness of at least 1.3 µm and at most 10.0 µm.

Description

Technical field

[0001] The invention relates to a method for producing semiconductor silicon wafers, in particular a method for producing a semiconductor silicon wafer comprising a silicon wafer substrate and a monocrystalline silicon epitaxial layer formed thereon, wherein the silicon wafer substrate is doped with phosphorus P and a layer measuring 0.9 × 10 18 atoms / cm² 3 has a set concentration of oxygen in solid solution and a specific resistance set to a maximum of 1.05 mΩ·cm. Background of the technology

[0002] The specific substrate resistance of the most modern epitaxial wafers for metal-oxide-semiconductor field-effect transistor (MOSFET) power devices is at most 1.00 mΩ·cm. To further reduce the specific resistance of the substrate, the dopant concentration must be increased. Therefore, the n-type dopant species was changed from arsenic and antimony to phosphorus (P), which has a relatively low volatility and whose concentration is approximately 1 × 10⁻⁶. 20 atoms / cm² 3 amounts.

[0003] According to patent literature JP 5 845 143 B2, JP 6 477 210 B2 and JP 5 892 232 B1, the growth of an epitaxial layer with the increased dopant concentration leads to the formation of stacking defects (hereinafter also referred to as SF) in the epitaxial layer. In particular, SFs tend to occur on substrates with a resistivity of at most 1.1 mΩ·cm.

[0004] According to JP 5 845 143 B2, JP 6 477 210 B2 and JP 5 892 232 B1, the crystal defects originating from SF are presumably caused by defects resulting from phosphorus (P) and oxygen (O) clusters. Furthermore, the literature also describes techniques for suppressing crystal defects during crystal growth, subsequent heat treatment, and epitaxial growth.

[0005] In particular, phosphorus and oxygen clusters or microprecipitates are formed in a heavily phosphorus-doped silicon wafer. To then remove the natural oxide layer on the surface of the silicon wafer, the clusters are selectively etched by heat treatment in a hydrogen gas atmosphere (hereinafter referred to as hydrogen burn-in treatment). This process, caused by the etching action of hydrogen and the difference in etching rate between the outermost surface of the silicon wafer and the clusters, results in the formation of fine pits. According to patent literature, it is presumed that during the growth of an epitaxial layer on a silicon wafer in which the micropits have formed, SF6 emanating from the micropits is generated in the epitaxial layer.

[0006] JP 5 845 143 B2 discloses a method for producing a silicon epitaxial wafer, which has: a step of forming a back-surface oxide film on the back surface of a silicon wafer cut from a single-crystal ingot produced by the CZ process, one step of removing the back-surface oxide film that is present on the outer circumference of the silicon wafer, a step of argon annealing, in which the silicon wafer is heat-treated in an argon atmosphere at a temperature of at least 1200 °C and at most 1220 °C after the removal of the back surface oxide, a step of the hydrogen annealing process in which the wafer is heat-treated in a hydrogen atmosphere for at least 30 seconds and at most 300 seconds after the argon annealing step, and a step in the growth of an epitaxial layer on the surface of the silicon wafer after the hydrogen firing process.

[0007] Furthermore, JP 5 845 143 B2 describes that SF in the epitaxial layer can be prevented by the above process steps.

[0008] Similar to JP 5 845 143 B2, JP 6 477 210 B2 describes a method for producing a silicon epitaxial wafer that suppresses the occurrence of SF in the epitaxial layer. JP 5 892 232 B1 relates to a method for producing a silicon single crystal, comprising: a step of forming a straight body with a length of at most 550 mm by pulling a seed crystal after immersion in a silicon melt to which red phosphorus has been added, such that the single crystal has a resistivity of at most 0.9 mΩ·cm; and a step of forming an end section with a length of at least 100 mm and at most 140 mm at the lower end of the straight body and a step of cutting the single crystal from the doped melt in a state in which the temperature of the upper end of the straight body is at least 590 °C. According to JP 5 892 232 B1, silicon epiaxial wafers can be obtained by this process in which the formation of light spot defects (LPDs) originating from SF is suppressed.

[0009] Furthermore, JP 2019-186 449 A and JP 2019-142 733 A disclose similar techniques. JP 2019-186 449 A discloses techniques for epitaxial growth on silicon substrates, focusing on temperature control during the growth process and improving the uniformity of the doping profiles. JP 2019-142 733 A discloses techniques for controlling the growth atmosphere using hydrogen and hydrogen chloride in epitaxial growth. Patent Literature: Summary of the Invention; Technical Problem

[0010] Unfortunately, even with the single-crystal and silicon epitaxial wafer fabrication methods according to JP 5 845 143 B2, JP 6 477 210 B2, JP 5 892 232 B1, JP 2019-186 449 A, and JP 2019-142 733 A, sufficient SF reduction effects cannot be achieved to meet the requirement. In particular, the method according to JP 2019-186 449 A provides only limited information on controlling the growth properties of phosphorus-doped silicon substrates. JP 2019-142 733 A does not adequately describe the optimal growth conditions for specific substrate materials, phosphorus-doped silicon, or devices for preventing dopants diffusion. The difficulty lies in suppressing SF by reducing phosphorus and oxygen clusters (microexcretions) with a reduced concentration of oxygen in solid solution.

[0011] To solve this problem, the suppression of SF6 in an epitaxial layer was intensively investigated within the scope of the invention. The results showed that the cause of SF6 in the epitaxial layer is P-aggregation defects, i.e., Si-P defects formed from phosphorus and silicon. Furthermore, P aggregation defects (Si-P defects) were found to have an internal additional Si plane (SF) therein (see SENDA, Takeshi [et al.]: Atomic structures of grown-in Si-P defects in red-phosphorus heavily doped CZ-Si crystals. In: 29th International Conference on Defects in Seminconductors, July 31-August 4, 2017, Matsue, Japan and SENDA, Takeshi [et al.]: Atomic structures of grown-in Si-P defects in red-phosphorus heavily doped CZ-Si crystals. In: The 78th JSAP Autumn Meeting, September 5-8, 2017, Fukuoka. Tokyo: Kōeki Shadan Hōjin Ōyō Butsuri Gakkai, 2017. Article No. 7p-PB6-5, p.13-244), which leads to crystal stress in the substrate surface prior to deposition of the epitaxial layer and causes SF to propagate in the epitaxial layer (epi-layer) upon subsequent deposition of the epitaxial layer.

[0012] According to the literature SENDA, Takeshi [et al.]: Atomic structures of grown-in Si-P defects in red-phosphorus heavily doped CZ-Si crystals. In: 29th International Conference on Defects in Semiconductors, July 31-August 4, 2017, Matsue, Japan and SENDA, Takeshi [et al.]: Atomic structures of grown-in Si-P defects in red-phosphorus heavily doped CZ-Si crystals. In: The 78th JSAP Autumn Meeting, September 5-8, 2017, Fukuoka. Tokyo : Kōeki Shadan Hōjin Ōyō Butsuri Gakkai, 2017. Article No. 7p-PB6-5, pp. 13-244, the Si-P defects are plate-like defects that contain silicon and a few atomic percent phosphorus. Phosphorus atoms are not located at the atomic site, but interstitially, and excess silicon (extrinsic SF) atoms are also present.

[0013] The phosphorus concentration, estimated based on the specific resistance around the defects, is approximately 0.2 atomic percent; the phosphorus aggregates locally, and crystal stresses are present.

[0014] Within the scope of the invention, it was found that the growth of SF6 or its size depends on the exposure or "experience" time at low temperature during the pulling of the silicon single crystal. This means that it is difficult to suppress SF6 originating from P-aggregation defects (Si-P defects) using the technique taught in JP 5 845 143 B2, JP 6 477 210 B2, and JP 5 892 232 B1. Furthermore, it was found that optimization is necessary for all processes, including crystal growth, heat treatment, and the growth of epitaxial layers, among others. This led to the invention.

[0015] The invention aims to provide a manufacturing process for silicon wafers that suppresses the generation of P aggregation defects (Si-P defects) and the occurrence of SF in the epitaxial layers. Problem solving

[0016] A method for producing a semiconductor silicon wafer, comprising a silicon wafer substrate and a monocrystalline silicon epitaxial layer thereon, wherein the silicon wafer substrate is cut from a phosphorus-doped monocrystalline silicon ingot drawn by the Czochralski method at a drawing speed of at least 0.5 mm / min and at most 1.0 mm / min under the influence of a magnetic field of at least 2000 G and at most 4000 G, and the silicon substrate has a resistivity of at most 1.05 mΩ·cm and a solid solution oxygen concentration of 0.9 × 10 18 atoms / cm² 3 and exhibits Si-P defects, which are essentially P aggregation defects produced by forced cooling of the grown crystal with a water cooler built into the drawing furnace, indicates: a step of mirror polishing a front surface of the silicon wafer substrate, a step of heat treatment of the silicon wafer substrate after mirror polishing, wherein in the heat treatment step the substrate is held at a constant temperature between at least 700 °C and at most 850 °C for at least 30 minutes and at most 120 minutes, subsequently, after increasing the temperature, the silicon wafer substrate is held at a temperature between at least 1100 °C and at most 1250 °C for at least 30 minutes and at most 120 minutes, and thereafter a period of less than 10 minutes for the silicon wafer substrate to experience temperatures between 700 °C and 450 °C during temperature cooling, wherein, following the heat treatment, the furnace atmosphere is a mixed gas composed of hydrogen H2 and argon Ar.and after the heat treatment step a step of depositing a monocrystalline silicon epitaxial layer with a thickness of at least 1.3 µm and at most 10.0 µm.

[0017] This allows the generation of SF in the epitaxial layer to be suppressed using the inventive method for semiconductor silicon wafers, since P aggregation defects (Si-P defects) can be suppressed in the crystal growth and heat treatment process.

[0018] The silicon wafer substrate for the invention is doped with phosphorus and adjusted to have a specific resistance of 1.05 mΩ·cm and a solid solution oxygen concentration of 0.9 × 10 18 atoms / cm² 3 exhibits.

[0019] In the substrate manufacturing process, the silicon ingot is drawn at a speed of at least 0.5 mm / min and at most 1.0 mm / min under the influence of a magnetic field of at least 2000 G and at most 4000 G. Forced cooling of the grown crystal with a water cooler integrated within the furnace enables the production of substrates in which the size and density increases of p-aggregation defects (Si-P defects) are suppressed. This manufacturing condition aims to shorten the cycle time in the temperature range between 600 °C and 700 °C, as this temperature range is the one that accelerates the growth of Si-P defects during crystal growth.

[0020] The substrate produced in this way is held at a constant temperature between at least 700 °C and at most 850 °C for at least 30 minutes and at most 120 minutes. During thermal processing at a temperature of at least 700 °C, impurities, moisture, and oxygen desorb from the silicon oxide layer formed on the back of the wafer.

[0021] The surface of the silicon wafer substrate is prone to reaction when thermally processed at a temperature of at least 850 °C. Therefore, thermal processing at a temperature of at least 850 °C degrades the surface roughness of the wafer due to impurities that are desorbed from the silicon oxide layer.

[0022] The invention suppresses the impairment of surface roughness caused by the desorption of impurities from the silicon oxide film by holding the wafers at a temperature of at least 700 °C and at most 850 °C for a fixed period of time. Since surface roughness increases at a treatment temperature of at least 850 °C, the problem of impaired surface roughness is circumvented by sufficiently densifying the silicon oxide film at a temperature of at least 700 °C and at most 850 °C and allowing the desorbed gas to be evacuated from the furnace; this avoids the roughening problem. The procedure promotes the decomposition of phosphorus in the Si-P defects and diffusion, producing the effects of contraction and density reduction of the Si-P defects. The holding time in this temperature range is at least 30 minutes and at most 120 minutes.

[0023] A holding time of less than 30 minutes is not desirable because the compaction of the silicon oxide film is insufficient, and a holding time of more than 120 minutes is not desirable because productivity decreases.

[0024] After the silicon substrates have been held at a fixed temperature between at least 700 °C and at most 850 °C for at least 30 minutes and at most 120 minutes, the temperature is subsequently increased, and the substrates are held at a fixed temperature between at least 1100 °C and at most 1250 °C for at least 30 minutes and at most 120 minutes.

[0025] Maintaining the substrate at a temperature between at least 1100 °C and at most 1250 °C serves to reduce stresses resulting from Si-P defects, and this reduction of stresses suppresses the generation of SF during the deposition of an epitaxial layer.

[0026] Furthermore, the temperature of the substrates is then lowered so that the duration during which the wafers are exposed to a temperature range of 700 °C to 450 °C is less than 10 minutes. This short temperature range cycle time of 700 °C to 450 °C makes it possible to suppress the generation of P aggregation defects and Si-P defects.

[0027] A series of heat treatments on the substrates, as described above, is carried out in a furnace atmosphere consisting of a mixed gas composed of H₂ and Ar gas. Since the silicon wafers are heat-treated in this hydrogen-argon mixture, the elimination of Si-P defects is advantageously promoted.

[0028] Following heat treatment, a monocrystalline silicon epitaxial layer with a thickness of at least 1.3 µm and at most 10.0 µm is formed. The thickness of the epitaxial layer is a typical value; that is, a monocrystalline silicon epitaxial layer below 1.3 µm cannot withstand the electrical voltage applied during the device manufacturing process, and a layer with a thickness above 10.0 µm increases costs undesirably.

[0029] As previously described, in the invention Si-P defects can be suppressed in the epitaxial layer by suppressing P aggregation defects in the crystal growth and heat treatment processes.

[0030] It is desirable that the maximum side length of Si-P defects be below 100 nm and the defect density below 1 × 10 12 / cm 3If the maximum side length is 100 nm or more, Si-P defects appear as SF (light spot defects; LPD) after the deposition of the epitaxial layer. Since the density of Si-P defects is at least 1 × 10 12 / cm 3 Numerous SF(LPD) remain, which impairs the electrical characteristics in the component processes; furthermore, this is undesirable.

[0031] It is desirable that the atmosphere in the furnace for heat treatments, within a temperature range of at least 700 °C to a maximum of 850 °C, be a dilute argon gas containing hydrogen, with a partial pressure in the range of 50% to 80%, and that at a higher temperature of at least 850 °C, the atmosphere be a dilute argon gas containing hydrogen, with a partial pressure in the range of 0.01% to 20%. The reason for this is to promote the densification of the silicon oxide film by hydrogen and to suppress its physical etching.The reason why, furthermore, the atmosphere at a higher temperature of at least 850 °C is a dilute argon gas with hydrogen, whose partial pressure is in the range of 0.01% to 20%, is to promote the elimination of Si-P defects and to suppress the physical etching of the silicon oxide film by hydrogen, similar to before.

[0032] Prior to the deposition of an epitaxial layer, a surface cleaning step is performed on a substrate, whereby it is desirable that surface silicon is removed to a depth of at least 50 nm and at most 150 nm by etching with a mixed gas of hydrogen (H2), hydrogen chloride (HCl) and Si-H-Cl gas.

[0033] By performing this cleaning step, SF6 levels can be further reduced after the epitaxial layer has grown. Defect removal using hydrogen chloride (HCl) is effective, and defect removal using a mixed gas of hydrogen (H2) and hydrogen chloride (HCl) is desirable. Since defect removal is carried out with a mixed gas of hydrogen (H2), hydrogen chloride (HCl), and silicon chloride (Si-HCl), the partial pressure of hydrogen chloride (HCl) is initially maintained at a specific value in the hydrogen chloride mixture. Subsequently, by reducing the partial pressure of hydrogen chloride (HCl), the surface shape of the substrate is reconstructed during hydrogen firing. Afterward, silicon chloride (Si-HCl) gas can be introduced while the partial pressure of hydrogen chloride (HCl) is reduced.

[0034] Since the residual depth of the defects is approximately 100 nm, an etching depth of surface silicon in a range of at least 50 nm and at most 150 nm is suitable, taking productivity into account.

[0035] Preferably, the silicon epitaxial layer is deposited at a deposition temperature of at least 1100 °C and at most 1150 °C with a growth rate of at least 3.5 µm / min and at most 6.0 µm / min.

[0036] Preferably, an oxide film removal step is included in which a surface oxide film is removed from the mirror-polished wafer before heat treatment in an acidic solution or acidic atmosphere. The inclusion of this oxide film removal step is desirable because the removal of the natural surface oxide film is necessary not only for cleaning the silicon wafer surface but also for eliminating Si-P defects.

[0037] It is desirable that the cutting angle of substrates prior to mirror polishing lies within a range of at least 0.1 degrees and at most 0.4 degrees relative to the orientation of the primary plane. The cutting angle of the substrates influences the growth and removal of SF during epitaxial layer deposition. By adjusting the cutting angle within this range, the SF can be removed during epitaxial layer growth. Advantageous effects of the invention

[0038] The method according to the invention aims to provide a manufacturing process for silicon wafers by which P aggregation defects (P-Si defects) are suppressed and SF is suppressed in the epitaxial layer. Brief description of the drawings Fig. Figure 1 shows a flowchart of an embodiment of a manufacturing process according to the invention for silicon wafers; Fig. Figure 2 shows a continuation of the schedule in Fig. 1 of an embodiment of a manufacturing process according to the invention for silicon wafers; Fig. Figure 3 is a diagram showing the dependence of LPD on the silicon deposition temperature and the growth rate; Fig. Figure 4 is a diagram of the relationship between Si-P defects and drawing speed; Fig. Figure 5 is a diagram showing the relationship between the number of LPDs and the amount of silicon removed; Fig. Figure 6 is a diagram showing the relationship between the number of LPDs and the holding time at a temperature of 650 °C to 900 °C; Fig. Figure 7 is a diagram of the relationship between the number of LPDs and the holding time in heat treatments at temperatures from 1050 °C to 1270 °C; Fig. Figure 8 is a diagram of the relationship between the number of LPDs and the experience time at 700 °C to 450 °C during withdrawal; and Fig. Figure 9 is a schematic representation of the construction of a drawing device equipped with a water cooler. Description of the embodiments

[0039] The following describes embodiments of a manufacturing process according to the invention for semiconductor silicon wafers based on Fig. 1, Fig. 2 and Fig. 9 described. The embodiment shown below is an example, and the invention is not limited to this embodiment.

[0040] According to Fig. 1. Silicon single-crystal ingots are produced by pulling single crystals using the Czochralski method (step 1). In the growth process of a single crystal, the silicon single crystal is doped with phosphorus (P) and pulled at a pulling speed of at least 0.5 mm / min and at most 1.0 mm / min under the influence of a magnetic field of at least 2000 G and at most 4000 G.

[0041] The reason the drawing speed is fixed in this range is as follows: To suppress the occurrence of constitutional undercooling, in which low-resistance crystals grow in a cellular form, the ratio G / V should be large, where G is the temperature curve of the melt and V is the drawing speed. That is, reducing the drawing speed V suppresses constitutional undercooling. However, reducing the drawing speed increases the transit time below 700 °C (in the temperature range of 600 °C to 700 °C), and phosphorus aggregate defects (Si-P defects) cannot be suppressed.For this reason, the temperature curve G is increased, and the constitutional undercooling phenomenon as well as the generation of P aggregation defects (Si-P defects) are suppressed by "forced cooling of the crystal with the water cooler provided in the drawing furnace, setting a drawing speed of at least 0.5 mm / min and at most 1.0 mm / min and applying a magnetic field of at least 2000 G and at most 4000 G".

[0042] Since P-aggregation defects (Si-P defects) in particular cannot be prevented with a drawing speed below 0.5 mm / min and the constitutional undercooling phenomenon cannot be suppressed with a drawing speed above 1.0 mm / min, this is not desirable.

[0043] The grown crystal is forced-cooled by the water cooler provided in the drawing furnace. For example, according to Fig. 9 a grown silicon single crystal 5 is forcibly cooled by means of the water cooler, which is arranged in the space between the upper area of ​​the drawing furnace 2 and a radiation shield 4 in the drawing device 1, thereby shortening the residence time in a temperature range of at least 600 °C to at most 700 °C. Fig. Reference 6 denotes a quartz glass crucible, reference 7 a heater, reference 8 a unit for applying a magnetic field, and reference 9 a wire for growing a silicon single crystal 5. Thus, the grown silicon single crystal is forced-cooled to a temperature below 600 °C using the water cooler. P-aggregation defects (Si-P defects) are suppressed by shortening the wafer's exposure time within a temperature range of 600 °C to 700 °C, which Fig. 4 shows.

[0044] Substrates are prepared by cutting a silicon single crystal with a cutting angle in the range of 0.1 to 0.4 degrees relative to the orientation of the primary plane (step 2). The cutting angle of the substrates influences the growth and elimination of SF during epitaxial layer deposition. The orientation of the primary plane is Si(100), and the cutting angle is in the range of 0.1 to 0.4 degrees. A silicon step terrace, which would provide a pathway for the movement of silicon atoms during epitaxial layer formation to eliminate SF defects, is formed by setting the cutting angle to a range of 0.1 to 0.4 degrees. As a result of the formation of the silicon step width, silicon atoms can move along the step width. This movement can relieve the stresses on the silicon atoms and eliminate the SF.

[0045] Substrates produced in this way have a specific resistance of at most 1.05 mΩ·cm and a concentration of dissolved oxygen of at most 0.9 × 10 18 atoms / cm² 3 and contain Si-P defects, which are essentially defects formed by aggregation of phosphorus in the crystal (step S3).

[0046] Substrates required in the technical field have a specific resistance of at most 1.05 mΩ·cm and a concentration of dissolved oxygen of at most 0.9 × 10 18 atoms / cm² 3Si-P crystal defects are suppressed by the previously described procedure for substrates (steps S1 and S2), but Si-P crystal defects still remain; the substrates contain Si-P crystal defects. The aforementioned values ​​for resistivity and dissolved oxygen concentration can be achieved by adjusting the dopant concentration, drawing speed, and magnetic field strength. The dopant concentration, drawing speed, and magnetic field strength can be varied to obtain the predetermined resistivity and dissolved oxygen concentration.

[0047] The Si-P defects of the substrates prepared in this way advantageously have a maximum side length of less than 100 nm, and the concentration of defects is less than at least 1 × 10 12 / cm 3If the maximum side length of the Si-P defects is 100 nm or more, Si-P defects appear as SF (LPD) after the formation of the epitaxial layer. If the density of the Si-P defects is 1 × 10 12 / cm 3 or more, SF (LPD) also remain. Therefore, it is desirable that the maximum side length of the Si-P defects be below 100 nm and the density of the Si-P defects be below 1 × 10 12 / cm 3 lying down and thus the crystal growth is carried out advantageously.

[0048] Next, a silicon oxide film is formed on the back surface of the substrate (step S4). For MOSFET power devices, a silicon oxide film is generally formed on the back surface of the wafer by low-temperature CVD at a temperature below, for example, 500 °C. The oxide film on the back surface is intended to prevent self-doping during the growth of the epitaxial layer. Typically, the oxide film, with a thickness of 300 nm to 800 nm, is formed in a reduced-pressure atmosphere within a temperature range of 400 °C to 500 °C.

[0049] The front surface of the substrate is then mirror-polished (step S5). Generally, mirror polishing is performed mechanically with a polishing pad and chemically with a slurry. Mirror polishing does not directly reduce Si-P defects. However, by further reducing the surface roughness through mirror polishing, Si-P defects can be easily eliminated by subsequent heat treatment.

[0050] Next, according to Fig. 2. The surface oxide film of the substrate, whose front surface is mirror-polished, is removed with an acidic solution or an acidic atmosphere (step S6). It is desirable that the oxide film removal step be included, as it is necessary to remove the natural surface oxide film not only to clean the Si surface but also to eliminate Si-P defects. In the case of removal with a chemical solution, for example, the chemical solution to be used is hydrogen fluoride (HF), the HF concentration diluted with purified water being 0.1% to 0.5%, and the processing time preferably being 30 to 120 seconds.

[0051] Then according to Fig. 2. The substrate is heat-treated at a constant temperature of at least 700 °C and below 850 °C, which is maintained for at least 30 minutes or at most 120 minutes (step S7).

[0052] The silicon oxide film is densified at a temperature of at least approximately 700 °C, causing impurities, moisture, and oxygen to desorb from the silicon oxide film. The surface of the silicon substrate is reactive at temperatures of 850 °C or above, and if the previously described desorption occurs at temperatures of 850 °C or higher, the surface roughness of the silicon wafer substrate increases. At temperatures of at least 700 °C and at most 850 °C, decomposition and diffusion of aggregated phosphorus in Si-P defects are promoted, but the increase in Si-P defects and density does not occur because the temperature range is low.

[0053] By adjusting the temperature of the desorption reaction to a temperature range, i.e. a constant temperature of at least 700 °C and at most 850 °C, impurities, moisture and oxygen can be diffused out of the silicon oxide film, and an increase in the surface roughness of the wafers can also be prevented.

[0054] Furthermore, the holding time in the aforementioned temperature range is at least 30 minutes and at most 120 minutes. Since diffusion is not accelerated if the holding time is less than 30 minutes, and productivity decreases above 120 minutes, this is not preferred.

[0055] Furthermore, the furnace atmosphere during heat treatment is a mixed gas of hydrogen and argon. The reason for using a dilute argon gas with hydrogen at a partial pressure of 50% to 80% is to accelerate the densification of the silicon oxide film by hydrogen and to prevent physical etching of the silicon oxide film by hydrogen.

[0056] After the temperature increase, the substrates are then held at a constant temperature of at least 1100 °C and at most 1250 °C for at least 30 minutes and at most 120 minutes (step S8). The heat treatment atmosphere is also a mixed gas of hydrogen and argon, similar to that used in step 7.

[0057] By keeping the substrates at a constant temperature of at least 1100 °C to at most 1250 °C for at least 30 minutes to at most 120 minutes, stresses resulting from Si-P defects can be eliminated, which is why SF defects in the epitaxial layer are also suppressed.

[0058] Since Si-P defects cannot be degraded if they are held at a temperature below 1100 °C or for less than 30 minutes in the aforementioned temperature range, and substrates deform if they are held at a temperature above 1250 °C or for 120 minutes or longer in the aforementioned temperature range, this is not preferred.

[0059] Subsequently, the temperature of the wafers is lowered so that the experience time of the temperatures of the wafers experiencing below 700 °C to at least 450 °C is less than 10 minutes (step S9).

[0060] This allows P-aggregation defects, or Si-P defects, to be suppressed by reducing the throughput time of the temperature range below 700 °C to at least 450 °C.

[0061] With regard to the furnace atmosphere of the heat treatment, which consists of a mixed gas of hydrogen and argon, the hydrogen partial pressure in the dilute argon gas is preferably set to 80% to 50% when the temperature is in a range of at least 700°C to below 850°C, and the hydrogen partial pressure in the dilute argon gas is preferably set to 0.01% to 20% when the temperature is below 700°C or at least 850°C.

[0062] The reason why the hydrogen partial pressure of the dilute argon gas is set to 80% to 50% at a temperature of at least 700°C to below 850°C is to accelerate the densification of the silicon oxide film by hydrogen and to suppress physical etching of the silicon oxide film by hydrogen. Subsequently, the reason why the hydrogen partial pressure of the dilute argon gas is set to 0.01% to 20% at a temperature of at least 850°C is to accelerate the densification of the silicon oxide film by hydrogen and to suppress physical etching of the silicon oxide film by hydrogen.

[0063] A surface cleaning treatment is performed on the substrates prior to the formation of the epitaxial layer (step S10). In this treatment, the surface of the silicon substrate is etched to a depth of at least 50 nm and at most 150 nm using a mixed gas of hydrogen (H₂), hydrogen chloride (HCl), and Si-H-Cl. This cleaning treatment physically reduces stresses in Si-P defects and further reduces SF₆ after epitaxial layer formation. Removing defects with hydrogen chloride (HCl) is effective, and removing defects with a mixed gas of hydrogen (H₂) and hydrogen chloride (HCl) is desirable.

[0064] The depth of the residual defects is at most about 100 nm, which is why the removal depth of the silicon surface by etching is suitable in a range of about 50 nm to 150 nm, taking productivity into account.

[0065] The surface cleaning treatment is carried out in a mixed gas of hydrogen (H₂), hydrogen chloride (HCl), and Si-HCl. Initially, the partial pressure of hydrogen chloride (HCl) is adjusted to a specific value in this hydrogen-hydrogen mixture. The surface shape is then reconstructed by curing with hydrogen after reducing the hydrogen chloride partial pressure. Following this, Si-HCl gas can be introduced while varying the hydrogen chloride partial pressure.

[0066] Next, a monocrystalline silicon epitaxial layer with a thickness of at least 1.3 µm and at most 10.0 µm is deposited. Silicon deposition takes place at a temperature of at least 1100 °C and at most 1150 °C and at a deposition rate of at least 3.5 µm / min and at most 6.0 µm / min (step S11).

[0067] It was found that there are suitable combinations of growth rate and temperature for the growth of the monocrystalline silicon epitaxial layer.

[0068] According to Fig. 3. It was found that light spot defects (LPD) are suppressed by setting the silicon deposition temperature to at least 1100 °C and at most 1150 °C and the deposition rate to at least 3.5 µm / min and at most 6.0 µm / min.

[0069] The reason why the epitaxial layer is deposited in a thickness range of at least 1.3 µm to at most 10.0 µm is that the monocrystalline silicon epitaxial layer with a thickness below 1.3 µm cannot withstand any breakdown voltage in device operation, and an epitaxial layer thickness above 10 µm can cause an increase in the cost of epitaxial wafers.

[0070] A silicon layer is grown by moving silicon atoms across the steps of the silicon surface. This process suppresses the formation of SF6, as the movement of silicon atoms corrects disturbances in the arrangement of silicon atoms caused by Si-P defects.

[0071] To achieve both the Si layer deposition and this correction, a condition is required that the deposition temperature of the Si layer is at least 1100 °C and at most 1150 °C, and the deposition rate is at least 3.5 µm / min and at most 6.0 µm / min. Designs

[0072] The invention is described in detail below on the basis of examples and comparative examples, but the invention is not limited to the examples. Experiment 1

[0073] The dependence of the size and density of Si-P defects generated in the substrates on variations in the growing speed of silicon single crystals, variations in the magnetic field strength, and the presence of forced cooling via a water cooler was investigated. Phosphorus (P)-doped silicon single crystals were grown such that the resistivity was set to a maximum of 1.05 mΩ·cm and the concentration of oxygen in solid solution to a maximum of 0.9 × 10⁻⁶. 18 atoms / cm² 3 fraud.

[0074] During the single crystal growth process, the drawing speed was varied from 0.3 mm / min to 1.4 mm / min, and the applied magnetic field was 3000 G. Furthermore, the maximum side length and density of Si-P defects were investigated in cases where the water cooler was installed in the drawing furnace and in cases where it was not.

[0075] In Fig. Figure 4 shows the results. The size of the Si-P defects was measured using a transmission electron microscope. The density of the Si-P defects was calculated based on the area observed with the transmission electron microscope. As a result, the maximum side lengths of the Si-P defects are below 100 nm for both cases, with and without the water cooler installed.

[0076] In the case without a water cooler, the density tends to decrease with increasing drawing speed; i.e., the density is at most 1 × 10 12 / cm 3 at a drawing speed of at least approximately 0.7 mm / min. However, the reduction rate from this value is very low. In contrast, with the installation of the water cooler, the density reaches a maximum of 1 × 10 12 / cm 3This can be achieved by setting the drawing speed to at least approximately 0.5 mm / min. Even if the drawing speed is set above 1 mm / min, the density tends to decrease with increasing drawing speed. However, since the effectiveness is low and productivity decreases, the drawing speed is preferably no more than 1 mm / min. Experiment 2

[0077] The relationship between the number of LPDs and the amount of silicon removed from the substrate surface was investigated. The test method involved measuring the number of LPDs using a Surfscan SP1, manufactured by KLA-Tencor Corporation. Experiment 2 is a step in step 10 of Fig. 2. Experiment carried out to demonstrate the suppressive effect on SF (LDP) when the amount of removal of the silicon surface layer by HCl is varied prior to the deposition of an epitaxial layer.

[0078] First, a silicon oxide film was formed on the back of a substrate; the substrate has a specific resistance of at most 1.05 mQ·cm, a concentration of oxygen in solid solution of at most 0.9 × 10 18 atoms / cm² 3 and Si-P defects with a maximum side length of less than 100 nm and a defect density of less than 1 × 10 12 / cm 3 The oxide film was formed with a thickness of 500 nm at a temperature in the range of 400 °C to 450 °C.

[0079] The front surface of the substrate was then mirror-polished. The material removal rate during mirror polishing was 15 µm. The mirror-polished substrate was heat-treated in a vertical diffusion oven for 120 minutes at 800 °C and 60 minutes at 1200 °C. The oven atmosphere during heat treatment was a mixture of hydrogen (H₂) and argon (Ar) (dilute Ar gas with a hydrogen partial pressure of 60%). The substrate was exposed to temperatures ranging from 700 °C to 450 °C for 8 minutes.

[0080] A monocrystalline silicon epitaxial layer with a thickness of 4.0 µm was deposited on the substrate at a deposition rate of 4.0 µm / min at 1150 °C. The amount of material removed from the silicon surface layer with HCl prior to deposition was varied up to a maximum of 500 nm. At this point, the HCl partial pressure was 0.5%. The number of LPDs (65 nm) on the substrate was measured, and the results are presented in Fig. 5 shown. On the vertical axis in Fig. 5 represents the number of LPDs. The term LPD (65 nm) refers to the measurement of the LPDs present on the main surface with a scattering intensity corresponding to that of a particle with a standard particle size of at least 65 nm.

[0081] As from Fig. As can be seen from Figure 5, the number of LPD (65 nm) is 10,000 if silicon removal from the substrate surface is not carried out, and on the other hand, the number of LPD (65 nm) is 100 to 200 if the silicon removal depth from the substrate surface is 50 nm to 150 nm. Experiment 3

[0082] In experiment 3, according to step 7 in Fig. 2. By holding the substrates at a constant temperature of at least 700 °C and below 850 °C for a minimum of 30 minutes and a maximum of 120 minutes, the increase in wafer surface roughness is reduced. Experiments were conducted to test the suppression resulting from the reducing effect of the generated pits on the wafer surface (LPD) and to promote the elimination of Si-P defects.

[0083] A silicon oxide film was formed on the back of a substrate; the substrate has a resistivity of at most 1.05 mQ·cm, a solid solution oxygen concentration of at most 0.9 × 10 18 atoms / cm² 3 and Si-P defects with a maximum side length of less than 100 nm and a defect density of less than 1 × 10 12 / cm 3 The oxide film was formed with a thickness of 500 nm at a temperature in the range of 400 °C to 450 °C.

[0084] The front surface of the substrate was then mirror-polished. The material removal rate during mirror polishing was 15 µm. The mirror-polished substrates were heat-treated for 60 minutes at 1200 °C in a vertical diffusion oven. The oven atmosphere for the heat treatment was a mixed gas of hydrogen and argon (diluted argon gas with a hydrogen partial pressure of 1%).

[0085] During the temperature increase for the 60-minute heat treatment at 1200 °C, the substrates were held at temperatures of 650 °C, 700 °C, 800 °C, 850 °C, and 900 °C for 15 minutes, 30 minutes, 120 minutes, and 180 minutes at each temperature. The furnace atmosphere for the heat treatment was a mixed gas of hydrogen and argon (diluted argon gas with a hydrogen partial pressure of 60%).

[0086] The wafer substrate was exposed to temperatures from 700 °C to 450 °C for 8 minutes. A monocrystalline silicon epitaxial layer with a thickness of 4 µm was deposited on the wafer substrate at a deposition rate of 4.0 µm / min at 1150 °C. The amount of material removed with hydrogen chloride prior to deposition was 100 nm, and the hydrogen chloride partial pressure was 0.5%.

[0087] The testing procedure involves measuring the number of LPDs using a Surfscan SP1, manufactured by KLA-Tencor Corporation. Fig. The results are shown in section 6. Fig. Figure 6 clearly shows that the number of LPDs reaches a substantially constant value within 30 minutes. The holding time is demonstrably preferably between 30 and 120 minutes, taking productivity into account.

[0088] The reduction in the number of LPDs when held at 650 °C or 900 °C is attributed to the fact that holding the substrates at these temperatures causes impurities, moisture, and oxygen to desorb from the silicon oxide film on the back of the wafer, increasing the surface roughness of the wafer. The resulting pits remain as LPDs after epitaxial growth. Therefore, the heat treatment temperature of wafers is preferably between 700 °C and 850 °C. Experiment 4

[0089] In Experiment 4, represented as step 8 in Fig. 2. It was tested whether stresses resulting from Si-P defects could be reduced by holding the substrates at a constant temperature of 1100 °C to 1250 °C for at least 30 minutes and at most 120 minutes.

[0090] First, a silicon oxide film was formed on the back of a substrate; the substrate has a specific resistance of at most 1.05 mQ·cm, a concentration of oxygen in solid solution of at most 0.9 × 10 18 atoms / cm² 3 and Si-P defects with a maximum side length of less than 100 nm and a defect density of less than 1 × 10 12 / cm 3 The oxide film was deposited with a thickness of 500 nm at a temperature in the range of 400 °C to 450 °C. Subsequently, the front surface of the substrate was mirror-polished, and the amount of material removed by mirror polishing was 15 µm.

[0091] The substrate, whose front surface was mirror-polished, was heat-treated in a vertical oven at 1050 °C, 1100 °C, 1200 °C, 1250 °C, and 1270 °C for 15 minutes, 30 minutes, 120 minutes, and 180 minutes at each temperature. During the temperature increase prior to heat treatment at 1050 °C, 1100 °C, 1200 °C, 1250 °C, and 1270 °C, the substrate was heat-treated by holding it at 800 °C for 120 minutes.

[0092] The furnace atmosphere for heat treatment consisted of a mixed gas of hydrogen and argon (diluted argon gas with a hydrogen partial pressure of 1%). The temperature reduction time for the wafer substrate, which was subjected to temperatures from 700 °C to 450 °C, was 8 minutes.

[0093] The amount of material removed with hydrogen chloride before the deposition of the monocrystalline silicon epitaxial layer was 100 nm, the hydrogen chloride partial pressure was 0.5%, and the temperature was 1180 °C. Subsequently, a monocrystalline silicon epitaxial layer with a thickness of 4 µm was formed on the substrate at a deposition rate of 4.0 at 1150 °C.

[0094] The testing procedure involves measuring the number of LPDs using the Surfscan SP1, manufactured by KLA-Tencor Corporation. Fig. The results are shown in section 7. Fig. 7. It is noted that the number of LPDs reaches a substantially constant value every 30 minutes. It was confirmed that the holding time is preferably between 30 and 120 minutes, taking productivity into account. How Fig. Figure 7 shows that the number of LPDs decreases with increasing temperature. The temperature is preferably between 1100 °C and 1250 °C, taking into account the issues of sliding motion and productivity. Experiment 5

[0095] In experiment 5, which is step 9 in Fig. As shown in Figure 2, it was tested whether the phosphorus (P) reaggregation defects (Si-P defects) could be suppressed by reducing the throughput time to 10 minutes in a temperature range from below 700 °C to at least 450 °C.

[0096] First, a silicon oxide film was formed on the back of a substrate; the substrate has a specific resistance of at most 1.05 mQ·cm, a concentration of oxygen in solid solution of at most 0.9 × 10 18 atoms / cm² 3 and Si-P defects with a maximum side length of less than 100 nm and a defect density of less than 1 × 10 12 / cm 3The oxide film was deposited at 500 nm in a temperature range of 400 °C to 450 °C. Subsequently, the front surface of the substrate was mirror-polished, and the amount of material removed by mirror polishing was 15 µm.

[0097] The substrate, with its mirror-polished front surface, was then heat-treated for 60 minutes at 1200 °C. The furnace atmosphere during this heat treatment was a mixture of hydrogen (H₂) and argon (Ar) (dilute Ar gas with a hydrogen partial pressure of 1%). Prior to the 60-minute heat treatment at 1200 °C, the substrate was heat-treated for 120 minutes at 800 °C. During this second heat treatment, the furnace atmosphere was also a mixture of hydrogen (H₂) and argon (Ar) (dilute Ar gas with a hydrogen partial pressure of 60%).

[0098] The removal temperature after the previously described heat treatment was set to 700 °C, and the removal rate from the furnace was varied from this point onward. The temperature of the silicon wafers exposed to the ambient atmosphere was measured using thermography, and the exposure time was calculated by adding the removal time to the holding time at 700 °C. The exposure time for wafers exposed to temperatures below 700 °C down to at least 450 °C was thus varied by 3 minutes, 5 minutes, 8 minutes, 10 minutes, 12 minutes, 15 minutes, and 20 minutes.

[0099] The surface layer of the silicon substrates was ablated with hydrogen chloride prior to the deposition of a 100 nm monocrystalline silicon epitaxial layer. The hydrogen chloride partial pressure was 0.5%, and the temperature was 1180 °C. Subsequently, a 4 µm thick monocrystalline silicon epitaxial layer was formed on the substrate at 1150 °C. Fig. The results are shown in Figure 8.

[0100] According to Fig. 8 confirms that by lowering the temperature so that the experience time for wafers experiencing temperatures below 700 °C and at least 450 °C is less than 10 minutes, the number of LPDs is at most one hundred (100) and the phosphorus reaggregation defects (Si-P defects) are suppressed. Experiment 6

[0101] Experiment 6 was performed to demonstrate that phosphorus aggregation defects (Si-P defects) could be suppressed by forming an epitaxial layer with a thickness of at least 1.3 µm and at most 10.0 µm according to step 11 in Fig. 2 was deposited after the deposition of a silicon layer with a deposition rate of at least 3.5 and at most 6 at a temperature of at least 1100 °C and at most 1150 °C.

[0102] First, a silicon oxide film was formed on the back of a substrate; the substrate has a specific resistance of at most 1.05 mQ·cm, a concentration of oxygen in solid solution of at most 0.9 × 10 18 atoms / cm² 3 and Si-P defects with a maximum side length of less than 100 nm and a defect density of less than 1 × 10 12 / cm 3 The oxide film was deposited with a thickness of 500 nm at a temperature in the range of 400 °C to 450 °C.

[0103] The front surface of the substrate was then mirror-polished, removing 15 µm of material. The mirror-polished substrates were heat-treated for 60 minutes at 1200 °C in a vertical diffusion furnace. In this process, the furnace atmosphere for the heat treatment was a mixed gas of hydrogen (H₂) and argon (Ar) (dilute Ar gas with a hydrogen partial pressure of 1%).

[0104] During the temperature increase prior to the 60-minute heat treatment at 1200 °C, the substrate was heat-treated for 120 minutes at 800 °C. The atmosphere in the furnace for this heat treatment was a mixed gas of hydrogen (H₂) and argon (Ar) (dilute Ar gas with a hydrogen partial pressure of 60%). During the temperature reduction, the exposure time for the substrate to temperatures from 700 °C to 450 °C was 8 minutes.

[0105] The surface of the silicon substrates was ablated to a depth of 100 nm using hydrogen chloride prior to the epitaxial growth process at a hydrogen chloride partial pressure of 0.5% and a temperature of 1180 °C. Subsequently, silicon epitaxial layers were deposited on the substrates at temperatures of 1100 °C, 1125 °C, and 1150 °C, varying the growth rates at each temperature to 2.4 µm / min, 3.8 µm / min, 4 µm / min, 5 µm / min, and 6.4 µm / min. The number of LPDs was then measured using the Surfan SP1, manufactured by KLA-Tencor Corporation. Fig. The results are shown in section 3.

[0106] According to Fig.3. It is found that LPDs can be suppressed by setting the silicon layer deposition temperature to at least 1100 °C and at most 1150 °C, and the growth rate to at least 3.5 and at most 6. It is desirable for the silicon epitaxial layer deposition temperature to be at least 1100 °C and at most 1150 °C, since problems such as sliding motion on the substrates occur when the silicon epitaxial layer deposition temperature is 1200 °C.

Claims

[1] Method for producing a semiconductor silicon wafer comprising a silicon wafer substrate and a monocrystalline silicon epitaxial layer thereon, wherein the silicon wafer substrate is cut from a phosphorus-doped monocrystalline silicon ingot (5) drawn by the Czochralski method at a drawing speed of at least 0.5 mm / min and at most 1.0 mm / min under the influence of a magnetic field of at least 2000 G and at most 4000 G, and the silicon wafer substrate has a resistivity of at most 1.05 mΩ·cm and a solid solution oxygen concentration of 0.9 × 10 18 atoms / cm² 3 and Si-P defects, which are essentially P aggregation defects produced by forced cooling of the grown crystal with a water cooler (3) installed in the drawing furnace (2), wherein the method comprises: a step (S5) of mirror polishing a front surface of the silicon wafer substrate; a step (S7, S8, S9) of heat treatment of the silicon wafer substrate after mirror polishing, wherein in the heat treatment step the substrate is held at a constant temperature between at least 700 °C and at most 850 °C for at least 30 minutes and at most 120 minutes, wherein subsequently, after increasing the temperature, the silicon wafer substrate is held at a temperature between at least 1100 °C and at most 1250 °C for at least 30 minutes and at most 120 minutes, and wherein thereafter a period of less than 10 minutes for the silicon wafer substrate to experience temperatures between 700 °C and 450 °C during temperature cooling, wherein following the heat treatment, the furnace atmosphere is a mixed gas composed of hydrogen and argon; and after the heat treatment step (S9), a step (S11) of depositing a monocrystalline silicon epitaxial layer with a thickness of at least 1.3 µm and at most 10.0 µm. [2] Method for producing a semiconductor silicon wafer according to claim 1, wherein a maximum side length of Si-P defects in the silicon wafer substrate is less than 100 nm and the density of the defects is less than 1 × 10 12 / cm 3 lies. [3] Method for producing a semiconductor silicon wafer according to claim 1, wherein the furnace atmosphere in the heat treatment step (S7) is dilute argon gas with hydrogen having a partial pressure in the range of 50% to 80% when raising the temperature from at least 700°C to below 850°C and dilute argon gas with hydrogen having a partial pressure in the range of 0.01% to 20% at a temperature of at least 850°C. [4] Method for producing a semiconductor silicon wafer according to claim 1, further comprising a step (S10) of surface cleaning of the silicon wafer substrate prior to the step (S11) of depositing an epitaxial layer thereon, wherein, in the surface cleaning step, silicon on the substrate surface is etched to a depth of at least 50 nm to at most 150 nm with a mixed gas of hydrogen, hydrogen chloride and Si-H-Cl. [5] Method for producing a semiconductor silicon wafer according to claim 1, wherein, in step (S11) of depositing a monocrystalline silicon epitaxial layer, the epitaxial layer is deposited at a deposition temperature of at least 1100 °C and at most 1150 °C and a deposition rate of at least 3.5 and at most 6.

0. [6] Method for producing a semiconductor silicon wafer according to claim 1, further comprising a step (S6) of oxide film removal from the mirror-polished wafer substrate prior to heat treatment, in which its surface oxide film is removed with an acidic solution or an acidic atmosphere. [7] Method for producing a semiconductor silicon wafer according to claim 1, wherein a cutting angle of the silicon wafer substrate before mirror polishing is in a range of at least 0.1 degrees to at most 0.4 degrees.

Images