Protection of an integrated circuit against electrostatic discharge

Abstract

Electrostatic discharge protection means (ESDPM) comprise a first voltage limiting module (VL) having a first input terminal (BE1) electrically coupled to each first input and / or output signal pin (PDi) of an integrated circuit by a first diode mounted to be reverse biased during the operation of the integrated circuit, the first module being configured to conduct between each first pin (PDi) and a ground pin (PVss) during a positive electrostatic discharge on one of the first pins, a second voltage limiting circuit (LPCL) electrically coupled and mounted conducting in the same direction as the first module, between an external power supply pin (PVcc) and the ground pin (PVss), having an internal node (BE2) capable of delivering an internal supply voltage (IVcc) in said domain, and configured to, in the presence of a positive electrostatic discharge on the power supply pin,to be traversed by a current (CR2) lower than the current (CR1) traversing the first voltage limiting module, and a blocking diode (D21) electrically connected between said first input terminal (BE1) and the power supply pin (PVcc). Figure for abbreviation: Figure 2,

Description

Title of the invention: Protection of an integrated circuit against electrostatic discharges

[0001] The invention relates to electronic devices, and in particular those intended for the protection of an integrated circuit against electrostatic discharges (ESD: Electro-Static Discharge), for example but not limited to those intended to protect integrated circuits of non-volatile memories, in particular of the EEPROM type.

[0002] An integrated circuit may comprise - input / output pads intended to receive and / or transmit electrical signals and connected to a domain of the integrated circuit implementing a particular functionality, such as for example a non-volatile memory device of the EEPROM type, - a power supply pad intended to receive a supply voltage from which the domain can be powered, and -a ground stud.

[0003] When the integrated circuit is not in operation, it may be subjected to an electrostatic discharge which may occur between any two pads among those mentioned above.

[0004] An electrostatic discharge typically results in a very brief current pulse (typically of the order of a hundred nanoseconds) whose current peak is of the order of, for example, 2 amperes and typically occurs after 10 nanoseconds. Typically, such a current peak occurs, for example, for a pulsed potential difference of 3 kV HBM applied between two pads through an RLC equivalent circuit.

[0005] It is recalled here that the letters HBM are the abbreviation of the English acronym "Human Body Model" well known to those skilled in the art in the field of protection against electrostatic discharges and designate in particular an electrical circuit intended to model an electrostatic discharge delivered by a human being and usually used to test the sensitivity of devices to electrostatic discharges. This HBM electrical circuit, which is the equivalent RLC circuit mentioned above and to which a high voltage (for example 3 kV) is applied, comprises in particular a capacitor charged under this high voltage and which will discharge through a resistance of 1.5 kilo-ohms in the device to be tested. Thus, in the present case, an electrostatic discharge of 3 kilovolts HBM means that a potential difference of 3 kilovolts is applied to the HBM electrical circuit.

[0006] It is then appropriate that this current pulse circulates through means of protection against electrostatic discharges and not through the area of ​​the integrated circuit to be protected.

[0007] These protection means therefore aim to absorb this current pulse and to avoid overvoltages on the pads of the integrated circuit.

[0008] ESD protection takes up a lot of space on a chip, due to the need to sustain high energy without destruction.

[0009] Thus, the higher the expected level of ESD protection, the greater the surface area occupied by the ESD protection (means of protection, interconnections).

[0010] And shrinking the lithography does not contribute to reducing this surface area significantly.

[0011] Indeed, with increasingly smaller lithographies, it is the surface area of ​​the functional circuits of the integrated circuit domain(s) which decreases, and not the surface area of ​​the ESD protection.

[0012] However, ESD protection has a significant and increasing impact on the surface area of ​​the chip and on its cost.

[0013] For example, in some technologies, ESD protection can occupy nearly 5% of the chip area.

[0014] Furthermore, for memory integrated circuits, the lower the memory density, the greater the relative contribution of ESD protection to the total chip size.

[0015] Thus in certain cases, a classic ESD protection can occupy nearly 15% of the surface of the chip.

[0016] It is therefore appropriate to maximize the ESD performance / ESD protection surface ratio.

[0017] This can be achieved either by reducing the total cost of the ESD protection surface for the same given ESD performance, or by increasing the performance of the ESD protection for the same surface cost.

[0018] To try to solve this problem, ESD protections have used diodes, bipolar transistors, thyristors, MOS switches (“MOSSWI”: MOS Switch according to an acronym well known to those skilled in the art) for decades.

[0019] Bipolar protections are typically individual per pad, and connected to a common ground rail.

[0020] The MOSSWI type protections are connected between the power supply pad and the ground pad, and each input / output pad is connected by 2 diodes to the power supply pad and the ground pad respectively.

[0021] Bipolar protectors generally offer better ESD robustness per surface area than MOSSWI type protectors, due to the negative resistance in intrinsic to their current-voltage curve induced by bipolar operation (whereas MOSSWI switches are based on usual MOSFET conduction) but their threshold, related to avalanche conduction of PN diodes (typically not less than 6V) cannot be made as low as the thresholds of MOSSWIs, which makes them unsuitable for advanced technologies requiring trigger levels below 2V.

[0022] Furthermore, one NPN bipolar transistor is typically provided per pad (except for the ground pad), which takes up a lot of surface area.

[0023] As for MOSSWI type protections, such a switch often takes up more space than a bipolar NPN structure.

[0024] It is possible to share the switches for several pads by using diodes, but this can lead to preventing, when the integrated circuit is in operation, the voltage present on the input / output pads from exceeding the value of the supply voltage increased by 0.6 V (which corresponds to the threshold voltage of a diode).

[0025] However, this limitation of the voltage on the input / output pads poses a problem when several chips are connected to an FC type bus.

[0026] Indeed, if one of the chips is stopped (zero supply voltage), then the bus wires connected to the input / output pads of this chip have a voltage limited to 0.6V, which blocks the operation of the bus for the other chips because certain bus signals must have a voltage greater than 0.6V.

[0027] Finally, a MOSSWI type protection contributes unfavorably to the chip's quiescent current (Icc standby) in the presence of a significant leakage current (loff) of the NMOS transistors.

[0028] There is therefore a need for good ESD protection with maximum surface gain and the possibility of providing, during operation of the integrated circuit, a voltage on the input / output pads not limited to the supply voltage increased by the threshold voltage of a diode.

[0029] According to one embodiment, it is proposed to share a single common voltage limiting element for all the input / output, power supply and ground pads, connected between a common node and the ground pad.

[0030] Thus a surface gain is obtained and all the pads, including the power pads, share the same connection to the discharge path.

[0031] More precisely, current is injected into the voltage limiting element through a diode in direct conduction, if the pad considered receives a positive electrostatic discharge, while current is injected into a rail connected to the ground pad, if the pad considered receives a negative electrostatic discharge.

[0032] According to one embodiment, pooling is also proposed at the level diodes. In fact, it is proposed to implement a pair of diodes per input / output or power supply pad, with homologous diodes of the pairs having a common anode connected to the ground pad and the other homologous diodes of the pairs having a common cathode connected to the terminal of the voltage limiting element not connected to the ground pad.

[0033] Thus the input / output and power pads use the same ESD scheme and the diodes are much smaller than the common voltage limiting element.

[0034] Furthermore, according to one embodiment, there is a diode connected directly between the power supply pad and the input of the common voltage limiting element, which makes it possible to avoid capping, during operation, the voltage on each input / output pad at the power supply voltage increased by the threshold voltage of a diode, which is particularly useful in the case of a connection of the integrated circuit on an FC bus.

[0035] Furthermore, according to one embodiment, a second voltage limiting element is connected in series with a resistor between the power supply pad and the ground pad, and is advantageously traversed, during an electrostatic discharge, by a lower current density than that traversing the common voltage limiting element.

[0036] The input terminal of this second voltage limiting element is the power supply terminal of the integrated circuit domain and, in the presence of an electrostatic discharge between the power supply pad and the ground pad, the voltage present at this input terminal is limited to a lower level than the voltage level present on the power supply pad and induced by the common current limiting element.

[0037] The level of ESD protection is therefore improved.

[0038] According to one aspect, an integrated circuit is proposed, comprising several first signal input and / or output pads, a domain of the integrated circuit coupled to said first pads, at least one second pad intended to receive a respective first supply voltage, at least one third pad intended to be coupled to a cold supply point, for example ground.

[0039] The integrated circuit also comprises means for protecting said domain against electrostatic discharges.

[0040] These protection means comprise a first voltage limiter module having a first input terminal electrically coupled to each first pad by a first diode mounted so as to be reverse biased during operation of the integrated circuit.

[0041] This first voltage limiter module is configured so as to be mounted passing between each first pad and said at least one third pad during a positive electrostatic discharge on one of the first pads.

[0042] The protection means also comprise at least one second voltage limiter circuit (comprising for example a second voltage limiter module connected in series with a resistor) electrically coupled between said at least one second pad and said at least one third pad.

[0043] When several second voltage limiting circuits are provided, it is possible in theory to have several distinct third pads, but in practice these third pads can in this case be joined together to form a single third pad.

[0044] Each second voltage limiting circuit is configured to be mounted passing between the corresponding second pad and the corresponding third pad during a positive electrostatic discharge on this second pad.

[0045] This second voltage limiting circuit has an internal node capable of delivering a second supply voltage to said domain.

[0046] This second supply voltage is an internal supply voltage effectively supplying the domain of the integrated circuit and is lower than the first supply voltage in particular during a positive electrostatic discharge on the second pad.

[0047] During operation of the integrated circuit, these two voltages are very close and the difference is preferably as small as possible (for example of the order of a few tens of mV) so as not to disturb the operation of the integrated circuit.

[0048] This second voltage limiter circuit is further configured to, in the presence of a positive electrostatic discharge on the corresponding second pad, be crossed by a current lower than the current crossing the first voltage limiter module.

[0049] The protection means further comprise a second diode electrically coupled between said first input terminal of the first voltage limiter module and said at least one second pad, i.e. the power supply pad so as to be forward biased between said at least one second pad and the first input terminal of the first voltage limiter module during a positive discharge on the corresponding second pad.

[0050] Since the first input terminal of the first voltage limiter module is coupled to each first pad via a first diode, this second diode, which acts as a non-return diode, is also coupled to each first pad, the term "coupled" encompassing direct or indirect coupling.

[0051] As indicated above, this second diode makes it possible to avoid capping, during operation, the voltage on each input / output pad at the supply voltage increased by the threshold voltage of a diode, which is, as recalled above, particularly useful in the case of a connection of the integrated circuit to an FC bus.

[0052] According to one embodiment, the protection means comprise first pairs of first diodes connected in parallel and respectively associated with the first pads, each first pair comprising two first diodes connected in series in the same direction, the common terminal of the two first diodes being coupled to the corresponding first pad.

[0053] Furthermore, the first voltage limiter module is connected in parallel with the first pairs of diodes.

[0054] The protection means also comprise a second pair of second diodes connected in parallel with the voltage limiter circuit module, the two second diodes being connected in series in the same direction as the first diodes, the common terminal of the two second diodes being electrically coupled to said at least one second pad.

[0055] Furthermore, the second voltage limiter circuit comprises a second voltage limiter module connected in series with a resistive element, the common terminal between the resistive element and the second voltage limiter forming a second input terminal for this second voltage limiter module as well as said internal node.

[0056] Furthermore, the anodes of all the diodes having their cathode connected either to a first pad or to said at least one second pad, are electrically coupled to said at least one third pad.

[0057] According to one embodiment, the protection means comprise a first discharge rail coupled to said input terminal of the first voltage limiter module and to the cathodes of all the diodes having their anode coupled either to a first pad or to the second pad, and a second discharge rail coupled to the third pad and to the anodes of all the diodes having their cathode connected either to a first pad or to said at least one second pad.

[0058] The first voltage limiter module and said at least one second voltage limiter module may have a similar structure.

[0059] According to one embodiment, the first voltage limiter module comprises at least one first lateral bipolar transistor whose collector forms said first input terminal, whose emitter is coupled to the third pad and whose base is connected to the third pad by a first base resistor, and each second voltage limiter module comprises at least one second lateral bipolar transistor whose collector forms said second input terminal, whose emitter is coupled to the corresponding third pad and whose base is connected to the corresponding third pad by a second base resistor.

[0060] Said at least one second voltage limiter module advantageously has a surface area smaller than that of the first voltage limiter module.

[0061] In particular, the first voltage limiter module may comprise NI first transistors in parallel, NI being greater than 1 and said at least one second module voltage limiter may comprise N2 second transistors in parallel, NI being greater than N2.

[0062] Said domain of the integrated circuit may comprise, for example, a non-volatile memory circuit.

[0063] According to another aspect there is provided a method, comprising -in the presence of a positive electrostatic discharge on one of the first signal input and / or output pads coupled to a domain of the integrated circuit, a limitation of the voltage on this first pad by circulating the current resulting from this discharge through a first voltage limiter module, -in the presence of a positive electrostatic discharge on a second pad intended to receive, during operation of the integrated circuit, a first supply voltage, a limitation of the voltage on the input terminal of at least one second voltage limiter module by distributing the current resulting from this discharge into, on the one hand, a first current flowing in the first voltage limiter module and in a non-return diode coupled between the second pad, the first pad and the input of the first voltage limiter module and, on the other hand, at least one second current flowing in said at least one second voltage limiter module, said at least one second current being lower than the first current, and -during operation of the integrated circuit, a delivery to said domain of at least one second supply voltage equal to the voltage present at said input terminal of said at least one second voltage limiter module.

[0064] According to one embodiment, said at least one second current also flows in a resistive element coupled between said input terminal of the corresponding second current limiting module and the second pad.

[0065] Other advantages and characteristics of the invention will appear on examining the detailed description of modes of implementation and embodiment, which are in no way limiting, and the appended drawings in which:

[0066] [Fig.l]

[0067] [Fig.2]

[0068] [Fig.3]

[0069] [Fig.4]

[0070] [Fig.5]

[0071] [Fig.6]

[0072] [Fig.7]

[0073] [Fig.8]

[0074] [Fig.9], and

[0075] [Fig. 10]

[0076] schematically illustrate embodiments and implementations of the invention.

[0077] In [Fig. 1], the reference IC designates an integrated circuit comprising a DMN domain including here a circuit forming a non-volatile memory device of the EEPROM type having in particular a PM memory plane of CEL cells of the EEPROM type as well as processing means (not shown here for the sake of simplification) including in particular a row decoder and a column decoder.

[0078] The integrated circuit IC comprises several first signal input and / or output pads. In this exemplary embodiment and for the purposes of simplification, three first pads PDI, PD2 and PD3 are shown.

[0079] The DMN domain is connected to these first PDi plots.

[0080] The integrated circuit also comprises a second PVcc pad intended to receive a first supply voltage Vcc and a third PVss pad intended to be coupled to a cold supply point, typically ground.

[0081] The integrated circuit IC also comprises MPESD means for protecting the DMN domain against electrostatic discharges.

[0082] As will be seen in more detail below, the MPESD protection means are in particular configured to, during operation of the integrated circuit IC, deliver a second supply voltage IVcc which is an internal supply voltage, taken from the external supply voltage Vcc, intended to supply the DMN domain.

[0083] As will be seen in more detail below, the value of this internal supply voltage IVcc is lower than the value of the external supply voltage Vcc, in particular during a positive electrostatic discharge on the second pad.

[0084] During operation of the integrated circuit, these two voltages are very close and the difference is preferably as small as possible (for example of the order of a few tens of mV) so as not to disturb the operation of the integrated circuit.

[0085] The MPESD protection means are also connected to the first pads PD1-PD3, to the second pad PVcc and to the third pad PVss.

[0086] Reference is now made more particularly to [Fig.2] to describe an embodiment of these MPESD protection means.

[0087] The MPESD protection means comprise first PPDi pairs of first diodes respectively associated with the first pads.

[0088] More precisely, the first PPDI pair of first diodes associated with the PDI pad comprises the two diodes DI 11 and DI 12.

[0089] The second pair PPD2 of first diodes associated with the pad PD2 comprises the two diodes D121 and D122 and the third pair PPD3 of first diodes associated with the pad PD3 comprises the two diodes D131 and DI32.

[0090] These first pairs are connected in parallel.

[0091] The first two diodes of each first pair are connected in series in the same meaning.

[0092] The common terminal of the first two diodes is electrically coupled to the corresponding first pad.

[0093] More precisely, the common terminal of the first two diodes DI 11 and DI 12, which is the anode of diode DI 11 and the cathode of diode DI 12, is connected to the first pad PDI.

[0094] The common terminal of the first two diodes D121 and D122, which is the anode of diode D121 and the cathode of diode D122 is connected to the first pad PD2.

[0095] The common terminal of the first two diodes D131 and DI32 which is the anode of diode D131 and the cathode of diode D132 is connected to the first pad PD3.

[0096] The cathodes of all the first diodes DI 11, D121 and D131 having their anode connected to the first corresponding pad PDI, PD2, PD3, are connected together on a first discharge rail, for example a metallization, PDSR.

[0097] The anodes of all the first diodes DI 12, D122, D132 having their cathode connected to the first corresponding pad PDI, PD2, PD3 are all connected to a second discharge rail GNDR, for example also a metallization, connected to the third pad PVss.

[0098] The MPESD protection means also comprise a first voltage limiter module PCL, an example of the structure of which will be described in more detail below, having a first input terminal BEI connected to the first discharge rail PDSR and a first output terminal BS1 connected to the second discharge rail GNDR.

[0099] The first voltage limiter module PCL is configured so as to be mounted passing in the direction from a first pad PDi to the third pad PVss during a positive electrostatic discharge on one of the first pads PDi, the passing direction being shown in [Fig.2] by the arrow FL

[0100] The MPESD protection means also comprise a second pair of second diodes D21 and D22, this second pair being connected in parallel with the first voltage limiter module PCL and therefore also in parallel with the first pairs of first diodes mentioned above.

[0101] The two diodes D21 and D22 are connected in series in the same direction as the first two diodes of each first pair of first diodes.

[0102] In other words, the cathode of the second diode D21 is connected to the first input terminal BEI of the first voltage limiter module PCL and the anode of the second diode D22 is connected to the second discharge rail GNDR.

[0103] The common terminal BCM of these two second diodes D21 and D22, i.e. the anode of diode D21 and the cathode of diode D22, is connected to the second PVcc pad.

[0104] As will be seen in more detail below, the second diode D21 forms a non-return diode making it possible, during operation of the integrated circuit, to limit the voltage on each first pad PDi to a voltage well above the external supply voltage Vcc.

[0105] The MPESD protection means also comprise a second voltage limiting circuit connected between the second PVcc pad and the third PVss pad.

[0106] This second voltage limiter circuit here comprises a resistor R connected in series with a second voltage limiter module LPCL.

[0107] The second voltage limiter module LPCL is configured to, during a positive electrostatic discharge on the second PVcc pad, be conductive in the same direction as the first voltage limiter module. In this case, the conductive direction illustrated by the arrow F2 in [Fig.2] goes from the second PVcc pad to the third PVss pad.

[0108] The second voltage limiter module LPCL therefore also gives the second voltage limiter circuit the forward direction illustrated by arrow F2.

[0109] The common terminal of the resistor R and of the second voltage limiter module LPCL forms the input terminal BE2 of this second voltage limiter module but also an internal node intended to deliver, during operation of the integrated circuit, the internal supply voltage IVcc.

[0110] The second voltage limiter circuit, and consequently the second voltage limiter module LPCL, is configured to be crossed, in the presence of a positive electrostatic discharge on the second PVcc pad by a current lower than the current crossing the first voltage limiter module PCL.

[0111] This is due here to the presence of the resistance R.

[0112] Reference is now made more particularly to [Fig.3] to describe an embodiment of the first PCL voltage limiter module.

[0113] This here comprises NI similar blocks (NI = 4) connected in parallel between the first input terminal BEI and the first output terminal BS1.

[0114] Each block comprises a lateral NPN bipolar transistor referenced Tl 1, respectively Tl2, T13 and Tl4.

[0115] For the sake of simplification, only the first block comprising the transistor T11 will be described here.

[0116] The collector C of the transistor T11 is connected to the first input terminal BEI while the emitter E of this transistor T11 is connected to the output terminal BS1.

[0117] The base B of the transistor Tl 1 is connected to the output terminal BS1 via a base resistor RB11.

[0118] [Fig.4] illustrates an embodiment of the second LPCL voltage limiting module.

[0119] As can be seen in this [Fig.4], the structure of the second limiter module of LPCL voltage is here identical to the structure of the first PCL module but the size of the second LPCL module is smaller than that of the first PCL module. Indeed, the second LPCL module here only has two lateral NPN transistors T21 and T22 connected in parallel between the input terminal BE2 and the output terminal BS2.

[0120] In a manner analogous to what has been described with reference to [Fig.3], the collector C of each transistor T21, T22 is connected to the input terminal BE2 and the emitter E of each transistor is connected to the output terminal BS2.

[0121] The bases B of the two transistors T21, T22 are respectively connected to the output terminal BS2 via two base resistors RB21 and RB22.

[0122] To have a smaller size than that of the first PCL voltage limiter module, the second LPCL voltage limiter module may comprise N2 lateral bipolar transistors with N2 less than NI (N2 = 2 in this example).

[0123] The second voltage limiter module LPCL has a smaller size because, as will be seen in more detail below, it is intended, in the presence of a positive electrostatic discharge on the second PVcc pad, to be traversed by a lower current than that traversing the first voltage limiter module PCL.

[0124] The trigger threshold of each of these two PCL and LPCL modules is theoretically similar and is for example of the order of 7 volts which corresponds to the avalanche voltage of the N+P diode between the collector and the base of each bipolar transistor.

[0125] More precisely, when, in the presence of an electrostatic discharge, the avalanche voltage of the collector-base junction is reached, the bipolar transistor begins to conduct. As a result, the voltage on its base increases and when the voltage on the base reaches the threshold of the bipolar transistor, i.e. of the order of 0.6 volts, the latter becomes conductive and there is therefore conduction between the collector and the emitter of the bipolar transistor.

[0126] At this moment, the corresponding voltage limiter module is on.

[0127] And, the voltage present at the input terminal of the voltage limiter module is clipped to a value of around 7 volts.

[0128] However, in practice, due in particular to the high current flowing through the first PCL voltage limiter module, the voltage present at the first input terminal BEI of this first PCL voltage limiter module may be greater than 7 volts.

[0129] On the other hand, the voltage on the input terminal BE2 and therefore on the internal node which is connected to the internal power supply pad of the integrated circuit domain, remains limited to approximately 7 volts due to the lower current which passes through this second LPCL voltage limiter module.

[0130] This will be explained in more detail below.

[0131] We now refer more particularly to figures 5 and following to describe examples of implementations of the method corresponding to examples of operation of the MPESD protection means.

[0132] [Fig.5] illustrates the discharge path of the CR current resulting from a positive electrostatic discharge between the first PDI pad and the first PD3 pad.

[0133] More precisely, the current CR from the first pad PDI passes through the diode DI 11 then flows on the first discharge rail PDSR before passing through the first voltage limiter module PCL and flowing on the second discharge rail GNDR before passing through the first diode DI32 to reach the pad PD3.

[0134] As a result, the voltage on the first PDI pad (referenced relative to the voltage on the first PD3 pad) is, in the presence of the positive ESD discharge, limited to the trigger voltage of the first voltage limiter module increased by the threshold voltages of two diodes, i.e. of the order of 8.2 volts in theory.

[0135] [Fig.6] illustrates the discharge path of the CR current resulting from a positive electrostatic discharge between the first pad PD3 and the third pad PVss.

[0136] This time, the current CR resulting from this positive discharge leaves the first pad PD3 then crosses the first diode D131, circulates on the first discharge rail PDSR and crosses the first voltage limiter module PCL before circulating on the second discharge rail GNDR to be reinjected into the third pad PVss.

[0137] And, here again, the voltage on the PD3 pad (referenced relative to the voltage on the third PVss pad) is limited to the trigger voltage of the first voltage limiter module increased by the threshold voltage of a diode, i.e. of the order of 7.6 volts in theory.

[0138] [Fig.7] illustrates the discharge path of the CR current resulting from a negative discharge between the first PDI pad and the third PVss pad.

[0139] This time, the current CR is injected into the second discharge rail GNDR through the diode DI 12 so as to be injected into the third pad PVss.

[0140] This time, the voltage present on the first PDI pad (referenced relative to the voltage on the third PVss pad) is limited to the opposite of the threshold voltage of a diode, i.e. -0.6 volts.

[0141] [Fig.8] illustrates the discharge path of the CR current resulting from a positive discharge between the second PVcc power pad and the third PVss pad.

[0142] As can be seen in this [Fig.8], the current CR coming from the second PVcc pad is divided into a first current CRI which passes through the second diode D21 before passing through the first voltage limiter module to return to the third PVss pad, and into a second current CR2 which passes through the second voltage limiter circuit, i.e. the resistor R and the second voltage limiter module LPCL, before also being injected into the third PVss pad.

[0143] This current distribution is also found in the case of a discharge positive between the second PVcc pad and any of the first pads, for example the first PD2 pad as shown in [Fig.9]

[0144] More precisely, the current CR, coming from the second PVcc pad, is subdivided into a first current CRI and a second current CR2.

[0145] The first current CRI passes through the second diode D21 then the first current limiting module PCL before being reinjected into the first pad PD2 through the second discharge rail GNDR and the first diode D122.

[0146] The second current CR2 passes through the resistor R, then the second voltage limiter module LPCL before circulating on the second discharge rail GNDR and being reinjected into the first pad PD2 through the first diode D122.

[0147] In the examples illustrated in [Fig.8] and in [Fig.9], the second current CR2 is weaker than the first current CRI as will now be explained more particularly with reference to [Fig. 10].

[0148] [Fig. 10] illustrates the case of a positive electrostatic discharge on the PVcc pad, this discharge occurring between the PVcc pad and the PVss pad. It is assumed here that this discharge has a level of 3kV HBM which corresponds to a current peak of 2 amperes (3000 volts / 1500 Ohms).

[0149] The current CR resulting from this discharge is therefore equal, at its peak, to 2 amperes.

[0150] The resistance R is here equal to 10 Ohms.

[0151] It is assumed that the voltage drop across each of the limiter modules PCL and LPCL voltage is equal to 7 volts (which corresponds to their theoretical trigger threshold) and that the voltage drop across the terminals of the second diode D21 in forward conduction is equal to 1 volt.

[0152] Therefore, the voltage drop across the resistor R is equal to 1 volt and consequently the current CR2 passing through the resistor R as well as the second voltage limiter module LPCL is equal to 100 milliamps.

[0153] The first current CRI flowing through the first PCL voltage limiter module is therefore equal to 1.9 A.

[0154] We therefore see in this diagram that in the presence of the electrostatic discharge, the voltage on the PVcc pad is clipped to a value (here 8 volts) greater than the value of the voltage at node BE2 and therefore at the input pad of the internal supply voltage of the domain which is here equal to 7 volts.

[0155] In practice, taking into account the high current flowing through the first voltage limiter module PCL, the voltage clipped by this first voltage limiter module may in certain cases be higher than this theoretical value of 7 volts and reach for example 8 volts which would then lead to a clipped voltage of the order of 9 volts on the second power supply pad PVcc.

[0156] On the other hand, taking into account the lower current CR2 circulating in the second circuit voltage limiter, due to the presence of the resistor, the voltage at node BE2 remains clipped at around 7 volts.

[0157] As regards the value of the resistor R, the higher it is, the lower the current CR2 is and the more the voltage at node BE2 is clipped around the theoretical trigger threshold of the LPCL voltage limiter module, in this case 7 volts.

[0158] The lower the resistance R, the higher the current CR2 and the voltage at node BE2 can then be clipped to a slightly higher value, for example around 7.5 volts.

[0159] It is also appropriate to take into account the value of the internal supply voltage IVcc during operation of the integrated circuit taking into account the voltage drop across the resistor R.

[0160] Thus, if the DMN domain includes an EEPROM memory circuit, then a resistance of 10 Ohms is sufficient, but if we took a resistance of 1 KOhms, then the voltage IVcc would collapse due to the excessive voltage drop across the terminals of the resistance R.

[0161] On the other hand, if the DMN domain includes a microprocessor circuit which can consume up to approximately 20 mA, then it is appropriate to take a resistance R less than 1 Ohm.

[0162] Also, the person skilled in the art will know how to adjust the value of the resistor R taking into account the intended application to obtain good ESD protection at the node BE2 while avoiding too great a drop in the internal supply voltage IVcc.

[0163] During operation of the integrated circuit, the voltage on each first pad PDi, referenced to ground, is clipped to the trigger threshold of the first voltage limiter module PCL increased by the threshold voltage of a diode (for example 0.6V). This clipping does not involve the supply voltage Vcc due to the anti-return diode D21. This is the reason why the voltage on each first pad can rise well above the voltage Vcc+0.6V, which is particularly interesting when the integrated circuit is connected to an FC bus together with other integrated circuits and one of the integrated circuits is stopped (Vcc=0V).

[0164] The invention is not limited to the modes of implementation and embodiment which have just been described but embraces all the variants thereof.

[0165] Thus, it would be possible to replace the resistor R with a short length N-type box using the saturation of electron mobility under a strong electric field.

[0166] Similarly, the lateral bipolar transistors present within the voltage limiter modules could possibly be replaced by switches of the “MOSSWI” type, although less advantageous in terms of size.

[0167] In certain applications the integrated circuit domain may comprise one or more output stages of the “push-pull” type. However, supplying this or these output stages from a single node BE2 may lead to a detrimental appearance of undervoltage peaks on this node BE2.

[0168] Also, in this case, it would be possible to provide for example K (K=2 for example) second voltage limiting circuits, connected in parallel between the second PVcc pad and the third PVss pad.

[0169] The internal node BE2 of one of these second voltage limiting circuits would be used to power the domain of the integrated circuit with the exception of the output stage(s) of the “push-pull” type, while the other second voltage limiting circuit would be used to power only this or these output stage(s) of the “push-pull” type.

[0170] Of course in other applications we could choose K greater than two.

[0171] It would also be possible in certain cases to have several second plots and several third plots.

[0172] All the second pads would be connected to the BCM terminal ([Fig.2]) so as to be able to reinject into the first voltage limiter module PCL which remains unique, and all the third pads would be connected to the anode of the second diode D22 ([Fig.2]).

[0173] But each second pad would be associated with a second voltage limiter circuit of its own, connected between this second pad and a corresponding third pad and whose internal node BE2 would deliver an internal supply voltage specific to this second voltage limiter circuit.

[0174] It would also be possible for each second pad to be associated with M (M being greater than 1) second voltage limiting circuits specific to it, connected in parallel between this second pad and a corresponding third pad, and respectively delivering M internal supply voltages, M being able to be identical or different for each second pad / third pad pair.

Claims

Claims

1. Integrated circuit, comprising several first signal input and / or output pads (PDi), a domain (DMN) of the integrated circuit coupled to said first pads, at least one second pad (PVcc) intended to receive a respective first supply voltage (Vcc), at least one third pad (PVss) intended to be coupled to a supply cold point (Vss) and means (MPESD) for protecting said domain against electrostatic discharges comprising a first voltage limiter module (PCL) having a first input terminal (BEI) electrically coupled to each first pad by a first diode mounted so as to be reverse biased during operation of the integrated circuit, the first voltage limiter module being configured so as to be mounted passing between each first pad (PDi) and said at least one third pad (PVss) during a positive electrostatic discharge on one of the first pads,at least one second voltage limiter circuit (LPCL) electrically coupled between said at least one second pad (PVcc) and said at least one third pad (PVss), each second voltage limiter circuit being configured to be mounted passing between the corresponding second pad and the corresponding third pad during a positive electrostatic discharge on this second pad, having an internal node (BE2) capable of delivering a second supply voltage (IVcc) to said domain, and configured to, in the presence of a positive electrostatic discharge on the corresponding second pad, to be crossed by a current (CR2) lower than the current (CRI) crossing the first voltage limiter module,and a second diode (D21) electrically connected between said first input terminal (BEI) and said at least one second pad (PVcc) so as to be forward biased between said at least one second pad and the first input terminal of the first voltage limiter module during a positive discharge on the corresponding second pad.,

2. Integrated circuit according to claim 1, in which the protection means (MPESD) comprise first pairs (PPDi) of first diodes connected in parallel and respectively associated with the first pads, each first pair (PPDi) comprising two first diodes connected in series in the same direction, the common terminal of the two first diodes being coupled to the first pad cor- corresponding, the first voltage limiter module (PCL) being connected in parallel with the first pairs of diodes (PPDi), a second pair of second diodes (D21, D22) connected in parallel with the voltage limiter circuit module, the two second diodes being connected in series in the same direction as the first diodes, the common terminal (BE2) of the two second diodes being electrically coupled to said at least one second pad (PVcc), each second voltage limiter circuit comprising a second voltage limiter module (LPCL) connected in series with a resistive element (R), the common terminal between the resistive element and the second voltage limiter forming a second input terminal (BE2) for this second voltage limiter module as well as said internal node, the anodes of all the diodes (DI 12, D122, D132, D22) having their cathode connected either to a first pad (PDi) or to said at least one second pad (PVcc),being electrically coupled to said at least one third pad (Vss).,

3. Integrated circuit according to claim 2, wherein the protection means (MPESD) comprises a first discharge rail (PDSR) coupled to said input terminal of the first voltage limiter module and to the cathodes of all the diodes (D111, D121, D131, D21) having their anode coupled either to a first pad (PDi) or to the second pad (PVcc), and a second discharge rail (GNDR) coupled to the third pad (PVss) and to the anodes of all the diodes (DI 12, D122, D132, D22) having their cathode connected either to a first pad or to said at least one second pad.

4. Integrated circuit according to one of claims 2 or 3, wherein the first voltage limiter module (PCL) and said at least one second voltage limiter module (LPCL) have a similar structure.

5. Integrated circuit according to claim 4, in which the first voltage limiter module (PCL) comprises at least one first lateral bipolar transistor (T 11, T12, T13, T14) whose collector forms said first input terminal, whose emitter is coupled to the third pad and whose base is connected to the third pad by a first base resistor, and each second voltage limiter module (LPCL) comprises at least one second lateral bipolar transistor (T21, T22) whose collector forms said second input terminal, whose emitter is coupled to the corresponding third pad and whose base is connected to the corresponding third pad by a second base resistor.

6. Integrated circuit according to claim 4 or 5, wherein said at least one second voltage limiter module (LPCL) has a surface footprint smaller than that of the first voltage limiter module (PCL).

7. Integrated circuit according to claims 5 and 6, wherein the first voltage limiter module (PCL) comprises N1 first transistors in parallel, N1 being greater than 1 and said at least one second voltage limiter module (LPCL) comprises N2 second transistors in parallel, N1 being greater than N2.

8. Integrated circuit according to one of the preceding claims, in which said domain (DMN) comprises a non-volatile memory circuit.

9. Method, comprising - in the presence of a positive electrostatic discharge on one of the first signal input and / or output pads (PDi) coupled to a domain of the integrated circuit, a limitation of the voltage on this first pad by circulating the current (CR) resulting from this discharge through a first voltage limiter module (PCL), - in the presence of a positive electrostatic discharge on a second pad (PVcc) intended to receive, during operation of the integrated circuit, a first supply voltage, a limitation of the voltage on the input terminal (BE2) of at least one second voltage limiter module (LPCL) by distributing the current (CR) resulting from this discharge into on the one hand a first current (CRI) circulating in the first voltage limiter module and in a non-return diode (D21) coupled between the second pad (PVcc),the first pad (PDi) and the input (BEI) of the first voltage limiter module (PCL) and on the other hand at least one second current (CR2) flowing in said at least one second voltage limiter module, said at least one second current (CR2) being lower than the first current (CRI), and -during operation of the integrated circuit, a delivery to said domain of at least one second supply voltage (IVcc) equal to the voltage present at said input terminal of said at least one second voltage limiter module (LPCL).,

10. Method according to claim 9, wherein said at least one second current (CR2) also flows in a resistive element (R) coupled between said input terminal (BE2) of the corresponding second current limiting module and the second pad (PVcc).

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