Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device capable of suppressing deterioration in electric characteristics and reducing a chip size, and a manufacturing method thereof.SOLUTION: According to one embodiment, a semiconductor device comprises a substrate, a first plug, first wiring, second wiring, a second plug, a third plug, and third wiring. The first plug is provided above the substrate, and extends in a first direction crossing an upper surface of the substrate. The first wiring is provided on the first plug, and contains copper. The second wiring is provided below the first plug. The second plug is located in a second direction crossing the first direction with respect to the first plug, and includes an upper end at a height different from an upper end of the first plug and a lower end at a height identical to the height of a lower end of the first plug. The third plug is provided on the second plug, extends in the first direction, and contains tungsten. The third wiring is provided below the second plug.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same. [Background technology]

[0002] When manufacturing a semiconductor device, it is desirable to reduce the chip size while suppressing deterioration of electrical characteristics. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2023-25904 A Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of reducing the chip size while suppressing deterioration of electrical characteristics, and a method for manufacturing the same are provided. [Means for solving the problem]

[0005] According to one embodiment, a semiconductor device includes a substrate, a first plug, a first wiring, a second wiring, a second plug, a third plug, and a third wiring. The first plug is provided above the substrate and extends in a first direction intersecting an upper surface of the substrate. The first wiring is provided on the first plug and contains copper. The second wiring is provided below the first plug. The second plug is located in a second direction intersecting the first direction with respect to the first plug, and has an upper end with a different height than an upper end of the first plug and a lower end with the same height as a lower end of the first plug. The third plug is provided on the second plug, extends in the first direction, and contains tungsten. The third wiring is provided below the second plug. [Brief description of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view showing a semiconductor device according to an embodiment. [Diagram 2] 1 is a plan view showing a stacked film of a semiconductor device according to an embodiment; [Diagram 3] 2 is an exploded view showing an electrode layer of the semiconductor device according to the embodiment; FIG. [Figure 4] 1 is a cross-sectional view showing a contact plug of a semiconductor device according to an embodiment. [Diagram 5] 1 is a vertical cross-sectional view showing a contact plug of a semiconductor device according to an embodiment. [Figure 6] 1 is a cross-sectional view showing a pillar portion of a semiconductor device according to an embodiment; [Figure 7] 1 is a plan view showing a wiring layout of a semiconductor device according to an embodiment; [Figure 8] 1 is a cross-sectional view showing a wiring layout of a semiconductor device according to an embodiment. [Figure 9] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 10] 10A to 10C are cross-sectional views showing the method for manufacturing the semiconductor device according to the embodiment, following FIG. 9. [Figure 11] 5A to 5C are cross-sectional views showing details of a method for manufacturing a semiconductor device according to an embodiment. [Figure 12] 12A to 12C are cross-sectional views showing the method for manufacturing the semiconductor device according to the embodiment, following FIG. 11. [Figure 13] 5A to 5C are cross-sectional views showing a method for manufacturing a semiconductor device according to a first comparative example. [Figure 14] 11 is a plan view showing a wiring layout of a semiconductor device manufactured by using a method for manufacturing a semiconductor device according to a second comparative example. FIG. [Figure 15] 11 is a cross-sectional view showing a wiring layout of a semiconductor device manufactured by using a method for manufacturing a semiconductor device according to a second comparative example. FIG. [Figure 16] 13A to 13C are cross-sectional views showing the method for manufacturing the semiconductor device according to the embodiment, subsequent to FIG. 12. [Figure 17] FIG. 11 is a cross-sectional view showing a semiconductor device according to a modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In Fig. 1 to Fig. 17, the same components are denoted by the same reference numerals, and duplicated explanations will be omitted. In this specification, the term "same" used to express the heights of a plurality of via plugs is not limited to the case where they are strictly the same, but also includes the case where they are substantially the same.

[0008] FIG. 1 is a cross-sectional view showing a semiconductor device according to an embodiment.

[0009] The semiconductor device in FIG. 1 is, for example, a three-dimensional semiconductor memory. The semiconductor device in FIG. 1 includes a circuit portion 1 and an array portion 2 provided on the circuit portion 1. The array portion 2 includes a memory cell array including a plurality of memory cells. The circuit portion 1 includes a CMOS circuit that controls the memory cell array. The semiconductor device in FIG. 1 is manufactured, for example, by bonding a circuit wafer including the circuit portion 1 and an array wafer including the array portion 2. FIG. 1 shows a bonding surface S between the circuit portion 1 (circuit wafer) and the array portion 2 (array wafer).

[0010] FIG. 1 shows X, Y, and Z directions that are perpendicular to each other. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may or may not coincide with the direction of gravity. The Z direction is an example of a first direction. The -X direction is an example of a second direction that intersects with the first direction. The Y direction is an example of a third direction that intersects with the first and second directions.

[0011] The circuit portion 1 includes a substrate 11, a plurality of transistors 12, a plurality of transistors 13, and an interlayer insulating film 14. The circuit portion 1 further includes a plurality of contact plugs 31, a wiring layer 32, a plurality of via plugs 33, a wiring layer 34, a plurality of via plugs 35, and a plurality of metal pads 36. The transistor 12 is an example of a first transistor. The transistor 13 is an example of a second transistor. The transistor 12 includes a gate insulating film 12a, a gate electrode 12b, a diffusion layer 12c, and a diffusion layer 12d. The transistor 13 includes a gate insulating film 13a, a gate electrode 13b, a diffusion layer 13c, and a diffusion layer 13d. Each of the wiring layers 32 and 34 may include a plurality of wires.

[0012] The array portion 2 includes an interlayer insulating film 21, a laminated film P, a plurality of columnar portions 24, and a plurality of contact plugs 26. The contact plugs 26 are an example of a third plug. The laminated film P includes a plurality of electrode layers 23 that are laminated in the Z direction and insulated from each other. More specifically, the laminated film P includes a plurality of insulating films 22 and a plurality of electrode layers 23 alternately. The array portion 2 further includes a plurality of metal pads 41, a plurality of via plugs 42, a wiring layer 43, a plurality of via plugs 44, a wiring layer 45, a plurality of via plugs 46, and a plurality of via plugs 47. The wiring layer 43 is an example of a second wiring. The via plug 44 is an example of a first plug. The wiring layer 45 is an example of a first wiring. The via plug 46 is an example of a fourth plug. The via plug 47 is an example of a fifth plug. Each of the wiring layers 43 and 45 may include a plurality of wirings. The array portion 2 further includes a plurality of metal pads 51, a plurality of via plugs 52, a wiring layer 53, and a plurality of via plugs 54. The wiring layer 53 is an example of a third wiring. The via plugs 54 are an example of a second plug. The wiring layer 53 may include a plurality of wirings.

[0013] First, a detailed description will be given of the circuit portion 1. The substrate 11 is, for example, a semiconductor substrate such as a silicon substrate. In Fig. 1, the upper surface of the substrate 11 is parallel to the X direction and the Y direction and perpendicular to the Z direction.

[0014] The transistors 12 are provided on a substrate 11. The gate insulating film 12a and the gate electrode 12b of each transistor 12 are laminated in order on the substrate 11. The diffusion layer 12c and the diffusion layer 12d of each transistor 12 are formed in the substrate 11 so as to sandwich the gate electrode 12b. One of the diffusion layer 12c and the diffusion layer 12d functions as a source region. The other of the diffusion layer 12c and the diffusion layer 12d functions as a drain region. Each transistor 12 is electrically connected to the corresponding columnar portion 24 via a metal pad 36, 41, etc. The transistor 12 may be provided facing the regions R2, R3 in the laminated film P where the columnar portion 24 is provided.

[0015] The transistors 13 are provided on a substrate 11. The gate insulating film 13a and the gate electrode 13b of each transistor 13 are laminated in order on the substrate 11. The diffusion layer 13c and the diffusion layer 13d of each transistor 13 are formed in the substrate 11 so as to sandwich the gate electrode 13b. One of the diffusion layer 13c and the diffusion layer 13d functions as a source region. The other of the diffusion layer 13c and the diffusion layer 13d functions as a drain region. Each transistor 13 is electrically connected to a corresponding contact plug 26 via a metal pad 36, 41, etc. At least a part of the transistors 13 may be provided facing a region R1 of the laminated film P in which the contact plug 26 is provided.

[0016] The interlayer insulating film 14 is provided on the substrate 11 and covers the transistor 12 and the transistor 13. The interlayer insulating film 14 is, for example, a laminated film including a silicon oxide film and other insulating films.

[0017] 1, contact plugs 31, wiring layer 32, via plugs 33, wiring layer 34, via plugs 35, and metal pads 36 are provided in this order on substrate 11. In the example shown in FIG. 1, each contact plug 31 is electrically connected to diffusion layer 12c or 13c of transistor 12 or 13. Each contact plug 31 may be electrically connected to gate electrode 12b or 13b of transistor 12 or 13.

[0018] Next, the array portion 2 will be described in detail. Fig. 2 is a plan view showing a laminated film of the semiconductor device according to the embodiment. Fig. 3 is an exploded view showing an electrode layer 23 of the semiconductor device according to the embodiment.

[0019] 1, the interlayer insulating film 21 of the array portion 2 is provided on the interlayer insulating film 14 of the circuit portion 1. The interlayer insulating film 21 is sandwiched between the interlayer insulating film 14 and the laminated film P. The interlayer insulating film 21 is, for example, a laminated film including a silicon oxide film and other insulating films.

[0020] The insulating films 22 and the electrode layers 23 are alternately stacked on the interlayer insulating film 21 above the substrate 11 to form a laminated film P. The electrode layers 23 are spaced apart from one another in the Z direction. Each insulating film 22 is, for example, a silicon oxide film. Each electrode layer 23 is, for example, a metal layer including a W (tungsten) layer. Each electrode layer 23 functions as, for example, a word line.

[0021] As shown in Figures 1 and 2, the laminated film P has regions R1, R2, R3, and R4. Region R1 is an example of a first region. Region R2 is an example of a second region. Region R3 is an example of a third region. Region R4 is an example of a fourth region.

[0022] The region R1 is located on the contact plug 26 and is electrically connected to the contact plug 26. The region R1 corresponds to a hook-up portion in the semiconductor device. The region R2 is located in the X direction with respect to the region R1 and above the via plug 46. In other words, the region R2 is a region in which the columnar portion 24 is provided. The region R2 corresponds to a memory cell array portion in the semiconductor device. The region R3 is located in the -X direction with respect to the region R1 and above the via plug 46. In other words, the region R3 is a region in which the columnar portion 24 is provided. The region R3 corresponds to a memory cell array portion in the semiconductor device. The region R4 is located in the Y direction or the -Y direction with respect to the region R1 and is a region that electrically connects the electrode layer 23 of the region R2 and the electrode layer 23 of the region R3. In other words, the electrode layer 23 of the region R4 is continuous with the electrode layer 23 of the region R2 and the electrode layer 23 of the region R3. The region R4 is also called a bridge region.

[0023] 2, the laminated film P has slits ST-1, ST-2, and ST-3. The slit ST-1 is an example of a first dividing portion, and the slit ST-2 is an example of a second dividing portion. The slit ST-2 is also an example of the first dividing portion, and in this case, the slit ST-3 is an example of the second dividing portion.

[0024] The slit ST-1 extends in the X direction and divides the laminated film P. The slit ST-2 is located in the Y direction relative to the slit ST-1 with the contact plug 26 therebetween. The slit ST-2 extends in the X direction and divides the laminated film P. The slit ST-3 is located in the Y direction relative to the slit ST-2 with the contact plug 26 therebetween. The slit ST-3 extends in the X direction and divides the laminated film P.

[0025] The regions R1, R2, R3, and R4 of the laminated film P are divided by slits ST-1, ST-2, and ST-3. An insulating film 27 is provided in the slits ST-1, ST-2, and ST-3.

[0026] As shown in FIGS. 1 to 3, the laminated film P in the region R1 is formed in a staircase shape along the X and Y directions. That is, the laminated film P in the region R1 has a staircase structure along the X and Y directions. More specifically, the staircase structure has a staircase portion SP extending from the lowest step, which is the end in the Z direction, toward the X direction, and dummy staircase portions SPd extending from the lowest step toward the -X, Y, and -Y directions. The staircase portion SP is formed in a gentle staircase shape. The electrode layer 23 of the staircase portion SP has a step surface (i.e., a terrace region) to which the contact plug 26 is connected. On the other hand, the dummy staircase portion SPd is formed in a steep staircase shape. The electrode layer 23 of the dummy staircase portion SPd does not have a step surface to which the contact plug 26 is connected.

[0027] 2, the step surface of the staircase portion SP on the upper step side (the X-direction side in FIG. 2) has a larger dimension in the Y direction than the step surface of the staircase portion on the lower step side (the -X-direction side in FIG. 2). Therefore, the step surface of the staircase portion SP on the upper step side has a margin that allows multiple contact plugs 26 to be connected along the Y direction between adjacent slits.

[0028] Each contact plug 26 is provided in the interlayer insulating film 21 in the region R1. Each contact plug 26 is, for example, a polysilicon layer or a metal layer. Each contact plug 26 penetrates the insulating film 22 of the staircase portion SP and contacts the step surface of the corresponding electrode layer 23. By contacting the step surface, each contact plug 26 is electrically connected to the corresponding electrode layer 23. Furthermore, each contact plug 26 is electrically connected to the corresponding transistor 13.

[0029] As shown in Fig. 1, a plurality of contact plugs 26 are arranged along the X direction. As shown in Fig. 1 and Fig. 3, the plurality of contact plugs 26 arranged along the X direction are connected to electrode layers 23 of staircase portions SP of different steps (i.e., layers).

[0030] As shown in Fig. 2, in the upper staircase portion SP, two contact plugs 26, 26-2 are arranged along the Y direction between adjacent slits ST-1, ST-2. The contact plug 26-2 is an example of a sixth plug. By arranging the two contact plugs 26, 26-2 along the Y direction between adjacent slits ST-1, ST-2, the chip size in the X direction can be reduced. Meanwhile, in the staircase portions SP other than the upper staircase portion SP, the contact plugs 26 are arranged one by one between adjacent slits.

[0031] As shown in FIG. 2, two contact plugs 26, 26-2 are also arranged along the Y direction between the adjacent slits ST-2, ST-3 of the upper step portion SP. The wiring structure between the slits ST-2, ST-3 is similar to the wiring structure between the slits ST-1, ST-2. Specifically, the wiring structure between the slits ST-2, ST-3 has a mirror symmetric shape with respect to the wiring structure between the slits ST-1, ST-2, with respect to the XZ plane defined at the center of the slit ST-2. In order to avoid redundant explanations, the following description will focus on the wiring structure between the slits ST-1, ST-2.

[0032] FIG. 4 is a cross-sectional view showing a contact plug 26 of a semiconductor device according to an embodiment. FIG. 5 is a vertical cross-sectional view showing a contact plug 26 of a semiconductor device according to an embodiment. As shown in FIGS. 4 and 5, a plurality of columnar portions 28 penetrating the interlayer insulating film 21 and the laminated film P are provided in the region R1. When forming the laminated film P, a sacrificial film and an insulating film 22 are laminated, and then the sacrificial film is replaced with the electrode layer 23. The columnar portions 28 are provided penetrating the sacrificial film and the insulating film 22 before replacement. The columnar portions 28 have a function of maintaining the mechanical strength of the staircase portion SP during replacement. The columnar portions 28 have an insulating film such as a silicon oxide film.

[0033] The columnar portion 24 is provided in the laminated film P in regions R2 and R3. The columnar portion 24 provided in region R2 is an example of a first columnar portion. The columnar portion 24 provided in region R3 is an example of a second columnar portion. Each columnar portion 24 has a columnar shape extending in the Z direction and penetrates the electrode layer 23. FIG. 6 is a cross-sectional view showing a columnar portion 24 of a semiconductor device according to an embodiment. As shown in FIG. 6, the columnar portion 24 includes a block insulating film 24a, a charge storage layer 24b, a tunnel insulating film 24c, a channel semiconductor layer 24d, and a core insulating film 24e, which are formed in this order on the side surface of the laminated film P.

[0034] The block insulating film 24a is, for example, a silicon oxide film. The charge storage layer 24b is, for example, an insulating film such as a silicon nitride film. The charge storage layer 24b may be a semiconductor layer such as a polysilicon layer. The tunnel insulating film 24c is, for example, a silicon oxide film. The channel semiconductor layer 24d is, for example, a polysilicon layer. The core insulating film 24e is, for example, a silicon oxide film. The channel semiconductor layer 24d in each columnar portion 24 is electrically connected to the corresponding transistor 12.

[0035] 1, the metal pad 41, the via plug 42, the wiring layer 43, the via plug 44, the wiring layer 45, the via plug 46, and the via plug 47 are provided in this order above the substrate 11. The upper end of the via plug 47 is in contact with the columnar portion 24. The metal pad 41 is joined to the corresponding metal pad 36 of the circuit portion 1. As a result, the columnar portion 24 is electrically connected to the transistor 12 via the via plugs 47, 46, the wiring layer 45, the via plug 44, the wiring layer 43, the via plug 42, the metal pads 41, 36, the via plug 35, the wiring layer 34, the via plug 33, the wiring layer 32, and the contact plug 31.

[0036] 1, a metal pad 51, a via plug 52, a wiring layer 53, and a via plug 54 are provided in this order above the substrate 11. The upper end of the via plug 54 is in contact with the contact plug 26. The metal pad 51 is joined to a corresponding metal pad 36 of the circuit portion 1. As a result, the contact plug 26 is electrically connected to the transistor 13 via the via plug 54, the wiring layer 53, the via plug 52, the metal pads 51 and 36, the via plug 35, the wiring layer 34, the via plug 33, the wiring layer 32, and the contact plug 31.

[0037] Next, the layout of the wirings 41-47, 51-54 in the array portion 2 will be described in more detail. FIG. 7 is a plan view showing the wiring layout of the semiconductor device according to the embodiment. FIG. 8 is a cross-sectional view showing the wiring layout of the semiconductor device according to the embodiment. The cross section around the contact plug 26 indicated by the character A in FIG. 8 is the AA cross section in FIG. 7. The cross section around the columnar portion 24 indicated by the character B in FIG. 8 is a cross section in the same direction as FIG. 1. Note that the cross section indicated by the character B in FIG. 8 is a cross section corresponding to the region R2 of the laminated film P. The cross section corresponding to the region R3 of the laminated film P is also similar to the character B in FIG. 8.

[0038] The via plugs 44 are provided above the substrate 11 (i.e., in the Z direction). The via plug 44 provided opposite the region R2 is an example of a first plug. The via plug 44 provided opposite the region R3 is an example of an eighth plug. The via plugs 44 extend upwardly to intersect with the upper surface of the substrate 11. The via plugs 44 contain, for example, tungsten.

[0039] Each wiring layer 45 is provided on a via plug 44. The wiring layer 45 provided opposite the region R2 is an example of a first wiring. The wiring layer 45 provided opposite the region R3 is an example of a fifth wiring. The wiring layer 45 is electrically connected to the via plug 44. The wiring layer 45 contains copper. The wiring layer 45 is, for example, a bit line extending in the Y direction. By containing copper, the wiring layer 45 can be formed at low cost.

[0040] The wiring layer 43 is provided under the via plug 44. The wiring layer 43 is electrically connected to the via plug 44. The wiring layer 43 contains, for example, tungsten.

[0041] The via plug 54 is located in the -X direction intersecting the Z direction with respect to the via plug 44. The via plug 54 has an upper end with a different height than the upper end of the via plug 44 and a lower end with the same height as the lower end of the via plug 44. In Fig. 8, the heights of the upper and lower ends of the via plug 54 are indicated by two-dot chain lines. The via plug 54 contains the same material as the via plug 44, for example, tungsten.

[0042] The contact plug 26 is provided on the via plug 54. The contact plug 26 is electrically connected to the via plug 54. The contact plug 26 extends in the Z direction. The contact plug 26 contains tungsten.

[0043] The wiring layer 53 is provided under the via plug 54. The wiring layer 53 is located in the same layer as the wiring layer 43. The wiring layer 53 contains the same material as the wiring layer 43, for example, tungsten.

[0044] The upper end of the via plug 54 is located higher than the upper end of the via plug 44. The via plug 46 is provided on the wiring layer 45. The via plug 46 is electrically connected to the wiring layer 45. The via plug 46 has an upper end at the same height as the upper end of the via plug 54. In other words, the via plug 54 is provided across multiple layers, including the layer in which the via plug 44 is located, the layer in which the wiring layer 45 is located, and the layer in which the via plug 46 is located. The via plug 54 has a larger outer diameter than the via plug 44.

[0045] The via plug 54 is provided directly below the contact plug 26. In other words, the via plug 54 is hardly shifted in the X and Y directions with respect to the contact plug 26. The center of the via plug 54 may coincide with the center of the contact plug 26.

[0046] An insulating layer 3 is provided under the wiring layer 45. The insulating layer 3 is penetrated by a via plug 44 and a via plug 54. The insulating layer 3 is, for example, a silicon nitride film (SiCN). The insulating layer 3 has a function of suppressing the diffusion of copper in the via plug 44.

[0047] The via plug 47 is provided between the via plug 46 and the columnar portion 24. The via plug 47 extends in the Z direction. The height of the lower end of the via plug 47 is the same as the height of the lower end of the contact plug 26. The via plug 47 is electrically connected to the via plug 46 and the columnar portion 24.

[0048] The contact plug 26-2 is located between the slit ST-1 and the slit ST-2 in the Y direction with respect to the contact plug 26. The contact plug 26-2 has an upper end that is as high as the upper end of the contact plug 26 and a lower end that is as high as the lower end of the contact plug 26. The contact plug 26-2 contains tungsten.

[0049] A via plug 54-2 is provided below the contact plug 26-2. The via plug 54-2 is an example of a seventh plug. The via plug 54-2 has an upper end with the same height as the upper end of the via plug 54 and a lower end with the same height as the lower end of the via plug 54. The via plug 54-2 is electrically connected to the contact plug 26-2. The via plug 54-2 contains tungsten like the via plug 54.

[0050] A wiring layer 53-2 is provided under the via plug 54-2. The wiring layer 53-2 is an example of a fourth wiring. The wiring layer 53-2 is electrically connected to the via plug 54-2. The wiring layer 53-2 contains the same material as the wiring layer 53, for example, tungsten.

[0051] A via plug 52-2 is provided below the wiring layer 53-2. A metal pad 51-2 is provided below the via plug 52-2. The metal pad 51-2 is joined to the metal pad 36 of the circuit portion 1. Thus, like the contact plug 26, the contact plug 26-2 is electrically connected to the transistor 13.

[0052] Next, a method for manufacturing the semiconductor device according to the embodiment having the above configuration will be described. Fig. 9 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the embodiment. Fig. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the embodiment, following Fig. 9.

[0053] FIG. 9 shows a circuit portion 1 included in a circuit wafer and an array portion 2 included in an array wafer. The orientation of the array portion 2 shown in FIG. 9 is opposite to that of the array portion 2 shown in FIG. 1. The semiconductor device of this embodiment is manufactured by bonding the circuit wafer and the array wafer together, as described above. FIG. 9 shows the array portion 2 before its orientation is reversed for bonding, and FIG. 10 shows the array portion 2 after its orientation is reversed for bonding and bonded to the circuit portion 1.

[0054] Fig. 9 shows an upper surface S1 of the circuit portion 1 and an upper surface S2 of the array portion 2. The array portion 2 shown in Fig. 9 includes a substrate 6 provided under a laminated film P. The substrate 6 is, for example, a semiconductor substrate such as a silicon substrate. The substrate 11 is an example of a first substrate. The substrate 6 is an example of a second substrate.

[0055] For example, the semiconductor device according to the embodiment is manufactured as follows. First, a plurality of transistors 12, a plurality of transistors 13, an interlayer insulating film 14, a plurality of contact plugs 31, a wiring layer 32, a plurality of via plugs 33, a wiring layer 34, a plurality of via plugs 35, and a plurality of metal pads 36 are formed on a substrate 11 (FIG. 9). Also, an interlayer insulating film 21, a plurality of insulating films 22, a plurality of electrode layers 23, a plurality of columnar portions 24, and a plurality of contact plugs 26, 26-2 are formed on a substrate 6 (FIGS. 8 and 9). Also, a plurality of metal pads 41, a plurality of via plugs 42, a wiring layer 43, a plurality of via plugs 44, a wiring layer 45, a plurality of via plugs 46, and a plurality of via plugs 47 are formed on the substrate 6 (FIG. 9). Also, a plurality of metal pads 51, 51-2, a plurality of via plugs 52, 52-2, wiring layers 53, 53-2, and a plurality of via plugs 54, 54-2 are formed on the substrate 6 (FIGS. 8 and 9).

[0056] Next, as shown in FIG. 10, the circuit wafer (circuit portion 1) and the array wafer (array portion 2) are bonded together by mechanical pressure. This bonds the interlayer insulating film 14 and the interlayer insulating film 21 together. Next, the circuit wafer and the array wafer are annealed at 400° C. This bonds the metal pad 36 and the metal pads 41, 51, and 51-2 together. The metal pads 36, 41, 51, and 51-2 are, for example, metal layers including a Cu (copper) layer.

[0057] As a result, each columnar portion 24 is electrically connected to the corresponding transistor 12, and each contact plug 26, 26-2 is electrically connected to the corresponding transistor 13 (FIG. 10).

[0058] Thereafter, the substrate 11 is thinned by CMP (Chemical Mechanical Polishing), the substrate 6 is removed by CMP, and the circuit wafer and the array wafer are cut into a plurality of chips. In this manner, the semiconductor device shown in FIG.

[0059] 1 shows the boundary surface between the interlayer insulating film 14 and the interlayer insulating film 21, and the boundary surface between the metal pad 36 and the metal pads 41 and 51, but these boundaries generally become unobservable after the above-mentioned annealing. However, the positions of these boundaries can be estimated by detecting the inclination of the side surface of the metal pad 36, the inclination of the side surfaces of the metal pads 41 and 51, and the positional deviation between the metal pad 36 and the metal pads 41 and 51.

[0060] Next, a manufacturing method of a part of the semiconductor device according to the embodiment will be described in more detail. Fig. 11 is a cross-sectional view showing the details of the manufacturing method of the semiconductor device according to the embodiment. First, a laminated film P is formed above a substrate 6. After forming the laminated film P, a columnar portion 24 is formed in regions R2 and R3 of the laminated film P (Fig. 11(a)).

[0061] After forming the columnar portion 24, contact plugs 26, 26-2 containing tungsten are simultaneously formed above the substrate 6 (FIGS. 11(a) and 8). Note that the laminated film P and the contact plug 26-2 are not shown in FIG. 11(a). The contact plugs 26, 26-2 are formed so as to be electrically connected to the electrode layer 23 of the laminated film P in the region R1 of the laminated film P. Also, a via plug 47 is formed on the columnar portion 24.

[0062] After forming the contact plugs 26, 26-2 and the via plug 47, a copper-containing wiring layer 45 is formed above the substrate 6 with a gap in the X direction from the contact plug 26 (FIG. 11(a)). The wiring layer 45 is formed on the via plug 46 so as to be electrically connected to the columnar portion 24.

[0063] After forming the wiring layer 45, the insulating layer 3 is formed on the wiring layer 45 (FIG. 11(a)). The insulating layer 3 is formed over the contact plugs 26, 26-2. After forming the insulating layer 3, the interlayer insulating film 21 is formed on the insulating layer 3 (FIG. 11(a)).

[0064] After forming the interlayer insulating film 21, a mask layer 8 is formed on the interlayer insulating film 21 (FIG. 11(a)). After forming the mask layer 8, an opening H1 is formed in the mask layer 8 above the via plugs 26, 26-2. The opening H1 is formed by, for example, SMAP (Stacked Mask Process).

[0065] Next, holes H2 are formed in the interlayer insulating film 21 by RIE (Reactive Ion Etching) using the mask layer 8 in which the openings H1 are formed as a mask (FIG. 11(b)). The holes H2 are formed so as to penetrate the interlayer insulating film 21 and the insulating layer 3 and expose the contact plugs 26, 26-2. After the holes H2 are formed, the mask layer 8 is removed. The mask layer 8 is removed by, for example, ashing.

[0066] After removing the mask layer 8, a mask layer 9 is formed on the interlayer insulating film 21 so as to fill the hole H2 (FIG. 11(c)). After forming the mask layer 9, an opening (not shown) is formed in the mask layer 9 above the wiring layer 45. The opening is formed by, for example, SMAP.

[0067] Next, a hole H3 is formed in the interlayer insulating film 21 by RIE using the mask layer 9 with the opening formed therein as a mask (FIG. 11(c)). At this time, the insulating layer 3 functions as an etching stopper, so that the hole H3 is formed until it reaches the insulating layer 3.

[0068] Fig. 12 is a cross-sectional view showing the method for manufacturing a semiconductor device according to the embodiment, following Fig. 11. After the hole H3 is formed, the mask layer 9 is removed (Fig. 12(a)). The mask layer 9 is removed by, for example, ashing.

[0069] After removing the mask layer 9, the insulating layer 3 on the wiring layer 45 is removed to form a hole H4 penetrating the interlayer insulating film 21 up to the wiring layer 45 (FIG. 12(b)). The insulating layer 3 on the wiring layer 45 may be removed by, for example, dry etching. The substrate 6 in which the holes H2 and H4 are formed is subjected to wet etching to remove residues generated by RIE from the substrate 6 (FIG. 12(b)). The chemical used for wet etching contains, for example, hydrochloric acid (HCL), dilute hydrofluoric acid (DHF) and choline (TMY).

[0070] FIG. 13 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a first comparative example. In FIG. 13(a), "+" indicates charges, i.e., ions, used in RIE. Here, as a first comparative example, an example in which a wiring layer 450 containing copper is formed above the contact plug 26 instead of the via plug 54 will be described. In the first comparative example, when a hole H2 is formed above the contact plug 26 by RIE (FIG. 13(a)), charges are stored in the capacitance between the contact plug 26 and the electrode layer 23. Incidentally, when a hole H3 is formed above the columnar portion 24, charges are also stored in the capacitance between the columnar portion 24 and the electrode layer 23. However, the capacitance between the columnar portion 24 and the electrode layer 23 is smaller than the capacitance between the contact plug 26 and the electrode layer 23. Therefore, the amount of charges stored in the capacitance between the columnar portion 24 and the electrode layer 23 is negligibly small compared to the amount of charges stored in the capacitance between the contact plug 26 and the electrode layer 23.

[0071] If charges are accumulated in the capacitance between the contact plug 26 and the electrode layer 23, the wiring layer 450 will dissolve in the chemical solution and disappear during wet etching after the hole H2 is formed (FIG. 13(b)). This is due to the battery effect based on the correlation between the potential of copper and the pH of the chemical solution. Specifically, during wet etching, the charges accumulated in the capacitance between the contact plug 26 and the electrode layer 23 move to the wiring layer 450, so that the wiring layer 450 has a potential greater than 0 [V]. If the wiring layer 450 made of copper comes into contact with an acidic chemical solution (such as hydrochloric acid or dilute hydrofluoric acid) while having a potential greater than 0 [V], the wiring layer 450 will dissolve in the chemical solution due to the battery effect. Therefore, in the first comparative example, the disappearance of the wiring layer 450 will deteriorate the electrical characteristics.

[0072] Next, as a second comparative example, an example in which a plurality of via plugs 440 are connected to the wiring layer 450 will be described. FIG. 14 is a plan view showing the wiring layout of a semiconductor device manufactured using the semiconductor device manufacturing method according to the second comparative example. FIG. 15 is a cross-sectional view showing the wiring layout of a semiconductor device manufactured using the semiconductor device manufacturing method according to the second comparative example. In the second comparative example, six via plugs 440 are connected to one wiring layer 450. As a result, the charge accumulated in the capacitance between the contact plug 26 and the electrode layer 23 during wet etching is dispersed and moved to six positions of the wiring layer 450 that come into contact with the chemical solution (i.e., positions corresponding to the six holes H2 in which the six via plugs 440 are respectively formed). As a result, compared to the case in which one via plug 440 is connected to one wiring layer 450 (FIG. 13(a)), the potential of the wiring layer 450 that comes into contact with the chemical solution is reduced to about 1 / 6 at the six positions. By reducing the potential of the wiring layer 450, the disappearance of the wiring layer 450 due to the battery effect is suppressed. Even if the wiring layer 450 is partially lost due to the battery effect, at least one via plug 440 connected to the remaining wiring layer 450 maintains the conduction between the metal pad 51 and the contact plug 26. However, in the second comparative example, the size of the wiring layer 450 in the X direction is increased because six via plugs 440 need to be connected to the wiring layer 450. In addition, the increase in the size of the wiring layer 450 in the X direction makes it difficult to secure a margin for forming two contact plugs 26, 26-2 between the adjacent slits ST-1, ST-2. Therefore, in the second comparative example, even if the deterioration of the electrical characteristics can be suppressed to some extent, the chip size cannot be reduced.

[0073] In contrast, as described above, in the embodiment, before wet etching, the wiring layer 450 containing copper is not formed on the contact plug 26, and instead, the hole H2 is formed to expose the contact plug 26. This makes it possible to structurally avoid the disappearance of the wiring layer 450 made of copper and the increase in the size of the wiring layer 450. Therefore, according to the embodiment, it is possible to reduce the chip size while suppressing the deterioration of the electrical characteristics.

[0074] Fig. 16 is a cross-sectional view showing the method for manufacturing a semiconductor device according to an embodiment subsequent to Fig. 12. After wet etching of the substrate 6, a via plug 44 containing tungsten is formed on the wiring layer 45. The via plug 44 is formed so as to fill the hole H4 (see Fig. 12(b)). Simultaneously with the formation of the via plug 44, a via plug 54 containing tungsten is formed on the contact plug 26. The via plug 54 is formed so as to fill the hole H2. After the via plugs 44 and 54 are formed, the tungsten on the interlayer insulating film 21 is removed by CMP (Chemical Mechanical Polisher) (Fig. 16(a)).

[0075] After CMP, a wiring layer 43 containing tungsten is formed on the via plug 44. At the same time as the formation of the wiring layer 43, a wiring layer 53 containing tungsten is formed on the via plug 54 (FIG. 16(b)).

[0076] As described above, the semiconductor device according to the embodiment includes the substrate 11, the via plug 44, the wiring layer 45, the wiring layer 43, the via plug 54, the contact plug 26, and the wiring layer 53. The via plug 44 is provided above the substrate 11 and extends in the Z direction intersecting the upper surface of the substrate 11. The wiring layer 45 is provided on the via plug 44 and contains copper. The wiring layer 43 is provided below the via plug 44. The via plug 54 is located in the -X direction intersecting the Z direction with respect to the via plug 44. The via plug 54 has an upper end with a different height than the upper end of the via plug 44 and a lower end with the same height as the lower end of the via plug 44. The contact plug 26 is provided on the via plug 54, extends in the Z direction, and contains tungsten. The wiring layer 53 is provided below the via plug 54. This eliminates the need to provide the copper-containing wiring layer 450 (see FIGS. 13 to 15) under the contact plug 26, thereby preventing deterioration of electrical characteristics due to loss of the wiring layer 450 and an increase in the size of the wiring layer 450. Therefore, according to the embodiment, it is possible to reduce the chip size while suppressing deterioration of electrical characteristics.

[0077] In the embodiment, the upper end of the via plug 54 is located higher than the upper end of the via plug 44. Also, a via plug 46 having an upper end at the same height as the upper end of the via plug 54 is provided on the wiring layer 45. This makes it possible to minimize the number of steps required to manufacture the wiring (i.e., the via plug 54) that connects the contact plug 26 and the wiring layer 53 to each other.

[0078] Moreover, according to the embodiment, by providing the via plug 54 directly below the contact plug 26, it becomes possible to further reduce the chip size.

[0079] Furthermore, according to the embodiment, the via plugs 44 and 54 contain the same material, so that the via plugs 44 and 54 can be formed simultaneously, thereby reducing the number of manufacturing steps for the semiconductor device.

[0080] Furthermore, according to the embodiment, the outer diameter of the via plug 54 is made larger than the outer diameter of the via plug 44, so that the via plug 54 can be appropriately formed to a height spanning multiple layers.

[0081] Furthermore, according to the embodiment, the wiring layers 43 and 53 contain the same material, so that the wiring layers 43 and 53 can be formed simultaneously, thereby reducing the number of steps in manufacturing the semiconductor device.

[0082] In the embodiment, the insulating layer 3 penetrated by the via plugs 44, 54 is provided under the wiring layer 45. This makes it possible to suppress the copper contained in the wiring layer 45 from diffusing into the interlayer insulating film 21.

[0083] The semiconductor device according to the embodiment further includes a laminated film P, a columnar portion 24, and a via plug 47. The laminated film P includes a plurality of electrode layers 23 that are laminated in the Z direction and insulated from each other. The laminated film P has a region R1 located on the contact plug 26 and electrically connected to the contact plug 26. The laminated film P further has a region R2 located in the X direction relative to the region R1 and above the via plug 46. The columnar portion 24 is provided in the region R2. The columnar portion 24 includes a semiconductor layer 24d extending in the Z direction and a charge storage layer 24b provided between the semiconductor layer 24d and the electrode layer 23. The via plug 47 is provided between the via plug 46 and the columnar portion 24 and extends in the Z direction. This makes it possible to reduce the chip size while suppressing deterioration of electrical characteristics in a three-dimensional semiconductor memory device.

[0084] The semiconductor device according to the embodiment further includes a slit ST-1, a slit ST-2, a contact plug 26-2, a via plug 54-2, and a wiring layer 53-2. The slit ST-1 extends in the X direction and divides the laminated film P. The slit ST-2 is located in the Y direction with respect to the slit ST-1 with the contact plug 26 therebetween. The slit ST-2 extends in the X direction and divides the laminated film P. The contact plug 26-2 is located in the Y direction with respect to the contact plug 26 between the slit ST-1 and the slit ST-2. The contact plug 26-2 has an upper end with the same height as the upper end of the contact plug 26 and a lower end with the same height as the lower end of the contact plug 26, and contains tungsten. The via plug 54-2 is provided below the contact plug 26-2. The via plug 54-2 has an upper end with the same height as the upper end of the via plug 54 and a lower end with the same height as the lower end of the via plug 54. The wiring layer 53-2 is provided under the via plug 54-2. This allows two contact plugs 26, 26-2 to be provided along the Y direction between the adjacent slits ST-1, ST-2, thereby effectively reducing the chip size.

[0085] Furthermore, according to the embodiment, the via plug 54-2 contains the same material as the via plugs 44, 54, so that the via plugs 44, 54, 54-2 can be formed simultaneously. This makes it possible to effectively reduce the chip size while reducing the number of manufacturing steps for the semiconductor device.

[0086] Furthermore, according to the embodiment, the wiring layer 53-2 contains the same material as the wiring layers 43 and 53, so that the wiring layers 43, 53, and 53-2 can be formed simultaneously. This makes it possible to effectively reduce the chip size and reduce the number of manufacturing steps for the semiconductor device.

[0087] In the embodiment, the laminated film P further includes a region R3 and a region R4. The region R3 is located in the -X direction with respect to the region R1, and is provided with a columnar portion 24 similar to the region R2. The region R4 is located in the Y direction with respect to the region R1. The region R4 electrically connects the electrode layer 23 of the region R2 and the electrode layer 23 of the region R3. This allows the staircase structure to be formed in the center of the cell region, thereby reducing the length and resistance of the electrode layer 23 compared to the case where the staircase structure is formed outside the cell region.

[0088] Next, a modified example of the embodiment will be described. Up to this point, the embodiment has been described in which the laminated film P in the region R1 has a staircase structure. In contrast, as shown in FIG. 17, the laminated film P in the region R1 may be continuous with the laminated film P in the regions R2 and R3, except for the through portion of the contact plug 26 and the insulating layer 25 provided on the periphery of the contact plug 26.

[0089] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel device and method described in this specification can be implemented in various other forms. In addition, various omissions, substitutions, and modifications can be made to the forms of the device and method described in this specification without departing from the spirit of the invention. The appended claims and their equivalents are intended to include such forms and modifications that fall within the scope and spirit of the invention. [Explanation of symbols]

[0090] 3: insulating layer, 11: substrate, 12: transistor, 13: transistor, 21: interlayer insulating film, 23: electrode layer, 24: columnar portion, 26: contact plug, 26-2: contact plug, 41: metal pad, 42: via plug, 43: wiring layer, 44: via plug, 45: wiring layer, 46: via plug, 47: via plug, 51: metal pad, 52: via plug, 53: wiring layer, 54: via plug

Claims

1. A substrate; a first plug provided above the substrate and extending in a first direction intersecting an upper surface of the substrate; a first interconnection containing copper and provided on the first plug; a second wiring provided under the first plug; a second plug located in a second direction intersecting the first direction with respect to the first plug, the second plug having an upper end at a different height than an upper end of the first plug and a lower end at the same height as a lower end of the first plug; a third plug disposed on the second plug, extending in the first direction, and containing tungsten; and a third wiring provided under the second plug. Semiconductor device.

2. an upper end of the second plug is located higher than an upper end of the first plug; 2. The semiconductor device according to claim 1, further comprising a fourth plug provided on said first interconnect and having an upper end at the same height as an upper end of said second plug.

3. 2. The semiconductor device according to claim 1, wherein said second plug is provided immediately below said third plug.

4. The semiconductor device according to claim 1 , wherein the first plug and the second plug contain the same material.

5. The semiconductor device according to claim 1 , wherein the second plug has an outer diameter larger than that of the first plug.

6. The semiconductor device according to claim 1 , wherein said second wiring and said third wiring contain the same material.

7. 2. The semiconductor device according to claim 1, further comprising an insulating layer provided under said first wiring and penetrated by said first plug and said second plug.

8. a stacked film including a plurality of electrode layers stacked in the first direction and insulated from one another, the stacked film having a first region located on the third plug and electrically connected to the third plug, and a second region located on the opposite side of the first region in the second direction and above the fourth plug; a first columnar section including a first semiconductor layer provided in the second region and extending in the first direction, and a first charge storage layer provided between the first semiconductor layer and the plurality of electrode layers; The semiconductor device according to claim 2 , further comprising: a fifth plug provided between said fourth plug and said first columnar portion and extending in said first direction.

9. The semiconductor device according to claim 8 , wherein the first wiring is a bit line.

10. a first dividing portion extending in the second direction and dividing the stacked film; a second dividing portion that is located in a third direction intersecting the first direction and the second direction with respect to the first dividing portion with the third plug therebetween, extends in the second direction, and divides the stacked film; a sixth plug, which is located between the first dividing portion and the second dividing portion in the third direction or on the opposite side of the third direction with respect to the third plug, has an upper end having the same height as an upper end of the third plug and a lower end having the same height as a lower end of the third plug, and contains tungsten; a seventh plug provided below the sixth plug and having an upper end at the same height as an upper end of the second plug and a lower end at the same height as a lower end of the second plug; 9. The semiconductor device according to claim 8, further comprising a fourth interconnection provided under said seventh plug.

11. The semiconductor device according to claim 10 , wherein the seventh plug contains the same material as the first plug and the second plug.

12. The semiconductor device according to claim 10 , wherein the fourth wiring contains the same material as the second wiring and the third wiring.

13. The laminated film is a third region in which a second columnar section is provided, the third region including a second semiconductor layer located in the second direction with respect to the first region and extending in the first direction, and a second charge storage layer provided between the second semiconductor layer and the plurality of electrode layers; 13. The semiconductor device according to claim 8, further comprising a fourth region located in a third direction intersecting the first direction and the second direction or on the opposite side of the third direction with respect to the first region, and electrically connecting the electrode layer of the second region and the electrode layer of the third region.

14. a fifth wiring that is provided in the third region, is electrically connected to the second columnar section, and contains copper; 14. The semiconductor device according to claim 13, further comprising: an eighth plug provided below said fifth interconnect, extending in said first direction, and having an upper end with the same height as an upper end of said first plug and a lower end with the same height as a lower end of said first plug.

15. a first transistor provided on the substrate and electrically connected to the second wiring; The semiconductor device according to claim 1 , further comprising a second transistor provided on said substrate and electrically connected to said third interconnect.

16. forming a third plug containing tungsten above the first substrate, the third plug extending in a first direction intersecting an upper surface of the first substrate; forming a first wiring containing copper above the first substrate and spaced apart from the third plug in a second direction intersecting the first direction; forming a first plug extending in the first direction on the first wiring; forming a second plug on the third plug, the second plug having an upper end having the same height as an upper end of the first plug and a lower end having a different height than a lower end of the first plug; forming a second wiring on the first plug; forming a third interconnect on the second plug.

17. The method for manufacturing a semiconductor device according to claim 16 , wherein the first plug and the second plug are formed simultaneously.

18. forming an insulating layer on the first wiring before forming the first plug and the second plug; forming an insulating film on the insulating layer; forming a first hole in the insulating film penetrating the insulating layer to expose a third plug; forming a second hole in the insulating film so as to penetrate the insulating layer and expose the first wiring; The method further includes treating the first substrate in which the first hole and the second hole are formed with a chemical solution; the first plug is formed in the second hole after the first substrate is treated with the chemical solution; The method for manufacturing a semiconductor device according to claim 16 , wherein the second plug is formed in the first hole after the first substrate is treated with the chemical solution.

19. before forming the third plug and the first wiring, forming a laminated film above the first substrate, the laminated film including a plurality of electrode layers laminated in the first direction and insulated from one another, the laminated film having a first region and a second region positioned in the second direction relative to the first region; forming a first columnar section in the second region, the first columnar section including a first semiconductor layer extending in the first direction and a first charge storage layer provided between the first semiconductor layer and the plurality of electrode layers; forming a first transistor and a second transistor on a second substrate; After forming the second wiring and the third wiring, the first substrate and the second substrate are bonded together to electrically connect the second wiring to the first transistor and to electrically connect the third wiring to the second transistor; further comprising removing the first substrate; the first wiring is formed so as to be electrically connected to the first columnar portion, 17. The method for manufacturing a semiconductor device according to claim 16, wherein the third plug is formed so as to be electrically connected to the electrode layer in the first region.

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