Semiconductor memory device

Abstract

To provide a semiconductor memory device that operates favorably.SOLUTION: A semiconductor memory device includes a semiconductor substrate and a plurality of transistors provided on the semiconductor substrate. A first transistor among the plurality of transistors includes a first gate insulating film provided on the semiconductor substrate, a first gate electrode provided on the first gate insulating film, a side wall insulating film provided on both side surfaces of the first gate electrode, a first region included in the semiconductor substrate and provided at a position overlapping the first gate electrode when viewed in a first direction intersecting a surface of the semiconductor substrate, a first diffusion layer included in the semiconductor substrate, connected to a first contact electrode extending in the first direction, and containing a first conductive-type impurity, a second diffusion layer included in the semiconductor substrate, provided between the first region and the first diffusion layer, and containing the first conductive-type impurity, and a third diffusion layer included in the semiconductor substrate, provided between the second diffusion layer and the first diffusion layer, connected to the second diffusion layer, and containing the first conductive-type impurity. A concentration of the second diffusion layer is higher than a concentration of the third diffusion layer.SELECTED DRAWING: Figure 12

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor memory device. [Background technology]

[0002] 2. Description of the Related Art A semiconductor memory device including a semiconductor substrate and a plurality of transistors provided on the semiconductor substrate is known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2021 / 0082896 [Patent Document 2] US Patent Application Publication No. 2021 / 0320094 [Patent Document 3] US Patent Application Publication No. 2022 / 0085003 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor memory device that operates favorably is provided. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a semiconductor substrate and a plurality of transistors provided on the semiconductor substrate. A first transistor of the plurality of transistors includes a first gate insulating film provided on the semiconductor substrate, a first gate electrode provided on the first gate insulating film, sidewall insulating films provided on both side surfaces of the first gate electrode, a first region included in the semiconductor substrate and overlapping with the first gate electrode when viewed from a first direction intersecting with a surface of the semiconductor substrate, a first diffusion layer included in the semiconductor substrate and connected to a first contact electrode extending in the first direction and containing a first conductive type impurity, a second diffusion layer included in the semiconductor substrate and provided between the first region and the first diffusion layer and containing the first conductive type impurity, and a third diffusion layer included in the semiconductor substrate and provided between the second diffusion layer and the first diffusion layer and containing the first conductive type impurity and connected to the second diffusion layer. The concentration of the second diffusion layer is higher than the concentration of the third diffusion layer. [Brief description of the drawings]

[0006] [Figure 1] FIG. 2 is a schematic block diagram showing the configuration of a memory die MD. [Diagram 2] 2 is a schematic circuit diagram showing a configuration of a portion of a memory die MD. [Diagram 3] 2 is a schematic circuit diagram showing a configuration of a portion of a memory die MD. [Figure 4] 1 is a schematic exploded perspective view showing a configuration example of a semiconductor memory device according to a first embodiment. [Diagram 5] 2 is a schematic bottom view showing an example of the configuration of the chip CM. FIG. [Figure 6] 2 is a schematic cross-sectional view showing a configuration of a portion of a memory die MD. [Figure 7] 2 is a schematic cross-sectional view showing a configuration of a portion of a memory die MD. [Figure 8] 2 is a schematic bottom view showing a configuration of a portion of the chip CM. FIG. [Figure 9] 2 is a schematic cross-sectional view showing the configuration of a portion of the chip CM. [Figure 10] 1 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a first embodiment. [Figure 11] 1 is a schematic plan view showing the structure of an N-type high-voltage transistor TrNH according to the first embodiment. [Figure 12] 1 is a schematic cross-sectional view showing the structure of an N-type high-voltage transistor TrNH according to the first embodiment. [Figure 13] 4 is a diagram for explaining the impurity concentration of the N-type high-voltage transistor TrNH according to the first embodiment. FIG. [Figure 14] 2 is a cross-sectional view showing the structure of a portion of the N-type high-voltage transistor TrNH according to the first embodiment. [Figure 15] 12 is a diagram conceptually showing impurity concentrations along the dotted line AA' in the region shown in FIG. 11. FIG. [Figure 16] 11 is a schematic cross-sectional view showing the structure of a P-type high-voltage transistor TrPH shown in FIG. [Figure 17] 11 is a schematic cross-sectional view showing the structure of an N-type low-voltage transistor TrNL shown in FIG. [Figure 18] 11 is a schematic cross-sectional view showing the structure of a P-type low-voltage transistor TrPL shown in FIG. [Figure 19] 10 is a schematic cross-sectional view showing a structure of an N-type high-voltage transistor TrNHA according to a modified example of the first embodiment. FIG. [Figure 20] 1A to 1C are schematic cross-sectional views for explaining a manufacturing method of an N-type high-voltage transistor TrNH and the like according to the first embodiment. [Figure 21] 1A to 1C are schematic cross-sectional views for explaining a manufacturing method of an N-type high-voltage transistor TrNH and the like according to the first embodiment. [Figure 22] 1A to 1C are schematic cross-sectional views for explaining a manufacturing method of an N-type high-voltage transistor TrNH and the like according to the first embodiment. [Figure 23] 1A to 1C are schematic cross-sectional views for explaining a manufacturing method of an N-type high-voltage transistor TrNH and the like according to the first embodiment. [Figure 24] 1A to 1C are schematic cross-sectional views for explaining a manufacturing method of an N-type high-voltage transistor TrNH and the like according to the first embodiment. [Diagram 25] 1A to 1C are schematic cross-sectional views for explaining a manufacturing method of an N-type high-voltage transistor TrNH and the like according to the first embodiment. [Figure 26] 1A to 1C are schematic cross-sectional views for explaining a manufacturing method of an N-type high-voltage transistor TrNH and the like according to the first embodiment. [Figure 27] 1A to 1C are schematic cross-sectional views for explaining a manufacturing method of an N-type high-voltage transistor TrNH and the like according to the first embodiment. [Figure 28] 5A to 5C are schematic cross-sectional views for illustrating a manufacturing method of the N-type high-voltage transistor TrNH according to the first embodiment. [Figure 29] 1A to 1C are schematic plan views for explaining a manufacturing method of the N-type high-voltage transistor TrNH according to the first embodiment. [Diagram 30] 5A to 5C are schematic cross-sectional views for illustrating a manufacturing method of the N-type high-voltage transistor TrNH according to the first embodiment. [Diagram 31] 1A to 1C are schematic plan views for explaining a manufacturing method of the N-type high-voltage transistor TrNH according to the first embodiment. [Diagram 32] 5A to 5C are schematic cross-sectional views for illustrating a manufacturing method of the N-type high-voltage transistor TrNH according to the first embodiment. [Diagram 33] 1A to 1C are schematic plan views for explaining a manufacturing method of the N-type high-voltage transistor TrNH according to the first embodiment. [Diagram 34] 5A to 5C are schematic cross-sectional views for illustrating a manufacturing method of the N-type high-voltage transistor TrNH according to the first embodiment. [Diagram 35] 5A to 5C are schematic cross-sectional views for illustrating a manufacturing method of the N-type high-voltage transistor TrNH according to the first embodiment. [Diagram 36] 5A to 5C are schematic cross-sectional views for illustrating a manufacturing method of the N-type high-voltage transistor TrNH according to the first embodiment. [Figure 37]5A to 5C are schematic cross-sectional views for explaining a manufacturing method of the N-type low-voltage transistor TrNL and the like according to the first embodiment. [Figure 38] 10A to 10C are schematic cross-sectional views for illustrating a manufacturing method of an N-type high-voltage transistor TrNHA according to a modified example of the first embodiment. [Figure 39] 10A to 10C are schematic cross-sectional views for illustrating a manufacturing method of an N-type high-voltage transistor TrNHA according to a modified example of the first embodiment. [Diagram 40] 5A to 5C are schematic cross-sectional views for illustrating a manufacturing method of the N-type high-voltage transistor TrNH according to the first embodiment. [Diagram 41] 11 is a schematic cross-sectional view showing the structure of an N-type high-voltage transistor TrNH according to a second embodiment. FIG. [Diagram 42] 11 is a schematic plan view showing a well formation region in which an N-type high-voltage transistor TrNH according to the second embodiment is configured. FIG. [Diagram 43] 42 is a diagram conceptually showing the impurity concentration in the depth direction (Z direction) of the N-type high-voltage transistor TrNH2 along the dotted line BB' in FIG. 41. [Diagram 44] 11A to 11C are schematic cross-sectional views for illustrating a manufacturing method of the N-type high-voltage transistor TrNH2 according to the second embodiment. [Diagram 45] 11A to 11C are schematic cross-sectional views for illustrating a manufacturing method of the N-type high-voltage transistor TrNH2 according to the second embodiment. [Figure 46] 11A to 11C are schematic cross-sectional views for illustrating a manufacturing method of the N-type high-voltage transistor TrNH2 according to the second embodiment. [Figure 47] 11A to 11C are schematic cross-sectional views for illustrating a manufacturing method of the N-type high-voltage transistor TrNH2 according to the second embodiment. [Figure 48] 11A to 11C are schematic cross-sectional views for illustrating a manufacturing method of the N-type high-voltage transistor TrNH2 according to the second embodiment. [Figure 49]11A to 11C are schematic cross-sectional views for illustrating a manufacturing method of the N-type high-voltage transistor TrNH2 according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiment is merely an example, and is not intended to limit the present invention. Also, the following drawings are schematic, and for the sake of explanation, some configurations may be omitted. Also, parts common to multiple embodiments may be given the same reference numerals, and explanations may be omitted.

[0008] In addition, in this specification, the term "semiconductor memory device" may refer to a memory die, or may refer to a memory system including a controller die, such as a memory chip, a memory card, or an SSD (Solid State Drive). Furthermore, it may refer to a configuration including a host computer, such as a smartphone, a tablet terminal, or a personal computer.

[0009] In addition, in this specification, when it is said that a first configuration is "electrically connected" to a second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via wiring, a semiconductor member, a transistor, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in an OFF state.

[0010] In addition, in this specification, when it is said that a first configuration is "connected between" a second configuration and a third configuration, it may mean that the first configuration, the second configuration, and the third configuration are connected in series, and that the second configuration is connected to the third configuration via the first configuration.

[0011] In addition, in this specification, when it is said that a circuit or the like "conducts" two wirings or the like, it may mean, for example, that the circuit or the like includes a transistor or the like, that the transistor or the like is provided in a current path between the two wirings, and that the transistor or the like is in an ON state.

[0012] In this specification, a predetermined direction parallel to the upper surface of the substrate is called the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and a direction perpendicular to the upper surface of the substrate is called the Z direction.

[0013] In this specification, a direction along a predetermined plane may be referred to as a first direction, a direction along this predetermined plane that intersects with the first direction may be referred to as a second direction, and a direction that intersects with this predetermined plane may be referred to as a third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0014] In this specification, expressions such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "up," and the direction toward the substrate along the Z direction is called "down." Furthermore, when referring to a certain configuration, the lower surface or lower end refers to the surface or end of the configuration facing the substrate, and when referring to the upper surface or upper end, refers to the surface or end of the configuration facing away from the substrate. Furthermore, surfaces that intersect with the X or Y direction are called side surfaces, etc.

[0015] In addition, in this specification, when referring to a configuration, member, etc., "width," "length," or "thickness" in a specific direction, this may mean the width, length, or thickness in a cross section observed by SEM (Scanning electron microscopy), TEM (Transmission electron microscopy), or the like.

[0016] In addition, in this specification, the term "wiring" may include wiring, via contact electrodes, connection parts for connecting wiring and via contact electrodes, pasted electrodes, and the like.

[0017] [First embodiment] [Circuit configuration of memory die MD] Fig. 1 is a schematic block diagram showing the configuration of a memory die MD according to the first embodiment. Fig. 2 is a schematic circuit diagram showing a partial configuration of the memory die MD. Fig. 3 is a schematic circuit diagram showing a partial configuration of the memory die MD.

[0018] FIG. 1 illustrates a plurality of control terminals. These control terminals may be represented as control terminals corresponding to high active signals (positive logic signals). Furthermore, the control terminals may be represented as control terminals corresponding to low active signals (negative logic signals). Furthermore, the control terminals may be represented as control terminals corresponding to both high active signals and low active signals. In FIG. 1, the reference numerals of the control terminals corresponding to low active signals include an overline. In this specification, the reference numerals of the control terminals corresponding to low active signals include a slash (" / "). The description in FIG. 1 is an example, and the specific embodiment can be appropriately adjusted. For example, it is also possible to make some or all of the high active signals low active signals, and to make some or all of the low active signals high active signals.

[0019] 1, the memory die MD includes a memory cell array MCA and a peripheral circuit PC. The peripheral circuit PC includes a voltage generating circuit VG, a row decoder RD, a sense amplifier module SAM, and a sequencer SQC. The peripheral circuit PC also includes a cache memory CM, an address register ADR, a command register CMR, and a status register STR. The peripheral circuit PC also includes an input / output control circuit I / O and a logic circuit CTR.

[0020] [Circuit configuration of memory cell array MCA] 2, the memory cell array MCA includes a plurality of memory blocks BLK. Each of the memory blocks BLK includes a plurality of string units SU. Each of the string units SU includes a plurality of memory strings MS. One end of each of the memory strings MS is connected to a peripheral circuit PC via a bit line BL. The other ends of each of the memory strings MS are connected to the peripheral circuit PC via a common source line SL.

[0021] The memory string MS includes a drain side select transistor STD, a plurality of memory cells MC (memory transistors), and a source side select transistor STS. The drain side select transistor STD, the plurality of memory cells MC, and the source side select transistor STS are connected in series between a bit line BL and a source line SL. Hereinafter, the drain side select transistor STD and the source side select transistor STS may be simply referred to as select transistors (STD, STS).

[0022] The memory cells MC are field-effect transistors. The memory cells MC include a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cells MC varies depending on the amount of charge in the charge storage film. The memory cells MC store one or more bits of data. A word line WL is connected to each of the gate electrodes of the memory cells MC corresponding to one memory string MS. Each of these word lines WL is commonly connected to all the memory strings MS in one memory block BLK.

[0023] The selection transistors (STD, STS) are field-effect transistors. The selection transistors (STD, STS) include a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film may include a charge storage layer. The gate electrodes of the selection transistors (STD, STS) are connected to selection gate lines (SGD, SGS), respectively. One drain side selection gate line SGD is commonly connected to all memory strings MS in one string unit SU. One source side selection gate line SGS is commonly connected to all memory strings MS in one memory block BLK. The drain side selection gate line SGD and the source side selection gate line SGS may each be referred to as a selection gate line SG.

[0024] [Circuit configuration of voltage generation circuit VG] The voltage generating circuit VG (FIG. 1) includes a plurality of voltage generating units vg1 to vg3, as shown in FIG. 3. The voltage generating units vg1 to vg3 generate voltages of a predetermined magnitude in a read operation, a write operation, and an erase operation, and supply the voltage to the voltage supply line L. VG1 ~L VG3 For example, in a write operation, the voltage generating unit vg1 outputs the program voltage V PGM In addition, the voltage generating unit vg2 outputs a read pass voltage in a read operation. In addition, the voltage generating unit vg2 outputs a write pass voltage in a write operation. Hereinafter, the read pass voltage and the write pass voltage are referred to as the non-selection voltage V USEL The voltage generating unit vg3 outputs a read voltage in a read operation. The voltage generating unit vg3 outputs a verify voltage in a write operation. Hereinafter, the read voltage and the verify voltage are referred to as the selected voltage V CGR The voltage generating units vg1 to vg3 may be, for example, boost circuits such as charge pump circuits, or step-down circuits such as regulators. P The voltage supply line L Pis the power supply voltage V CC or ground voltage V SS (Figure 1) are supplied. These voltage supply lines L P is connected to, for example, a pad electrode P. The operating voltage output from the voltage generating circuit VG is appropriately adjusted in accordance with a control signal from the sequencer SQC.

[0025] The voltage generation circuit VG (FIG. 1) described with reference to FIG. 3 above is configured to generate a program voltage, a read pass voltage, a write pass voltage, a read voltage, and a verify voltage to be applied to the word lines WL via the wiring CGI. However, the voltage generation circuit VG can generate not only the operating voltages to be applied to the word lines WL, but also a plurality of operating voltages to be applied to the bit lines BL, the source lines SL, and the select gate lines (SGD, SGS) during the read operation, the write operation, and the erase operation on the memory cell array MCA, and output them to a plurality of voltage supply lines. These operating voltages are appropriately adjusted according to control signals from the sequencer SQC.

[0026] [Circuit configuration of row decoder RD] The row decoder RD (FIG. 1) includes a row control circuit RowC, a word line decoder WLD, a driver circuit DRV, and an address decoder (not shown), as shown in FIG. 3. The row control circuit RowC includes a plurality of block decoder units blkd and a block decoder (not shown).

[0027] The plurality of block decoder units blkd correspond to the plurality of memory blocks BLK in the memory cell array MCA. The block decoder unit blkd includes a plurality of word line switches WLSW. The plurality of word line switches WLSW correspond to the plurality of word lines WL in the memory blocks BLK.

[0028] The word line switch WLSW is, for example, a field effect type NMOS transistor. A drain electrode of the word line switch WLSW is connected to the word line WL. A source electrode of the word line switch WLSW is connected to a wiring CGI. The wiring CGI is connected to all the block decoder units blkd in the row control circuit RowC. A gate electrode of the word line switch WLSW is connected to a signal supply line BLKSEL. A plurality of signal supply lines BLKSEL are provided corresponding to all the block decoder units blkd. In addition, the signal supply line BLKSEL is connected to all the word line switches WLSW in the block decoder unit blkd.

[0029] In a read operation, a write operation, etc., for example, the address data D in the address register ADR (FIG. 1) ADD The signal supply line BLKSEL corresponding to one block decoder unit blkd corresponding to the block address included in the memory block BLK1 becomes the "H" state. Moreover, the signal supply line BLKSEL corresponding to the other block decoder units blkd becomes the "L" state. Moreover, a voltage corresponding to the multiple word lines WL is supplied to the wiring CGI. As a result, a voltage is supplied to the word line WL in one memory block BLK corresponding to the above block address. Moreover, the word lines WL in the other memory blocks BLK become floating.

[0030] The word line decoder WLD includes a plurality of word line decode units wld. The plurality of word line decode units wld correspond to a plurality of memory cells MC in the memory string MS. In the example of FIG. 3, the word line decode unit wld includes two transistors T WLS ,T WLU The transistor T WLS ,T WLU is, for example, a field effect NMOS transistor. WLS ,T WLU The drain electrode of the transistor T is connected to the wiring CGI. WLS The source electrode is wired CGI S Transistor TWLU The source electrode is wired CGI U Transistor T WLS The gate electrode of the signal line WLSEL S Transistor T WLU The gate electrode of the signal line WLSEL U Signal line WLSEL is connected to S is one of the transistors T included in each word line decode unit wld. WLS A plurality of signal lines WLSEL are provided corresponding to the U The other transistor T included in each word line decode unit wld is WLU The word line decoder WLD includes two transistors T WLS ,T WLU The structure will be described later.

[0031] In a read operation, a write operation, etc., for example, the address data D in the address register ADR (FIG. 1) ADD A signal line WLSEL corresponding to one word line decode unit wld corresponding to the page address included in S goes to the “H” state, and the corresponding WLSEL U In addition, the signal lines WLSEL corresponding to the other word line decode units wld are in the "L" state. S goes to the “L” state, and the corresponding WLSEL U In addition, the wiring CGI S A voltage corresponding to the selected word line WL is supplied to the line CGI U A voltage corresponding to the unselected word lines WL is supplied to one word line WL corresponding to the page address. Thus, a voltage corresponding to the selected word line WL is supplied to one word line WL corresponding to the page address. Moreover, voltages corresponding to the unselected word lines WL are supplied to the other word lines WL.

[0032] The driver circuit DRV is, for example, a transistor T DRV1 ~T DRV6 The transistor T DRV1 ~TDRV6 is, for example, a field effect NMOS transistor. DRV1 ~T DRV4 The drain electrode is wired CGI S Transistor T DRV5 ,T DRV6 The drain electrode is wired CGI U Transistor T DRV1 The source electrode of the voltage supply line L VG1 , and is connected to the output terminal of the voltage generating unit vg1 via the transistor T DRV2 ,T DRV5 The source electrode of the voltage supply line L VG2 , and is connected to the output terminal of the voltage generating unit vg2 via the transistor T DRV3 The source electrode of the voltage supply line L VG3 , and is connected to the output terminal of the voltage generating unit vg3 via the transistor T DRV4 ,T DRV6 The source electrode of the voltage supply line L P The transistor T DRV1 ~T DRV6 The gate electrodes of the six transistors T DRV1 ~T DRV6 The structure will be described later.

[0033] In the read operation, write operation, etc., for example, the wiring CGI S One of the signal lines VSEL1 to VSEL4 corresponding to the wiring CGI U One of the two corresponding signal lines VSEL5 and VSEL6 goes to the "H" state, and the other goes to the "L" state.

[0034] An address decoder (not shown) sequentially refers to the row address RA of the address register ADR (FIG. 1) in accordance with a control signal from the sequencer SQC (FIG. 1). The row address RA includes the above-mentioned block address and page address. The address decoder uses the above-mentioned signal lines BLKSEL and WLSEL S ,WLSEL U The voltage is controlled to be in the “H” or “L” state.

[0035] In the example of Fig. 3, the row decoder RD is provided with one block decoder unit blkd for each memory block BLK. However, this configuration can be changed as appropriate. For example, one block decoder unit blkd may be provided for two or more memory blocks BLK.

[0036] [Circuit configuration of the sense amplifier module SAM] The sense amplifier module SAM (FIG. 1) detects the ON / OFF state of a memory cell MC and obtains data indicating the state of the memory cell MC. Such an operation is sometimes called a sense operation. The sense amplifier module SAM includes a plurality of sense amplifier units. The plurality of sense amplifier units correspond to a plurality of bit lines BL. Each of the plurality of sense amplifier units includes a sense amplifier circuit and a latch circuit.

[0037] [Circuit configuration of cache memory CM] The cache memory CM (FIG. 1) includes a plurality of latch circuits. The plurality of latch circuits are connected to the latch circuits in the sense amplifier module SAM via wiring DBUS. Data DAT included in the plurality of latch circuits is transferred sequentially to the sense amplifier module SAM or the input / output control circuit I / O.

[0038] In addition, a decode circuit and a switch circuit (not shown) are connected to the cache memory CM. The decode circuit decodes the column address CA held in the address register ADR. The switch circuit connects the latch circuit corresponding to the column address CA to the bus BUS (FIG. 1) in response to the output signal of the decode circuit.

[0039] [Circuit configuration of sequencer SQC] The sequencer SQC (Figure 1) reads the command data D held in the command register CMR. CMD In accordance with the above, the sequencer SQC outputs internal control signals to the row decoder RD, the sense amplifier module SAM, and the voltage generating circuit VG. In addition, the sequencer SQC outputs status data D ST is output to the status register STR.

[0040] The sequencer SQC also generates a ready / busy signal and outputs it to the terminal RY / ( / BY). While the terminal RY / ( / BY) is in the "L" state (busy period), access to the memory die MD is basically prohibited. Also, while the terminal RY / ( / BY) is in the "H" state (ready period), access to the memory die MD is permitted.

[0041] [Circuit configuration of input / output control circuit I / O] The input / output control circuit I / O includes data signal input / output terminals DQ0 to DQ7, toggle signal input / output terminals DQS, / DQS, a plurality of input circuits, a plurality of output circuits, a shift register, and a buffer circuit. The plurality of input circuits, the plurality of output circuits, the shift register, and the buffer circuit are each connected to a power supply voltage V CCQ and ground voltage V SS is connected to the terminal supplied with

[0042] The data input via the data signal input / output terminals DQ0 to DQ7 is output from the buffer circuit to the cache memory CM, the address register ADR, or the command register CMR in response to the internal control signal from the logic circuit CTR. Also, the data output via the data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or the status register STR to the buffer circuit in response to the internal control signal from the logic circuit CTR.

[0043] The input circuits include, for example, a comparator connected to any one of the data signal input / output terminals DQ0 to DQ7 or both of the toggle signal input / output terminals DQS, / DQS. The output circuits include, for example, an OCD (Off Chip Driver) circuit connected to any one of the data signal input / output terminals DQ0 to DQ7 or either of the toggle signal input / output terminals DQS, / DQS.

[0044] [Circuit configuration of logic circuit CTR] The logic circuit CTR (Figure 1) receives external control signals from a controller die (not shown) via external control terminals / CEn, CLE, ALE, / WE, RE, and / RE, and outputs internal control signals to the input / output control circuit I / O in response.

[0045] [Memory Die MD Structure] 4 is a schematic exploded perspective view showing a configuration example of the semiconductor memory device according to the first embodiment. As shown in FIG. 4, the memory die MD includes a chip C on the memory cell array MCA side. M and the peripheral circuit PC side chip C P And, it is equipped with.

[0046] Chip C M On the upper surface of the X Also, chip C M On the underside of I1 Also, chip C P On the upper surface of the I2 The following is Chip CM Regarding the multiple laminated electrodes P I1 The surface on which the external pad electrodes P X The surface on which the chip C is provided is called the back surface. P Regarding the multiple laminated electrodes P I2 The surface on which the chip C is provided is called the front surface, and the surface opposite the front surface is called the back surface. P The surface of the chip C P The chip C is located above the back surface of the chip C. M The back side of the chip is C M The surface of the substrate is provided above the substrate.

[0047] Chip C M and Chip C P is Chip C M Surface and chip C P The surface of the laminated electrodes P I1 is a plurality of laminated electrodes P I2 , and a plurality of bonding electrodes P I2 The electrode is placed in a position where it can be attached to the I1 and the laminated electrode P I2 What is Chip C? M and Chip C P The laminate functions as a laminate electrode for bonding the two and electrically connecting them.

[0048] In the example of FIG. 4, chip C M The corners a1, a2, a3, and a4 of the chip C P These correspond to corners b1, b2, b3, and b4.

[0049] Figure 5 shows the chip C M FIG. 5 is a schematic bottom view showing a configuration example of the laminated electrode P I1 6 and 7 are schematic cross-sectional views showing a part of the configuration of the memory die MD. M8 is a schematic bottom view showing a part of the configuration of the chip C. In FIG. 8, the left side region shows an XY cross section at a height position corresponding to the word line WL, and the right side region shows an XY cross section at a height position corresponding to the drain side selection gate line SGD. In addition, in the right side region of FIG. 8, via contact electrodes ch, Vy, and bit lines BL are also shown to show the connection portion between the semiconductor layer 120 and the bit lines BL. Via contact electrodes ch, Vy, and bit lines BL are also provided in the left side region of FIG. 8. FIG. 9 shows the chip C. M 9 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor layer 120. Although Fig. 9 shows a YZ cross section, a structure similar to that of Fig. 9 can be observed even when a cross section other than the YZ cross section along the central axis of the semiconductor layer 120 (for example, an XZ cross section) is observed.

[0050] [Chip C M Structure of In the example of FIG. 5, chip C M 5, each of the four memory planes MP0 to MP3 includes a plurality of memory blocks BLK arranged in the Y direction. In the example of FIG. 5, each of the four memory planes MP0 to MP3 includes a hook-up region R HU and a memory hole region R MH (memory area). M The peripheral region R is provided on one end side in the Y direction from the four memory planes MP0 to MP3. P Equipped with.

[0051] In the illustrated example, the hook-up region R HU are provided at both ends of the memory plane MP in the X direction. However, this configuration is merely an example, and the specific configuration can be appropriately adjusted. For example, the hook-up region R HU The hook-up region R may be provided at one end of the memory plane MP in the X direction, not at both ends of the memory plane MP in the X direction. HUmay be provided at the center position or near the center position in the X direction of the memory plane MP.

[0052] Chip C M For example, as shown in FIG. SB and the substrate layer L SB A memory cell array layer L MCA and the memory cell array layer L MCA a via contact electrode layer CH provided below the via contact electrode layer CH, a plurality of wiring layers M0, M1 provided below the via contact electrode layer CH, and a chip bonding electrode layer MB provided below the wiring layers M0, M1.

[0053] [Chip C M Base layer L SB Structure of For example, as shown in FIG. SB The memory cell array layer L MCA The semiconductor device comprises a conductive layer 100 provided on the upper surface of the substrate, an insulating layer 101 provided on the upper surface of the conductive layer 100, a back surface wiring layer MA provided on the upper surface of the insulating layer 101, and an insulating layer 102 provided on the upper surface of the back surface wiring layer MA.

[0054] The conductive layer 100 may include, for example, a semiconductor layer such as silicon (Si) doped with an N-type impurity such as phosphorus (P) or a P-type impurity such as boron (B), may include a metal such as tungsten (W), or may include a silicide such as tungsten silicide (WSi).

[0055] The conductive layer 100 functions as a part of the source line SL (FIG. 1). Four conductive layers 100 are provided corresponding to the four memory planes MP0 to MP3 (FIG. 5). A region VZ not including the conductive layer 100 is provided at the ends of the memory plane MP in the X direction and the Y direction.

[0056] The insulating layer 101 includes, for example, silicon oxide (SiO2).

[0057] The back wiring layer MA includes a plurality of wirings ma. These wirings ma may include, for example, aluminum (Al).

[0058] Some of the multiple wirings ma function as part of the source lines SL (FIG. 2). Four of these wirings ma are provided corresponding to the four memory planes MP0 to MP3 (FIG. 5). Each of these wirings ma is electrically connected to the conductive layer 100.

[0059] In addition, some of the wirings ma are connected to the external pad electrodes P X This wiring ma functions as a P The wiring ma is provided in the memory cell array layer L in the region VZ not including the conductive layer 100. MCA The wiring ma is connected to a via contact electrode CC in the insulating layer 102. A part of the wiring ma is exposed to the outside of the memory die MD through an opening TV provided in the insulating layer 102.

[0060] The insulating layer 102 is, for example, a passivation layer made of an insulating material such as polyimide.

[0061] [Chip C M The memory cell array layer L MCA Memory hole region R MH Structure in As described with reference to FIG. MCA 6, a plurality of memory blocks BLK arranged in the Y direction are provided. An inter-block insulating layer ST such as silicon oxide (SiO2) is provided between two memory blocks BLK adjacent to each other in the Y direction. A plurality of stacked structures including a plurality of conductive layers 110 arranged in the Z direction and arranged in the Y direction correspond to a plurality of memory blocks BLK.

[0062] 6, the memory block BLK includes a plurality of conductive layers 110 arranged in the Z direction and a plurality of semiconductor layers 120 extending in the Z direction. Also, as shown in FIG 9, a gate insulating film 130 is provided between each of the conductive layers 110 and the semiconductor layers 120.

[0063] The conductive layer 110 has a generally plate-like shape extending in the X-direction. The conductive layer 110 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W) or molybdenum (Mo). The conductive layer 110 may also include polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An interlayer insulating layer 111 such as silicon oxide (SiO2) is provided between the multiple conductive layers 110 arranged in the Z-direction.

[0064] Of the multiple conductive layers 110, one or more conductive layers 110 located in the uppermost layer function as the gate electrode of the source side select transistor STS (FIG. 2) and the source side select gate line SGS (see FIG. 6). These multiple conductive layers 110 are electrically independent for each memory block BLK.

[0065] Further, a plurality of conductive layers 110 positioned below this function as gate electrodes of memory cells MC (FIG. 2) and word lines WL. These plurality of conductive layers 110 are each electrically independent for each memory block BLK.

[0066] In addition, one or more conductive layers 110 located below the above function as the gate electrode of the drain side select transistor STD and the drain side select gate line SGD. For example, as shown in FIG. 8, the width Y SGD is the width Y in the Y direction of the conductive layer 110 functioning as the word line WL. WL In addition, an inter-string unit insulating layer SHE made of silicon oxide (SiO 2 ) or the like is provided between two conductive layers 110 adjacent to each other in the Y direction.

[0067] The semiconductor layers 120 are arranged in a predetermined pattern in the X and Y directions, for example, as shown in FIG. 8. Each of the semiconductor layers 120 functions as a channel region of a plurality of memory cells MC and select transistors (STD, STS) included in one memory string MS (FIG. 2). The semiconductor layer 120 includes, for example, polycrystalline silicon (Si) or the like. The semiconductor layer 120 has a substantially cylindrical shape, and an insulating layer 125 such as silicon oxide is provided in the central portion. The outer peripheral surfaces of the semiconductor layers 120 are surrounded by a plurality of conductive layers 110, and face these plurality of conductive layers 110.

[0068] Moreover, an impurity region (not shown) is provided at the upper end of the semiconductor layer 120. This impurity region is connected to the conductive layer 100 (see FIG. 6). This impurity region contains, for example, an N-type impurity such as phosphorus (P) or a P-type impurity such as boron (B).

[0069] In addition, an impurity region (not shown) is provided at the lower end of the semiconductor layer 120. This impurity region is connected to the bit line BL through a via contact electrode ch and a via contact electrode Vy. This impurity region contains an N-type impurity such as phosphorus (P).

[0070] The gate insulating film 130 has a substantially cylindrical shape covering the outer peripheral surface of the semiconductor layer 120, as shown in FIG. 8, for example. The gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133 stacked between the semiconductor layer 120 and the conductive layer 110, as shown in FIG. 9, for example. The tunnel insulating film 131 and the block insulating film 133 include, for example, silicon oxide (SiO2), silicon oxynitride (SiON), or the like. The charge storage film 132 includes, for example, a film capable of storing charge, such as silicon nitride (SiN). The tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120 except for the contact portion between the semiconductor layer 120 and the conductive layer 100.

[0071] 9 shows an example in which the gate insulating film 130 includes a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may include a floating gate such as polycrystalline silicon containing N-type or P-type impurities.

[0072] [Chip C M The memory cell array layer L MCA Hookup area R HU Structure in As shown in Figure 7, the hook-up area R HU A plurality of via contact electrodes CC are provided in the conductive layer 110. Each of the plurality of via contact electrodes CC extends in the Z direction, and is connected at its upper end to the conductive layer 110 (WL, SGD, SGS).

[0073] [Chip C M The memory cell array layer L MCA The surrounding area R P Structure in Surrounding area R P For example, as shown in FIG. X A plurality of via contact electrodes CC are provided corresponding to the external pad electrodes P X is connected to [Via contact electrode layer CH structure]

[0074] The via contact electrodes ch included in the via contact electrode layer CH are, for example, MCA Internal configuration and chip C P The semiconductor device is electrically connected to at least one of the components.

[0075] The via contact electrode layer CH includes a plurality of via contact electrodes ch. The plurality of via contact electrodes ch may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The via contact electrodes ch are provided corresponding to the plurality of semiconductor layers 120 and are connected to the lower ends of the plurality of semiconductor layers 120.

[0076] [Chip C M [Structure of wiring layers M0 and M1] The wiring layers M0 and M1 include, for example, a memory cell array layer L MCA Internal configuration and chip C P The semiconductor device is electrically connected to at least one of the components.

[0077] The wiring layer M0 includes a plurality of wirings m0. The plurality of wirings m0 may include, for example, a barrier conductive film such as titanium nitride (TiN), tantalum nitride (TaN), or a laminated film of tantalum nitride (TaN) and tantalum (Ta), and a laminated film of a metal film such as copper (Cu). Some of the plurality of wirings m0 function as bit lines BL. The bit lines BL are arranged in the X direction and extend in the Y direction, as shown in FIG. 8, for example.

[0078] The wiring layer M1 includes a plurality of wirings m1, as shown in Fig. 6. The plurality of wirings m1 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The plurality of wirings m1 are electrically connected to the wiring m0 through a via contact electrode V1, as shown in Figs. 6 and 7.

[0079] [Chip bonding electrode layer MB structure] The plurality of wirings included in the chip bonding electrode layer MB are, for example, MCA Internal configuration and chip C P The semiconductor device is electrically connected to at least one of the components.

[0080] The chip bonding electrode layer MB is made up of multiple bonding electrodes P I1 (Adhesive pad). These multiple adhesive electrodes P I1 For example, the barrier conductive film p is made of titanium nitride (TiN), tantalum nitride (TaN), or a laminated film of tantalum nitride (TaN) and tantalum (Ta). I1B and copper (Cu) and other metal films I1M The insulating film may include a laminated film.

[0081] Also, Chip C P As shown in FIG. 6, for example, the semiconductor substrate 200 includes a semiconductor substrate 200, an electrode layer GC provided above the semiconductor substrate 200, wiring layers D0, D1, D2, D3, and D4 provided above the electrode layer GC, and a chip bonding electrode layer DB provided above the wiring layers D0, D1, D2, D3, and D4.

[0082] [Chip C P Structure of the semiconductor substrate 200 The semiconductor substrate 200 includes P-type silicon (Si) containing P-type impurities such as boron (B). On the surface of the semiconductor substrate 200, an N-type well region 200N containing N-type impurities such as phosphorus (P), a P-type well region 200P containing P-type impurities such as boron (B), a semiconductor substrate region 200S in which the N-type well region 200N and the P-type well region 200P are not provided, and an insulating region STI are provided. A part of the P-type well region 200P is provided in the semiconductor substrate region 200S, and a part of the P-type well region 200P is provided in the N-type well region 200N. The N-type well region 200N, the P-type well region 200P provided in the N-type well region 200N and the semiconductor substrate region 200S, and the semiconductor substrate region 200S function as a part of a plurality of transistors Tr and a plurality of capacitors, etc., which constitute the peripheral circuit PC, respectively. A part of the plurality of transistors Tr functions as a word line switch WLSW. The insulating region STI includes, for example, silicon oxide (SiO 2 ) or the like, and is provided so as to extend from the surface of the semiconductor substrate 200 in the Z direction.

[0083] [Chip C P [Structure of electrode layer GC] An electrode layer GC is provided on the upper surface of the semiconductor substrate 200 with an insulating layer 200G interposed therebetween. The electrode layer GC includes a plurality of electrodes gc facing the surface of the semiconductor substrate 200. Furthermore, each region of the semiconductor substrate 200 and the plurality of electrodes gc included in the electrode layer GC are connected to a via contact electrode CS, respectively.

[0084] The N-type well region 200N of the semiconductor substrate 200, the P-type well region 200P provided in the N-type well region 200N and the semiconductor substrate region 200S, and the semiconductor substrate region 200S each function as a channel region of a plurality of transistors Tr constituting the peripheral circuit PC and one electrode of a plurality of capacitors, etc.

[0085] The electrodes gc included in the electrode layer GC function as gate electrodes of the transistors Tr constituting the peripheral circuit PC, the other electrodes of the capacitors, and the like.

[0086] The via contact electrode CS extends in the Z direction, and its lower end is connected to the upper surface of the semiconductor substrate 200 or the electrode gc. An impurity region containing N-type impurities or P-type impurities is provided at the connection portion between the via contact electrode CS and the semiconductor substrate 200. The via contact electrode CS may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0087] [Chip C P [Structure of wiring layers D0, D1, D2, D3, and D4] For example, as shown in FIG. 6, a plurality of connection parts and a plurality of wirings included in D0, D1, D2, D3, and D4 are, for example, a memory cell array layer L MCA Internal configuration and chip C P The semiconductor device is electrically connected to at least one of the components.

[0088] The wiring layers D0, D1, and D2 each include a plurality of connection parts d0, d1, and d2 and a plurality of wirings. The plurality of connection parts d0, d1, and d2 and the plurality of wirings may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0089] The wiring layers D3 and D4 each include a plurality of connection parts d3 and d4 and a plurality of wirings. The plurality of connection parts d3 and d4 and the plurality of wirings may include a barrier conductive film such as titanium nitride (TiN), tantalum nitride (TaN), or a laminated film of tantalum nitride (TaN) and tantalum (Ta), and a laminated film of a metal film such as copper (Cu), etc.

[0090] [Chip bonding electrode layer DB structure] The plurality of wirings included in the chip bonding electrode layer DB are, for example, MCA Internal configuration and chip C P The semiconductor device is electrically connected to at least one of the components.

[0091] The chip bonding electrode layer DB is made up of a plurality of bonding electrodes P I2 These multiple laminated electrodes P I2 For example, the barrier conductive film p is made of titanium nitride (TiN), tantalum nitride (TaN), or a laminated film of tantalum nitride (TaN) and tantalum (Ta). I2B and copper (Cu) and other metal films I2M The insulating film may include a laminated film.

[0092] In addition, the bonded electrode P I1 and the laminated electrode P I2 In addition, metal films such as copper (Cu) I1M ,p I2M Using this, the metal film p I1M and metal film p I2M However, the alignment error of the laminated electrode P due to the alignment error is small. I1 and the laminated electrode P I2 Distortion of the shape of the laminated conductive film p I1B ,p I2B The bonded structure can be confirmed by the positional misalignment (the occurrence of discontinuous parts on the side). I1 and laminated electrode P I2 When the laminated electrode P is formed by the damascene method, each side surface has a tapered shape. I1 and the laminated electrode P I2The cross-sectional shape along the Z direction at the portion where the laminated electrodes P are laminated together is not a straight line, but a non-rectangular shape. I1 and the laminated electrode P I2 When these are bonded together, the bottom, sides, and top of each Cu that forms them are covered with barrier metal. In contrast, in a typical wiring layer that uses Cu, an insulating layer (SiN or SiCN, etc.) that has the function of preventing oxidation of Cu is provided on the top surface of the Cu, and no barrier metal is provided. For this reason, even if there is no misalignment in the bonding, it is possible to distinguish it from a typical wiring layer.

[0093] [Transistor Tr structure] Fig. 10 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device according to the first embodiment. Fig. 10 shows an example of the structure of a plurality of transistors Tr provided in a semiconductor substrate region 200S according to the present embodiment.

[0094] 10, the surface of the semiconductor substrate 200 is provided with P-type well regions 310a, 310 containing P-type impurities such as boron (B), N-type well regions 311a, 311 containing N-type impurities such as phosphorus (P), a semiconductor substrate region 200S in which the N-type well regions 311a, 311 and the P-type well regions 310a, 310 are not provided, and an insulating region STI. The P-type well regions 310a, 310 are an example of the P-type well region 200P described with reference to FIG. 6. The N-type well regions 311a, 311 are an example of the N-type well region 200N described with reference to FIG. 6.

[0095] As described with reference to FIGS. 6 and 7, chip C P A plurality of transistors Tr are provided on the semiconductor substrate 200. The plurality of transistors Tr include a plurality of N-type high-voltage transistors Tr NH and multiple P-type high-voltage transistors Tr PH and multiple N-type low-voltage transistors Tr NL and multiple P-type low-voltage transistors Tr PL and P-type high voltage transistor Tr PHand N-type low-voltage transistor Tr NL and P-type low-voltage transistor Tr PL The high voltage transistor Tr NH The high-voltage transistor Tr NH ,Tr PH For example, a voltage greater than 10 V may be supplied to the high-voltage transistor Tr. NH For example, the two transistors T WLS ,T WLU is a high voltage transistor Tr NH For example, the six transistors T DRV1 ~T DRV6 Also, high voltage transistor Tr NH This is achieved by:

[0096] Hereinafter, N-type high-voltage transistor Tr NH , P-type high voltage transistor Tr PH , N-type low-voltage transistor Tr NL and P-type low-voltage transistor Tr PL The structure of each will be explained in order.

[0097] [High voltage transistor Tr NH Structure of FIG. 11 shows an N-type high-voltage transistor Tr according to the first embodiment. NH 12 is a schematic plan view showing the structure of an N-type high-voltage transistor Tr according to the first embodiment. NH 12 is a schematic cross-sectional view showing the structure of the N-type high-voltage transistor Tr according to the first embodiment. Note that Fig. 12 is a cross-sectional view of the structure shown in Fig. 11 taken along the dotted line AA'. Fig. 13 is a schematic cross-sectional view showing the structure of the N-type high-voltage transistor Tr according to the first embodiment. NH FIG. 14 is a diagram for explaining the impurity concentration of the N-type high-voltage transistor Tr according to the first embodiment. NH13. Fig. 14 is a cross-sectional view showing a part of the structure of Fig. 13. Fig. 15 is a conceptual diagram showing the impurity concentration along the dotted line AA' in the region shown in Fig. 11. Fig. 15 shows the impurity concentration of N-type impurities such as phosphorus (P) and arsenic (As).

[0098] High voltage transistor Tr NH As shown in FIG. 12, the high-voltage transistor Tr NH 12 and 14, includes a part of the semiconductor substrate region 200S, a gate insulating film 241 such as silicon oxide (SiO2) provided on the surface of the semiconductor substrate 200, a gate electrode member 243 such as polycrystalline silicon (Si) provided on the upper surface of the gate insulating film 241, a gate electrode member 244 such as tungsten (W) provided on the upper surface of the gate electrode member 243, a cap insulating layer 245 such as silicon oxide (SiO2) or silicon nitride (Si3N4) provided on the upper surface of the gate electrode member 244, and a sidewall insulating film 246 such as silicon oxide (SiO2) or silicon nitride (Si3N4) provided on the side surface in the X direction or Y direction of the gate electrode member 243, the gate electrode member 244, and the cap insulating layer 245. The gate electrode member 243 contains, for example, an N-type impurity such as phosphorus (P) or arsenic (As), or a P-type impurity such as boron (B). The gate electrode member 243 and the gate electrode member 244 are one of the multiple electrodes gc described with reference to Fig. 6 etc., and function as the gate electrode 201 provided on the gate insulating film 241. The gate insulating film 241 is one of the multiple insulating layers 200G described with reference to Fig. 6 etc.

[0099] High voltage transistor Tr NH 12 and 14, includes a liner insulating layer 247 made of silicon oxide (SiO2) or the like and a liner insulating layer 248 made of silicon nitride (Si3N4) or the like, which are laminated on the surface of the semiconductor substrate 200, the side surface in the X direction or the Y direction of the gate insulating film 241, the side surface in the X direction or the Y direction of the sidewall insulating film 246, and the upper surface of the cap insulating layer 245.

[0100] High voltage transistor Tr NH 12, a via contact electrode CS extending in the Z direction is connected to the semiconductor substrate 200. The via contact electrode CS may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The via contact electrode CS penetrates the liner insulating layer 247 and the liner insulating layer 248 and is connected to the surface of the semiconductor substrate 200. NH The gate electrode 244 functions as a source electrode or a drain electrode of the high-voltage transistor Tr. A via contact electrode CS (not shown) may penetrate the liner insulating layer 248, the liner insulating layer 247, and the cap insulating layer 245 and be connected to the upper surface of the gate electrode member 244. NH It functions as a part of the gate electrode.

[0101] High voltage transistor Tr NH 12 and the like, has a channel region 206 on the surface of the semiconductor substrate 200 facing the gate electrode member 243. In other words, the channel region 206 is a region included in the semiconductor substrate 200 and provided at a position overlapping the gate electrode 201 when viewed from the Z direction intersecting the surface of the semiconductor substrate 200. Also, as shown in, for example, FIGS. 11 and 12 and the like, a high concentration N-diffusion layer 202, a low concentration N-diffusion layer 203, and an N+ diffusion layer 204 are provided on the surface of the semiconductor substrate 200. For example, in FIG. 11, the high concentration N-diffusion layer 202, the low concentration N-diffusion layer 203, and the N+ diffusion layer 204 on the left side function as a source region, and the high concentration N-diffusion layer 202, the low concentration N-diffusion layer 203, and the N+ diffusion layer 204 on the right side function as a drain region.

[0102] The N+ diffusion layer 204 is a diffusion layer region that is included in the semiconductor substrate 200, is connected to a via contact electrode CS extending in the Z direction, and contains a first conductive type impurity. The first conductive type impurity is, for example, an N-type impurity such as phosphorus (P) or arsenic (As). The impurity concentration of the N-type impurity contained in the N+ diffusion layer 204 is higher than the impurity concentrations of the N-type impurities contained in the high concentration N- diffusion layer 202 and the low concentration N- diffusion layer 203.

[0103] The high-concentration N-diffusion layer 202 is a diffusion layer region that is included in the semiconductor substrate 200 and is provided between the channel region 206 and the N+ diffusion layer 204 and contains a first conductive type impurity. At least a part of the high-concentration N-diffusion layer 202 is provided at a position overlapping the sidewall insulating film 246 when viewed from the Z direction. The b region shown in FIG. 14 is a region that is provided at a position overlapping the channel region 206 when viewed from the Z direction, and may be called an overlap region. The impurity concentration of the N-type impurity included in the high-concentration N-diffusion layer 202 is higher than the impurity concentration of the N-type impurity included in the low-concentration N-diffusion layer 203. The impurity concentration of the N-type impurity included in the high-concentration N-diffusion layer 202 is lower than the impurity concentration of the N-type impurity included in the N+ diffusion layer 204.

[0104] The low-concentration N- diffusion layer 203 is included in the semiconductor substrate 200, is provided between the high-concentration N- diffusion layer 202 and the N+ diffusion layer 204, and is a diffusion layer region containing impurities of the first conductivity type, connected to the high-concentration N- diffusion layer 202.

[0105] Here, as shown in FIG. 15, the high-voltage transistor Tr shown in FIG. 11 and FIG. 12 is NH The peak of the impurity concentration of the low concentration N-diffusion layer 203 in 17 atoms / cm 3 On the other hand, the peak of the impurity concentration of the high-concentration N- diffusion layer 202 is, for example, 5 to 15×10 17 atoms / cm 3 The peak of the impurity concentration of the N+ diffusion layer 204 is, for example, 0.1 to 10×10 20 atoms / cm 3The region b shown in Figure 15 is the overlap region described above.

[0106] As shown in FIG. 11 and FIG. 14, the width L1 of the high concentration N- diffusion layer 202 in the Y direction is larger than the width L3 of the sidewall insulating film 246 in the Y direction. The distance L2 in the Y direction between the high concentration N- diffusion layer 202 and the N+ diffusion layer 204 is larger than the width L1 of the high concentration N- diffusion layer 202 in the Y direction. Here, the width L1 of the high concentration N- diffusion layer 202 in the Y direction is, for example, about 325 nm, but may be 250 nm or more and 450 nm or less. The width L3 of the sidewall insulating film 246 in the Y direction is, for example, about 60 nm, but may be 50 nm or more and 70 nm or less. Also, as shown in FIG. 14, the thickness T of the gate insulating film in the Z direction is, for example, about 42 nm, but may be 35 nm or more and 50 nm or less.

[0107] High voltage transistor Tr NH In this case, when 20V is applied to the drain electrode, 0V is applied to the gate electrode, and no voltage is applied to the source electrode, the source electrode is floating. In this state, when 25V is applied to the gate electrode, the high-voltage transistor Tr NH The high-voltage transistor Tr is turned on, and the voltage applied to the drain region is transferred to the source region. NH In this case, at the moment of transition from the off state to the on state, a large potential difference occurs between the drain region and the source region. As a result, the electric field in the vicinity of the drain region overlapping with the sidewall insulating film 246 when viewed from the Z direction becomes stronger, causing impact ionization and generating hot carriers (hot electrons).

[0108] High voltage transistor Tr NH In this case, hot carriers generated by impact ionization are trapped in the insulating films (in the gate insulating film 241, the liner insulating layer 247, and the liner insulating layer 248) near the sidewall insulating film 246 included in region a in FIG.

[0109] In addition, the high voltage transistor Tr NHThe channel region 206 of the high-voltage transistor Tr NH If it is desired to set the threshold voltage, which is the gate-source voltage at which the transistor transitions from an off state to an on state, to a positive value, a P-type impurity such as boron (B) may be introduced into the channel region 206. On the other hand, if it is desired to set this threshold voltage to a negative value, an N-type impurity such as arsenic may be introduced into the channel region 206. In this way, the high-voltage transistor Tr NH By introducing P-type or N-type impurities into the channel region 206, the threshold voltage can be adjusted.

[0110] [P-type high-voltage transistor Tr PH Structure of FIG. 16 shows the P-type high-voltage transistor Tr PH FIG. 1 is a schematic cross-sectional view showing the structure of a P-type high-voltage transistor Tr PH 16, the P-type high-voltage transistor Tr is provided in an N-type well region 311 of a semiconductor substrate 200. PHincludes a part of the N-type well region 311, a gate insulating film 251 such as silicon oxide (SiO2) provided on the surface of the N-type well region 311 (semiconductor substrate 200), a gate electrode member 253 such as polycrystalline silicon (Si) provided on the upper surface of the gate insulating film 251, a gate electrode member 254 such as tungsten (W) provided on the upper surface of the gate electrode member 253, a cap insulating layer 255 such as silicon oxide (SiO2) or silicon nitride (Si3N4) provided on the upper surface of the gate electrode member 254, and a sidewall insulating film 256 such as silicon oxide (SiO2) or silicon nitride (Si3N4) provided on the side surface in the X direction or Y direction of the gate electrode member 253, the gate electrode member 254, and the cap insulating layer 255. The gate electrode member 253 contains, for example, an N-type impurity such as phosphorus (P) or arsenic (As), or a P-type impurity such as boron (B). The gate electrode member 253 and the gate electrode member 254 are one of the multiple electrodes gc described with reference to FIG. 6 and the like, and function as a gate electrode provided on the gate insulating film 251. The gate insulating film 251 is one of the multiple insulating layers 200G described with reference to FIG. 6 and the like. PH The length (thickness) in the Z direction of the gate insulating film 251 is NH The length (thickness) of the gate insulating film in the Z direction is the same as that of the gate insulating film in the Z direction, and is, for example, about 42 nm, but may be 35 nm or more and 50 nm or less.

[0111] P-type high voltage transistor Tr PH 16 , includes a liner insulating layer 257 made of silicon oxide (SiO2) or the like and a liner insulating layer 258 made of silicon nitride (Si3N4) or the like, which are stacked on the surface of the N-type well region 311, the side surface in the X direction or the Y direction of the gate insulating film 251, the side surface in the X direction or the Y direction of the sidewall insulating film 256, and the upper surface of the cap insulating layer 255.

[0112] P-type high voltage transistor Tr PHA via contact electrode CS extending in the Z direction is connected to the P-type high-voltage transistor Tr. The via contact electrode CS penetrates the liner insulating layer 257 and the liner insulating layer 258 and is connected to the surface of the N-type well region 311. PH The gate electrode 244 functions as a source electrode or a drain electrode of the P-type high-voltage transistor Tr. A via contact electrode CS (not shown) may be connected to the upper surface of the gate electrode member 244 by penetrating the liner insulating layer 258, the liner insulating layer 257, and the cap insulating layer 255. PH It functions as a part of the gate electrode.

[0113] P-type high voltage transistor Tr PH has a channel region on the surface of the N-type well region 311 facing the gate electrode member 253. In other words, this channel region is included in the N-type well region 311 of the semiconductor substrate 200 and is provided at a position overlapping with the gate electrode when viewed from the Z direction. Also, as shown in Fig. 16, for example, a P+ diffusion layer 213 is provided on the surface of the N-type well region 311. In Fig. 16, the P+ diffusion layer 213 on the left side functions as a source region, and the P+ diffusion layer 213 on the right side functions as a drain region.

[0114] The P+ diffusion layer 213 is a diffusion layer region that is included in the N-type well region 311 of the semiconductor substrate 200, is connected to a via contact electrode CS extending in the Z direction, and contains a second conductive type impurity. The second conductive type impurity is, for example, a P-type impurity such as boron (B).

[0115] In addition, the P-type high-voltage transistor Tr PH is a high voltage transistor Tr NH Unlike the above, it does not have a diffusion layer corresponding to the high concentration N-diffusion layer 202.

[0116] [N-type low-voltage transistor Tr NL Structure of FIG. 17 shows the N-type low-voltage transistor Tr NLFIG. 1 is a schematic cross-sectional view showing the structure of an N-type low-voltage transistor Tr NL 17, the N-type low-voltage transistor Tr is provided in a P-type well region 310 of a semiconductor substrate 200. NL The gate insulating film 341 includes a part of the P-type well region 310, a gate insulating film 341 such as silicon oxide (SiO2) provided on the surface of the P-type well region 310 (semiconductor substrate 200), a gate electrode member 343 such as polycrystalline silicon (Si) provided on the upper surface of the gate insulating film 341, a gate electrode member 344 such as tungsten (W) provided on the upper surface of the gate electrode member 343, a cap insulating layer 345 such as silicon oxide (SiO2) or silicon nitride (Si3N4) provided on the upper surface of the gate electrode member 344, and a sidewall insulating film 346 such as silicon oxide (SiO2) or silicon nitride (Si3N4) provided on the side surface in the X direction or Y direction of the gate electrode member 343, the gate electrode member 344, and the cap insulating layer 345. The gate electrode member 343 contains, for example, an N-type impurity such as phosphorus (P) or arsenic (As), or a P-type impurity such as boron (B). The gate electrode member 343 and the gate electrode member 344 are one of the electrodes gc described with reference to FIG. 6 and function as a gate electrode provided on the gate insulating film 341. The gate insulating film 341 is one of the insulating layers 200G described with reference to FIG. 6. NL The length (thickness) in the Z direction of the gate insulating film 341 is NH It may be smaller than the length (thickness) in the Z direction of the gate insulating film, for example, 6 nm or more and 8 nm or less.

[0117] N-type low-voltage transistor Tr NL includes a liner insulating layer 347 made of silicon oxide (SiO2) or the like and a liner insulating layer 348 made of silicon nitride (Si3N4) or the like, which are stacked on the surface of the P-type well region 310, the side surface in the X direction or the Y direction of the gate insulating film 341, the side surface in the X direction or the Y direction of the sidewall insulating film 346, and the upper surface of the cap insulating layer 345.

[0118] N-type low-voltage transistor Tr NLA via contact electrode CS extending in the Z direction is connected to the P-type well region 310. The via contact electrode CS penetrates the liner insulating layer 347 and the liner insulating layer 348 and is connected to the surface of the P-type well region 310. NL The gate electrode 344 functions as a source electrode or a drain electrode of the gate electrode member 344. A via contact electrode CS (not shown) may penetrate the liner insulating layer 348, the liner insulating layer 347, and the cap insulating layer 345 and be connected to the upper surface of the gate electrode member 344. The via contact electrode CS (not shown) may be connected to the upper surface of the gate electrode member 344. NL It functions as a part of the gate electrode.

[0119] In addition, the N-type low-voltage transistor Tr NL has a channel region on the surface of the P-type well region 310 facing the gate electrode member 343. In other words, this channel region is included in the P-type well region 310 of the semiconductor substrate 200 and is provided at a position overlapping with the gate electrode when viewed from the Z direction. Also, as shown in Figures 10 and 17, for example, an N+ diffusion layer 303 is provided on the surface of the P-type well region 310. In Figure 17, the N+ diffusion layer 303 on the left side functions as a source region, and the N+ diffusion layer 303 on the right side functions as a drain region.

[0120] The N+ diffusion layer 303 is included in the P-type well region 310 of the semiconductor substrate 200, is connected to a via contact electrode CS extending in the Z direction, and is a diffusion layer region containing a first conductivity type impurity. NL The distance from the channel region of the N-type high-voltage transistor Tr NH The distance is smaller than the distance from the channel region 206 to the via contact electrode CS.

[0121] In addition, the N-type low-voltage transistor Tr NL is a high voltage transistor Tr NH Unlike the above, it does not have a diffusion layer corresponding to the high concentration N-diffusion layer 202.

[0122] [P-type low-voltage transistor Tr PL Structure of FIG. 18 shows a P-type low-voltage transistor Tr PL FIG. 1 is a schematic cross-sectional view showing the structure of a P-type low-voltage transistor Tr PL 18, the P-type low-voltage transistor Tr is provided in an N-type well region 311a of the semiconductor substrate 200. PL includes a part of the N-type well region 311a, a gate insulating film 351 such as silicon oxide (SiO2) provided on the surface of the N-type well region 311a (semiconductor substrate 200), a gate electrode member 353 such as polycrystalline silicon (Si) provided on the upper surface of the gate insulating film 351, a gate electrode member 354 such as tungsten (W) provided on the upper surface of the gate electrode member 353, a cap insulating layer 355 such as silicon oxide (SiO2) or silicon nitride (Si3N4) provided on the upper surface of the gate electrode member 354, and a sidewall insulating film 356 such as silicon oxide (SiO2) or silicon nitride (Si3N4) provided on the side surface in the X direction or Y direction of the gate electrode member 353, the gate electrode member 354, and the cap insulating layer 355. The gate electrode member 353 contains, for example, an N-type impurity such as phosphorus (P) or arsenic (As), or a P-type impurity such as boron (B). The gate electrode member 353 and the gate electrode member 354 are one of the multiple electrodes gc described with reference to FIG. 6 and the like, and function as a gate electrode provided on the gate insulating film 351. The gate insulating film 351 is one of the multiple insulating layers 200G described with reference to FIG. 6 and the like. PL The length (thickness) of the gate insulating film 351 in the Z direction is NH It may be smaller than the length (thickness) in the Z direction of the gate insulating film, for example, 6 nm or more and 8 nm or less.

[0123] P-type low-voltage transistor Tr PLincludes a liner insulating layer 357 made of silicon oxide (SiO2) or the like and a liner insulating layer 358 made of silicon nitride (Si3N4) or the like, which are stacked on the surface of the N-type well region 311a, the side surface of the gate insulating film 351 in the X direction or the Y direction, the side surface of the sidewall insulating film 356 in the X direction or the Y direction, and the upper surface of the cap insulating layer 355.

[0124] P-type low-voltage transistor Tr PL A via contact electrode CS extending in the Z direction is connected to the P-type low-voltage transistor Tr. The via contact electrode CS penetrates the liner insulating layer 357 and the liner insulating layer 358 and is connected to the surface of the N-type well region 311a. PL The gate electrode 354 functions as a source electrode or a drain electrode of the P-type low-voltage transistor Tr. A via contact electrode CS (not shown) may be connected to the upper surface of the gate electrode member 354 by penetrating the liner insulating layer 358, the liner insulating layer 357, and the cap insulating layer 355. PL It functions as a part of the gate electrode.

[0125] P-type low-voltage transistor Tr PL has a channel region on the surface of the N-type well region 311a facing the gate electrode member 353. In other words, this channel region is included in the N-type well region 311a of the semiconductor substrate 200 and is provided at a position overlapping with the gate electrode when viewed from the Z direction. Also, as shown in Figures 10 and 18, for example, a P+ diffusion layer 313 is provided on the surface of the N-type well region 311a. In Figure 18, the P+ diffusion layer 313 on the left side functions as a source region, and the P+ diffusion layer 313 on the right side functions as a drain region.

[0126] The P+ diffusion layer 313 is included in the N-type well region 311a of the semiconductor substrate 200, is connected to a via contact electrode CS extending in the Z direction, and is a diffusion layer region containing impurities of a second conductivity type. PL The distance from the channel region of the N-type high-voltage transistor Tr NHThe distance is smaller than the distance from the channel region 206 to the via contact electrode CS.

[0127] In addition, the P-type low-voltage transistor Tr PL is a high voltage transistor Tr NH Unlike the above, it does not have a diffusion layer corresponding to the high concentration N-diffusion layer 202.

[0128] [Effects of the first embodiment] The high-voltage transistor Tr NH In the case where the high-concentration N-diffusion layer 202 is not provided in the semiconductor substrate 200, the upper surface side of the low-concentration N-diffusion layer 203 in the Z direction is easily depleted. That is, the liner insulating layer 248, such as silicon nitride (Si3N4), is likely to trap electrons, and therefore the liner insulating layer 248 is likely to trap hot carriers generated by impact ionization at a position overlapping the high-concentration N-diffusion layer 202 as viewed from the Z direction. For this reason, the position on the surface of the semiconductor substrate 200 where the low-concentration N-diffusion layer 203 is provided is likely to be depleted. As a result, the high-voltage transistor Tr NH When the high-voltage transistor Tr NH There is a risk that the current flowing through the

[0129] Therefore, the high-voltage transistor Tr NH In the case where the high-concentration N-diffusion layer 202 is not provided and the impurity concentration of the low-concentration N-diffusion layer 203 is uniformly increased, a problem occurs in that the breakdown voltage deteriorates when a high voltage is applied to the drain region. NHWhen 0V is applied to the gate electrode and a high voltage is applied to the drain electrode, a high voltage is applied to the N+ diffusion layer 204 in the drain region (on the right side in FIG. 13). At this time, the Y-direction region of the N+ diffusion layer 204 and the low-concentration N- diffusion layer 203 can be simulated as a series resistor connecting the nodes n1 and n2, and a voltage drop occurs, so that the potential of the node n2 when the electrons are used as the reference is greater than the potential of the node n1 when the electrons are used as the reference. If the impurity concentration of the low-concentration N- diffusion layer 203 is increased uniformly, the voltage drop at the node n2 becomes smaller and the voltage difference between the source and drain is concentrated in the channel region 206, so that the high-voltage transistor Tr NH The breakdown voltage of the

[0130] In contrast, as shown in FIG. 13, the high-voltage transistor Tr NH In this example, a high-concentration N-type diffusion layer 202 is provided at node n1. This maintains the impurity concentration of the low-concentration N-type diffusion layer 203 and the potential at node n2, so that the high-voltage transistor Tr NH In addition, the high-voltage transistor Tr according to the present embodiment can be prevented or suppressed from deteriorating in withstand voltage. NH In the case of the high-concentration N-diffusion layer 202, the impurity concentration at the node n2 can be increased. This allows the high-voltage transistor Tr NH When the high-voltage transistor Tr NH Therefore, the decrease in the current flowing through the capacitor can be suppressed.

[0131] In addition, the high voltage transistor Tr NH In the present embodiment, a high-concentration N-diffusion layer 202 is provided in a region including a position about 250 nm away from the gate electrode 201 (channel region 206) in the channel direction (for example, the Y direction) where impact ionization occurs.

[0132] [Modification of the first embodiment] FIG. 19 is a diagram showing a modified example of an N-type high-voltage transistor Tr NHA 12 are given the same reference numerals and redundant explanations will be omitted.

[0133] As shown in FIG. 19, an N-type high-voltage transistor Tr NHA represents the N-type high-voltage transistor Tr according to the first embodiment shown in FIG. NH 2 in that a P-diffusion layer 205 is provided.

[0134] The P-diffusion layer 205 is provided at a position overlapping the source region and the drain region when viewed from the Z direction and between the channel region 206 and the insulating region STI, and is a diffusion layer containing P-type impurities such as boron (B).

[0135] The P-diffusion layer 205 is an N-type high-voltage transistor Tr NHA The leakage current between the source region and the drain region of the N-type high-voltage transistor Tr NHA It is possible to suppress leakage current between the first transistor and another adjacent transistor.

[0136] [First embodiment of N-type high-voltage transistor Tr NH Manufacturing method thereof] Next, with reference to FIGS. 20 to 37, the N-type high-voltage transistor Tr according to the first embodiment will be described. NH A manufacturing method of the above will be described. Figs. 20 to 27 are schematic cross-sectional views for explaining the manufacturing method, and show a cross section corresponding to Fig. 10. Figs. 28, 30, 32, 33, 35, and 36 are schematic cross-sectional views for explaining the manufacturing method, and show a cross section corresponding to Fig. 12. Figs. 29, 31, and 34 are schematic plan views for explaining the manufacturing method, and show a plan view corresponding to Fig. 11. Fig. 37 is a schematic cross-sectional view for explaining the manufacturing method, and shows a cross section corresponding to Fig. 17.

[0137] First, as shown in FIG. 20, a P-type impurity such as boron (B) and an N-type impurity such as phosphorus (P) are implanted into the surface of the semiconductor substrate 200 (semiconductor substrate region 200S) to form the P-type well regions 310a, 310 and the N-type well regions 311a, 311. This process is performed, for example, by ion implantation. Specifically, a resist having an opening corresponding to the P-type well regions 310a, 310 is formed on the surface of the semiconductor substrate 200 (semiconductor substrate region 200S), and the P-type impurity such as boron (B) is introduced into the semiconductor substrate 200 (semiconductor substrate region 200S) by, for example, ion implantation. After the resist having an opening corresponding to the P-type well regions 310a, 310 is peeled off, a resist having an opening corresponding to the N-type well regions 311a, 311 is formed, and the N-type impurity such as phosphorus (P) is introduced into the semiconductor substrate 200 (semiconductor substrate region 200S) by, for example, ion implantation. Thereafter, the resist having openings corresponding to the N-type well regions 311a and 311 is peeled off. In this manner, the P-type well regions 310a and 310 and the N-type well regions 311a and 311 are formed. NH In order to adjust the threshold voltage, a P-type or N-type impurity may be introduced into a region of the semiconductor substrate 200 (semiconductor substrate region 200S) corresponding to the channel region 206.

[0138] Next, as shown in FIG. 21, for example, an insulating film 241a such as silicon oxide is formed on the upper surface of the semiconductor substrate 200. This step is performed by, for example, thermal oxidation. The insulating film 241a is formed to a thickness thinner than the thickness of the gate insulating film 241 (FIG. 12) in the Z direction. Next, a part of the insulating film 241a is removed. This step is performed by, for example, wet etching. In this step, the high-voltage transistor Tr NH ,Tr PH The insulating film 241a remains in the region corresponding to the low-voltage transistor Tr NL ,Tr PL The insulating film 241a is removed in the region corresponding to the above.

[0139] Next, as shown in FIG. 22, for example, an insulating film 341a such as silicon oxide is formed. This step is performed by, for example, thermal oxidation. The insulating film 341a is formed to the same thickness as the thickness in the Z direction of the gate insulating film 341 (FIG. 17). In this step, the high-voltage transistor Tr NH ,Tr PH In the corresponding regions, the insulating film 341a becomes thicker and reaches a thickness similar to that of the gate insulating film 241 (FIG. 12) in the Z direction.

[0140] Next, a conductive layer gcA of polycrystalline silicon (Si) is formed, for example, as shown in Fig. 23. This process is performed by, for example, CVD or the like.

[0141] Next, as shown in FIG. 24, for example, an opening STIA is formed at a position corresponding to the insulating region STI (FIG. 10). In this step, for example, the conductive layer gcA and the insulating films 241a, 341a at a position corresponding to the insulating region STI are removed, and the semiconductor substrate 200 is anisotropically etched to a depth of about 0.4 μm in the Z direction. The opening STIA extends in the Z direction and the X or Y direction, penetrates the conductive layer gcA and the insulating films 241a, 341a, and divides a part of the surface of the semiconductor substrate 200. This step is performed by a method such as RIE (Reactive Ion Etching).

[0142] Next, as shown in Fig. 25, for example, insulating regions STI are formed in the semiconductor substrate 200. This process is performed by, for example, CVD or the like. In this process, the opening STIA is filled with an insulating layer. Next, a part of the formed insulating layer is removed to form a plurality of insulating regions STI, for example, as shown in Fig. 25. The process of removing a part of the formed insulating layer is performed by, for example, a method such as CMP (Chemical Mechanical Polishing).

[0143] 26, a gate electrode member 243A such as polycrystalline silicon (Si), a gate electrode member 244A such as tungsten (W), and a cap insulating layer 245A such as silicon oxide (SiO2) or silicon nitride (Si3N4) are sequentially laminated on the upper surface of the conductive layer gcA. This process is performed by, for example, CVD.

[0144] Next, as shown in FIG. 27, the gate electrode member 243A, the gate electrode member 244A, and the cap insulating layer are removed from the region other than the region that will become the gate electrode. This process is performed by a method such as RIE. In this manner, the high-voltage transistor Tr NH The gate electrode member 243, the gate electrode member 244, and the cap insulating layer 245 of the high-voltage transistor Tr PH The gate electrode member 253, the gate electrode member 254, and the cap insulating layer 245 of the low-voltage transistor Tr NL The gate electrode member 343, the gate electrode member 344, and the cap insulating layer 345 of the low-voltage transistor Tr PL A gate electrode member 353, a gate electrode member 354 and a cap insulating layer 355 are then formed.

[0145] Next, as shown in, for example, FIG. 28 and FIG. 29, a high-voltage transistor Tr NH A resist 245r having an opening in a region corresponding to the entire surface is formed, and phosphorus (P) is ion-implanted to form a low-concentration N-diffusion layer 203. 12 atoms / cm 2 Alternatively, phosphorus (P) may be ion-implanted at a dose of 1000 .mu.m.

[0146] 30 and 31, a resist 202r is formed with openings in areas corresponding to the high concentration N-diffusion layer 202 and the cap insulating layer 245, and phosphorus (P) is ion-implanted. 12 atoms / cm 2As a result, in the region corresponding to the high concentration N-diffusion layer 202 in the semiconductor substrate 200 (the region between the resist 202r and the cap insulating layer 245 in FIG. 30), phosphorus (P) ions may be implanted at a dose of, for example, 6.3×10 12 atoms / cm 2 Since phosphorus (P) can be ion-implanted at a dose of 1000 .mu.m, a high-concentration N-diffusion layer 202 is formed.

[0147] Next, as shown in FIG. 32, for example, after removing the resist 202r, silicon oxide (SiO2) or silicon nitride (Si3N4) is deposited on the upper surface of the semiconductor substrate 200, the cap insulating layer 245, and the side surfaces of the gate electrode member 243, the gate electrode member 244, and the cap insulating layer 245 in the X direction or the Y direction, and anisotropic etching is performed to form the sidewall insulating film 246. At this time, the insulating film 241a is simultaneously removed from the source region and the drain region (active region) to form the gate insulating film 241. By removing the insulating film 241a by anisotropic etching, the gate insulating film 241 is formed without protruding from the end of the sidewall insulating film 256 when viewed from the Z direction. This makes it possible to make the junction depth in the Z direction of the N+ diffusion layer 204 described later shallow.

[0148] Next, as shown in, for example, FIGS. 33 and 34, a resist 204r having an opening in a region corresponding to the N+ diffusion layer 204 is formed, and the N+ diffusion layer 204 is formed by ion-implanting, for example, arsenic (As).

[0149] 35, after removing the resist 204r, a liner insulating layer 247 such as silicon oxide (SiO2) is formed on the surface of the semiconductor substrate 200, the side surface in the X direction or Y direction of the gate insulating film 241, the side surface in the X direction or Y direction of the sidewall insulating film 246, and the upper surface of the cap insulating layer 245. This process is performed by, for example, CVD or the like.

[0150] Next, as shown in FIG. 36, a liner insulating layer 248 such as silicon nitride (Si3N4) and a via contact electrode CS are formed to form a high-voltage transistor TrNH is formed.

[0151] When forming the resist 204r having an opening in the region corresponding to the N+ diffusion layer 204 described with reference to FIGS. 33 and 34, for example, as shown in FIG. 37, the low-voltage transistor Tr NL A resist 303r is formed with an opening in a corresponding region over the entire surface. Then, for example, arsenic (As) is ion-implanted to form an N+ diffusion layer 303.

[0152] N-type low-voltage transistor Tr NL In the case of the MOSFET, the speed performance is improved by shortening the gate length and increasing the current driving force. For this reason, it is important to maintain the resistance to the short channel effect. When arsenic (As) is ion-implanted, if the thickness of the insulating film 341a in the Z direction is large, the energy of the ion implantation must be increased. In this case, the junction depth of the N+ diffusion layer 303 in the Z direction becomes deep, and the N-type low-voltage transistor Tr NL On the other hand, if the insulating film 341a is removed when arsenic (As) is ion-implanted, the energy of the ion implantation can be reduced. In this case, the junction depth of the N+ diffusion layer 303 in the Z direction can be made shallow, so that the short channel effect resistance of the N-type low-voltage transistor Tr NL The short channel effect resistance of the semiconductor device can be improved.

[0153] In this embodiment, although not shown, when the sidewall insulating film 346 is formed by a process similar to that described with reference to FIG. 32, the insulating film 341a is simultaneously removed by anisotropic etching, so that the gate insulating film 341 is formed without protruding from the end of the sidewall insulating film 346 when viewed from the Z direction. This makes it possible to make the junction depth of the N+ diffusion layer 303 in the Z direction shallow. In other words, the N-type high-voltage transistor Tr can be manufactured without increasing the number of manufacturing processes. NH An N-type low-voltage transistor Tr NL The short channel effect resistance of the semiconductor device can be improved.

[0154] 33 and 34, a resist having an opening corresponding to the P+ diffusion layer 213 described with reference to Fig. 16 and the P+ diffusion layer 313 described with reference to Fig. 18 is formed, and boron (B) ions are implanted to simultaneously form the P+ diffusion layer 213 and the P+ diffusion layer 313. Since the insulating film 341a has been removed when boron (B) ions are implanted, the energy of the ion implantation can be reduced, and the junction depth in the Z direction of the P+ diffusion layer 213 and the P+ diffusion layer 313 can be made shallow.

[0155] [N-type high-voltage transistor Tr according to a modification of the first embodiment NHA Manufacturing method thereof] Next, referring to FIG. 38 and FIG. 39, a modified N-type high-voltage transistor Tr NHA 38 and 39 show a method for manufacturing an N-type high-voltage transistor Tr according to a modification of the first embodiment. NHA 20 is a schematic cross-sectional view for explaining the manufacturing method, showing a cross section corresponding to FIG. 19.

[0156] High voltage transistor Tr NHA Basically, it is a high-voltage transistor Tr NH It is manufactured similarly to.

[0157] However, after forming the liner insulating layer 247 as described with reference to FIG. NH A resist 205r having an opening in the whole may be formed. Then, for example, as shown in Fig. 38, a P-diffusion layer 205 may be formed by ion-implanting boron (B) into a region deeper in the Z direction than the regions of the high-concentration N-diffusion layer 202 and the low-concentration N-diffusion layer 203.

[0158] Then, as shown in FIG. 39, a liner insulating layer 248 such as silicon nitride (Si3N4) and a via contact electrode CS are formed to form a high-voltage transistor Tr NHA is formed.

[0159] In addition, when the high-concentration N-diffusion layer 202 is formed as described with reference to FIGS. 30 and 31, the high-voltage transistor Tr NH 35, for example, after forming the liner insulating layer 247, as shown in FIG. 40, a resist 205r may be formed with openings in the regions corresponding to the high-concentration N-diffusion layer 202 and the cap insulating layer 245, and phosphorus (P) may be ion-implanted. This not only makes it possible to suppress depletion of the upper side of the high-concentration N-diffusion layer 202 in the Z direction due to hot carriers, but also reduces the effective gate length of the high-voltage transistor Tr NH Therefore, the reduction in the effective gate length can be suppressed.

[0160] [Second embodiment] Next, referring to FIG. 41 and FIG. 42, a high-voltage N-type transistor Tr according to a second embodiment will be described. NH2 FIG. 41 shows an N-type high-voltage transistor Tr according to the second embodiment. NH2 FIG 42 is a schematic cross-sectional view showing the structure of an N-type high-voltage transistor Tr according to the second embodiment. NH2 12 and the like are given the same reference numerals and redundant explanations will be omitted.

[0161] High-voltage transistor Tr according to the first embodiment NH As described with reference to FIGS. 11 to 14, the N-type high-voltage transistor Tr according to the modification of the first embodiment is provided in the semiconductor substrate region 200S. NHA Similarly, the N-type high-voltage transistor Tr is provided in the semiconductor substrate region 200S. However, this configuration is merely an example. NH or N-type high voltage transistor Tr NHA may be provided in a region other than the semiconductor substrate region 200S.

[0162] For example, the peripheral circuit PC of the semiconductor memory device according to the second embodiment is basically configured similarly to the peripheral circuit PC of the semiconductor memory device according to the first embodiment. However, the peripheral circuit PC of the semiconductor memory device according to the second embodiment includes a plurality of N-type high-voltage transistors Tr NH (Fig. 12, etc.) or N-type high-voltage transistor Tr NHA (Fig. 19, etc.) instead of multiple N-type high-voltage transistors Tr NH2 (Figure 41)

[0163] N-type high-voltage transistor Tr according to the second embodiment NH2 FIG. 41 shows a typical N-type high-voltage transistor Tr according to the first embodiment. NH (Fig. 12, etc.) or N-type high-voltage transistor Tr NHA (FIG. 19, etc.). However, the N-type high-voltage transistor Tr NH2 is provided in the P-type well region 263p, not in the semiconductor substrate region 200S. NH2 The P-type well region 263p in which the N-type high-voltage transistor Tr according to this embodiment is provided is electrically isolated from the semiconductor substrate region 200S via the N-type well region 274n. NH2 The well region in which the above is provided will now be described in detail.

[0164] N-type high-voltage transistor Tr NH2 The channel region 206, the N+ diffusion layer 204, the high concentration N- diffusion layer 202, and the low concentration N- diffusion layer 203 are provided in the P-type well region 263p. As described above, the semiconductor substrate 200 (semiconductor substrate region 200S) is provided with an isolating N-type well region 274n for electrically isolating the P-type well region 263p from the semiconductor substrate region 200S. Since the P-type well region 263p is electrically isolated from the semiconductor substrate region 200S, a negative bias can be applied thereto.

[0165] The isolation N-type well region 274n is composed of three regions, an N-type well region 271n, an N-type well region 272n, and an N-type well region 273n. In addition to the P-type well region 263p, a P-type well region 261p and a P-type well region 262p are provided in the semiconductor substrate 200 (semiconductor substrate region 200S) within a region surrounded by the isolation N-type well region 274n.

[0166] The P-type well region 261p is provided below the P-type well region 263p. The P-type well region 262p is provided so as to surround the side surfaces (XY directions) of the P-type well region 263p when viewed from the Z direction.

[0167] The N-type well region 271n is provided below the P-type well region 261p. The N-type well region 272n is provided so as to surround the P-type well region 261p when viewed from the Z direction, and connects the N-type well region 271n and the N-type well region 273n. The N-type well region 273n is provided so as to surround the P-type well region 262p when viewed from the Z direction.

[0168] FIG. 43 shows an N-type high-voltage transistor Tr along the dotted line BB' in FIG. NH2 43 is a diagram conceptually illustrating the impurity concentration in the depth direction (Z direction) of the high-voltage transistor Tr shown in FIG. NH2 2 shows the impurity concentration when a P-diffusion layer 205 (not shown) is provided.

[0169] 41, a low concentration N-diffusion layer 203 is provided on the surface of the P-type well region 263p, and a P-diffusion layer 205 (not shown) is provided below the low concentration N-diffusion layer 203. For this reason, in the example shown in FIG. 43, the solid line having a peak near the surface of the P-type well region 263p indicates the impurity concentration of the low concentration N-diffusion layer 203, and the peak of the impurity concentration is, for example, 3 to 11×10 17 atoms / cm 3The dotted line having a peak at a depth of about 0.2 μm from the surface of the P-type well region 263p indicates the impurity concentration of the P-diffusion layer 205. In addition, in a region of about 0.5 μm to about 1.1 μm from the surface of the P-type well region 263p, the impurity concentration is, for example, 10 15 atoms / cm 3 The following P-type impurity concentrations are shown.

[0170] 43, the impurity concentration of the P-type impurity increases monotonically in a region from about 1.1 μm to about 1.8 μm deep from the surface of the P-type well region 263p, and the impurity concentration of the P-type impurity decreases monotonically in a region from about 1.8 μm to about 2.4 μm deep from the surface of the P-type well region 263p. Also, the impurity concentration of the N-type impurity increases monotonically in a region from about 1.4 μm to about 2.4 μm deep from the surface of the P-type well region 263p.

[0171] In FIG. 43, the impurity concentration distribution excluding the impurity concentrations of the P-type well region 261p and the N-type well region 271n is the same as that of the N-type high-voltage transistor Tr according to the modification of the first embodiment. NHA The impurity concentration distribution is similar to that of

[0172] [Manufacturing method] Next, with reference to FIGS. 44 to 49, a high-voltage N-type transistor Tr according to a second embodiment will be described. NH2 The manufacturing method thereof will be described.

[0173] 44, a resist 271r having openings corresponding to the P-type well region 261p and the N-type well region 271n is formed on the surface of the semiconductor substrate 200 (semiconductor substrate region 200S). Then, an N-type impurity such as phosphorus (P) is ion-implanted to form the N-type well region 271n, and then a P-type impurity such as boron (B) is ion-implanted to form the P-type well region 261p. do.

[0174] Next, as shown in FIG. 45, a resist 272r having an opening corresponding to the N-type well region 272n is formed on the surface of the semiconductor substrate 200 (semiconductor substrate region 200S), and an N-type impurity such as phosphorus (P) is ion-implanted to form the N-type well region 272n.

[0175] Next, as shown in FIG. 46, a resist 262r having an opening corresponding to the P-type well region 262p is formed on the surface of the semiconductor substrate 200 (semiconductor substrate region 200S), and a P-type impurity such as boron (B) is ion-implanted to form the P-type well region 262p.

[0176] 47, a resist 273r having an opening corresponding to the N-type well region 273n is formed on the surface of the semiconductor substrate 200 (semiconductor substrate region 200S), and an N-type impurity such as phosphorus (P) is ion-implanted to form the N-type well region 273n. The resist 273r is then peeled off.

[0177] 48, an insulating film 241a such as silicon oxide is formed on the upper surface of the semiconductor substrate 200. This step is performed by, for example, thermal oxidation.

[0178] Next, as shown in Fig. 49, for example, an insulating region STI is formed in the semiconductor substrate 200, and a stacked structure corresponding to the gate electrode is formed. This step is performed in the same manner as the steps described with reference to Fig. 21 to Fig. 27. Thereafter, the steps described with reference to Fig. 28 and subsequent steps are performed to form the high-voltage transistor Tr according to the second embodiment. NH2 is manufactured.

[0179] [Effects of the second embodiment] An N-type high-voltage transistor Tr provided in a P-type well region 263p electrically isolated from the semiconductor substrate 200 NH2 If the semiconductor device does not have the high concentration N- diffusion layer 202, there is a problem that the current driving force is likely to deteriorate when the potential of the source region and the drain region is made higher than the potential of the P-type well region 263p.

[0180] The reason for this can be considered as follows. That is, by forming the P-type well region 261p in the semiconductor substrate 200, the number of P-type impurities contained in the depletion layer when a high potential is applied to the source region increases. This is because the lower region in the Z direction of the low concentration N-diffusion layer 203 and the overlap region, which is a region provided at a position where the channel region 206 and the low concentration N-diffusion layer 203 overlap in the Y direction, are depleted, and the parasitic resistance increases. In particular, the overlap region is depleted two-dimensionally in the YZ plane, and the increase in the parasitic resistance of the overlap region is the main cause of the deterioration of the current driving force.

[0181] In contrast, in this embodiment, the N-type high-voltage transistor Tr NH2 Since the transistor has the high concentration N- diffusion layer 202, even if the potential of the source region and the drain region is increased, depletion of the overlap region can be suppressed, and deterioration of the current driving force can be suppressed.

[0182] In addition, the N-type high-voltage transistor Tr NH2 Since the N-type high-voltage transistor Tr has a high concentration N-diffusion layer 202, even if the low concentration N-diffusion layer 203 is uniformly made high concentration, the deterioration of the breakdown voltage can be suppressed. NH2 Since the high-concentration N-diffusion layer 202 has a high concentration, it is possible to suppress depletion of the upper region in the Z direction of the low-concentration N-diffusion layer 203 caused by trapping hot carriers (hot electrons) generated by impact ionization, as in the first embodiment. NH2 According to this, not only is the deterioration of the breakdown voltage alleviated, but also the increase in resistance due to the formation of a depletion layer caused by trapped hot carriers (hot electrons) is alleviated.

[0183] [Other embodiments] In the above embodiment, the technology applied to the NAND flash memory has been described. However, the technology described in this specification can be applied to configurations other than the semiconductor memory device, such as a three-dimensional NOR flash memory. The technology described in this specification can also be applied to configurations of semiconductor devices other than the semiconductor memory device. [others]

[0184] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0185] 200...semiconductor substrate, 200N, 271n, 272n, 273n, 311, 311a...N-type well region, 200P, 261p, 262p, 263p, 310, 310a...P-type well region, 200S...semiconductor substrate region, 201...gate electrode, 202...high concentration N-diffusion layer, 203...low concentration N-diffusion layer, 204, 303...N+ diffusion layer, 205...P-diffusion layer , 206...channel region, 213, 313...P+ diffusion layer, 241a, 341a...insulating film, 246, 256, 346, 356...sidewall insulating film, 247, 248, 257, 258, 347, 348, 357, 358...liner insulating layer, 274n...isolation N-type well region, 303...N+ diffusion layer CC, C400...via contact electrode, CS...via contact electrode.

Claims

1. A semiconductor substrate; a plurality of transistors provided on the semiconductor substrate; A first transistor of the plurality of transistors is a first gate insulating film provided on the semiconductor substrate; a first gate electrode provided on the first gate insulating film; sidewall insulating films provided on both side surfaces of the first gate electrode; a first region included in the semiconductor substrate and provided at a position overlapping the first gate electrode when viewed from a first direction intersecting a surface of the semiconductor substrate; a first diffusion layer including a first conductivity type impurity and connected to a first contact electrode included in the semiconductor substrate and extending in the first direction; a second diffusion layer including the first conductivity type impurity and provided between the first region and the first diffusion layer, the second diffusion layer being included in the semiconductor substrate; a third diffusion layer that is included in the semiconductor substrate, is provided between the second diffusion layer and the first diffusion layer, and is connected to the second diffusion layer, and contains an impurity of the first conductivity type; The concentration of the first conductive type impurity in the second diffusion layer is higher than the concentration of the first conductive type impurity in the third diffusion layer. Semiconductor memory device.

2. The first transistor is It is an N-channel transistor.

2. The semiconductor memory device according to claim 1.

3. The first conductivity type impurity is an N-type impurity.

2. The semiconductor memory device according to claim 1.

4. At least a portion of the second diffusion layer is provided at a position overlapping the sidewall insulating film when viewed from the first direction.

2. The semiconductor memory device according to claim 1.

5. The concentration of the first conductive type impurity in the second diffusion layer is less than 10 times the concentration of the first conductive type impurity in the third diffusion layer.

2. The semiconductor memory device according to claim 1.

6. The concentration of the first conductive type impurity in the first diffusion layer is 10 times or more higher than the concentration of the first conductive type impurity in the second diffusion layer.

2. The semiconductor memory device according to claim 1.

7. a first insulating layer including silicon (Si) and oxygen (O) and provided on both side surfaces of the first gate electrode via the sidewall insulating film; a second insulating layer including silicon (Si) and nitrogen (N) and provided on both sides of the first gate electrode via the first insulating layer; 2. The semiconductor memory device according to claim 1, comprising:

8. a fourth diffusion layer that is included in the semiconductor substrate, is provided at a position overlapping with the third diffusion layer when viewed from the first direction, is positioned on an opposite side of the third diffusion layer from the first gate electrode in the first direction, and contains an impurity of a second conductivity type different from the first conductivity type; 2. The semiconductor memory device according to claim 1.

9. The semiconductor substrate is containing an impurity of a second conductivity type different from the first conductivity type, a first well containing an impurity of the second conductivity type; a second well including an impurity of the first conductivity type, the second well being provided so as to surround the first well when viewed from the first direction; Equipped with The first region, the first diffusion layer, the second diffusion layer, and the third diffusion layer are provided in the first well.

2. The semiconductor memory device according to claim 1.

10. The first transistor is supplied with a voltage greater than 10V.

2. The semiconductor memory device according to claim 1.

11. A second transistor of the plurality of transistors is A second gate insulating film provided on the semiconductor substrate; a second gate electrode provided on the second gate insulating film; The length of the first gate insulating film in the first direction is greater than the length of the second gate insulating film in the first direction.

2. The semiconductor memory device according to claim 1.

12. A second transistor of the plurality of transistors is A second gate insulating film provided on the semiconductor substrate; a second gate electrode provided on the second gate insulating film; a second region included in the semiconductor substrate and overlapping the second gate electrode when viewed from the first direction; a fifth diffusion layer that is included in the semiconductor substrate, is connected to a second contact electrode that extends in the first direction, and contains an impurity of the first conductivity type; A distance from the first region to the first contact electrode is greater than a distance from the second region to the second contact electrode.

2. The semiconductor memory device according to claim 1.

13. A plurality of conductive layers aligned in the first direction; a semiconductor layer extending in the first direction and facing the plurality of conductive layers; a charge storage film provided between the plurality of conductive layers and the semiconductor layer; a current generating circuit electrically connected to the plurality of conductive layers; Equipped with The first transistor is provided in a current path between the plurality of conductive layers and the current generating circuit.

2. The semiconductor memory device according to claim 1.

14. A semiconductor substrate; a plurality of transistors provided on the semiconductor substrate; A first transistor of the plurality of transistors is a first gate insulating film provided on the semiconductor substrate; a first gate electrode provided on the first gate insulating film; sidewall insulating films provided on both side surfaces of the first gate electrode; a first region included in the semiconductor substrate and provided at a position overlapping the first gate electrode when viewed from a first direction intersecting a surface of the semiconductor substrate; a diffusion layer including a first conductivity type impurity and provided at a position overlapping the sidewall insulating film when viewed from the first direction, the diffusion layer being included in the semiconductor substrate; another diffusion layer that is provided on the opposite side of the first region in a second direction intersecting the first direction with respect to the one diffusion layer, is connected to the one diffusion layer, and contains the first conductive type impurity; Equipped with The concentration of the first conductive type impurity in the one diffusion layer is higher than the concentration of the first conductive type impurity in the other diffusion layer. Semiconductor memory device.

15. The first transistor is It is an N-channel transistor.

15. The semiconductor memory device according to claim 14.

16. The first conductivity type impurity is an N-type impurity.

15. The semiconductor memory device according to claim 14.

17. The concentration of the first conductive type impurity in the one diffusion layer is less than 10 times the concentration of the first conductive type impurity in the other diffusion layer.

15. The semiconductor memory device according to claim 14.

18. a first insulating layer including silicon (Si) and oxygen (O) and provided on both side surfaces of the first gate electrode via the sidewall insulating film; a second insulating layer including silicon (Si) and nitrogen (N) and provided on both sides of the first gate electrode via the first insulating layer; 15. The semiconductor memory device according to claim 14, comprising:

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