Memory device

Abstract

To solve the problem in which it is difficult to maintain data stored in a storage capacitor for a sufficiently long time due to a gate leak of a transistor.SOLUTION: A memory device includes a first memory circuit including an Si transistor, a selection circuit including an Si transistor, and a second memory circuit including OS transistors and a storage capacitor. The second memory circuit has a configuration in which one terminal of the storage capacitor is connected to a connection part of the two OS transistors connected in series, an output of the second memory circuit is connected to a second input terminal of the selection circuit, and an input of the second memory circuit is connected to a first input terminal of the selection circuit or an output terminal of the first memory circuit.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine, a It relates to a product or composition of matter. In the specification, a semiconductor device, a display device, a power storage device, a driving method thereof, a manufacturing method thereof, etc. In this specification, examples of the semiconductor device include a memory circuit and a processor including a memory circuit. Processors (typically programmable logic devices, CPUs, microcontrollers) The present invention relates to a processor, a memory controller, and an electronic device equipped with the processor.

[0002] In this specification, a semiconductor device refers to a semiconductor element (transistor, diode, etc.). A semiconductor device is a device that uses semiconductor characteristics to This refers to any device that can function. For example, integrated circuits, chips equipped with integrated circuits, display devices, Optical devices and electronic devices, etc. may be included in semiconductor devices or may have semiconductor devices. There is. [Background technology]

[0003] Central Processing Unit (CPU) and other Signal processing devices have a wide variety of configurations depending on their applications. Generally, in addition to the main memory for storing data and programs, there are registers, caches, and The register is used for arithmetic processing and program execution. It has the role of temporarily holding the data signal to hold the row state, etc. Flash memory is placed between the processor and the main memory and provides slow access to the main memory. The purpose of this is to reduce the number of bits required to perform calculations and speed up the processing.

[0004] In a signal processing device, memory circuits such as registers and cache memories are It is necessary to write data signals at high speed. Therefore, flip-chip registers are usually used. The flop uses SRAM (Static Random Access Memory) as cache memory. In other words, these registers, cache memories, etc. The chip has a volatile memory circuit that loses data signals when the power supply is interrupted. It is used.

[0005] In order to reduce power consumption, the signal processing device is A method has been proposed in which the supply of power voltage is temporarily stopped (see, for example, Patent Document 1). In the method of Patent Document 1, peripheral circuits of volatile storage circuits such as registers and cache memories A non-volatile memory circuit is disposed in the memory, and the data signal is temporarily stored in the non-volatile memory circuit. In this way, even when the supply of power supply voltage to the signal processing device is stopped, the registers, The data signals stored in the cache memory or the like are held.

[0006] In addition, when the supply of power supply voltage to a signal processing device is stopped for a long period of time, Before stopping, the data signal in the volatile storage circuit is written to a hard disk, flash memory, etc. By transferring the data to an external memory circuit, loss of the data signal can also be prevented.

[0007] However, while the supply of power supply voltage to the signal processing device is stopped, A data signal stored in a volatile memory circuit is stored in the nonvolatile memory circuit. In the method described above, magnetic elements and ferroelectrics are mainly used as non-volatile memory circuits. Therefore, the manufacturing process of the signal processing device is complicated.

[0008] In addition, while the supply of power supply voltage to the signal processing device is stopped, volatile storage is performed in the external storage circuit. In the method of storing the data signal of the circuit, the data signal is transferred from the external storage circuit to the volatile storage circuit. It takes time to restore the signal. Therefore, backing up the data signal using an external memory circuit is A short interruption of power supply voltage when no data signals are input or output, in order to reduce power consumption. Not suitable for.

[0009] In this regard, Patent Document 2 describes a transistor (e.g. For example, a transistor having an oxide semiconductor in a channel formation region and a storage capacitor are A memory device 140 (FIG. 9) has been proposed to be used in place of a volatile memory circuit. In this structure, the channel formation region is made of silicon (hereafter referred to as a Si transistor). The memory circuit 121 is made up of a silicon transistor. 36 and a transistor using an oxide semiconductor in the channel formation region (hereafter referred to as OS transistor) The OS transistor 101 has a storage capacitor 102. By utilizing the extremely small leakage current in the It is designed to be able to maintain its function even if the power source is cut off.

[0010] This method provides a memory device that does not require a complicated manufacturing process and can reduce power consumption. In particular, it is possible to suppress power consumption by stopping the supply of power supply voltage even for a short period of time. It is possible to provide a memory device that can be used instead of a non-volatile memory circuit. In addition, by using OS transistors and storage capacitors, there is no degradation of characteristics due to rewriting. It has advantages. [Prior art documents] [Patent documents]

[0011] [Patent Document 1] Japanese Patent Application Publication No. 10-078836 [Patent Document 2] JP 2012-257200 A Summary of the Invention [Problem to be solved by the invention]

[0012] In the configuration of FIG. 9, the input terminal of the selection circuit connected to the storage capacitor is connected to the gate of a Si transistor. However, depending on the design of the selection circuit, a Si transistor may be connected. In some cases, the source or drain of the Si transistor is connected to the gate. However, as LSIs become more miniaturized, In recent years, the leakage current of transistor gates has become so large that it cannot be ignored. Therefore, in a configuration like that shown in Figure 9, it becomes difficult to retain data for a sufficient period of time. It is coming.

[0013] In view of the above problems, one embodiment of the disclosed invention is a method for manufacturing a semiconductor device that does not require a complicated manufacturing process and has low power consumption. Another object of the present invention is to provide a storage device capable of suppressing the power supply voltage supply for a short period of time. One of the objectives is to provide a storage device that can reduce power consumption even when stopped. Even if the gate leakage increases with the miniaturization of Si transistors, the power supply voltage One object is to provide a storage device that can reduce power consumption by stopping the supply. [Means for solving the problem]

[0014] In order to solve the above problem, one embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, A storage circuit having a first transistor and a storage capacitor is used. One terminal of the storage capacitor is connected to a first transistor. A current is applied to one of the source or drain of the first transistor and one of the source or drain of the second transistor. The first transistor and the second transistor are electrically connected to each other in an off state. For example, a transistor using an oxide semiconductor in a channel formation region has a significantly small leakage current. The OS transistor is an O-type transistor. Since the leakage current in the OFF state is extremely small, the signal stored in the storage capacitor can be maintained for a long period of time. In this way, the first transistor and the second transistor can be an OS A memory circuit using transistors has the advantage that there is no deterioration in characteristics due to rewriting.

[0015] One embodiment of the present invention includes a first memory circuit, a selection circuit, and a second memory circuit. The circuit includes a first transistor, a second transistor, and a storage capacitor. One terminal is connected to the source or drain of the first transistor and the other terminal is connected to the drain of the second transistor. The first transistor and the second transistor are electrically connected to one of the source and the drain. A transistor is a transistor that has a very small leakage current in the off state, such as a channel transistor. A transistor using an oxide semiconductor (referred to as an OS transistor) is used in the gate formation region. The OS transistor has a significantly small leakage current in the off state, so that the storage capacitance The signal held in the second transistor can be maintained for a long period of time. The other terminal is electrically connected to a second input terminal of the selection circuit. The source or drain of the first transistor is electrically connected to the input terminal of the memory circuit of The other terminal is electrically connected to the first input terminal of the selection circuit or the output terminal of the second memory circuit. can be.

[0016] The other of the source and the drain of the second transistor and the second input terminal of the selection circuit are connected to a buffer. The power supply may be electrically connected to the power supply through a buffer circuit. When the voltage of the signal held in the storage capacitor decreases during the voltage supply stop period, By providing a buffer circuit, it is possible to compensate for the voltage and output it as a normal voltage. If the voltage can be compensated for, the guaranteed operating range of the storage device can be expanded.

[0017] The other of the source and drain of the first transistor and the first input terminal or the second input terminal of the selection circuit are connected to each other. The output terminal of the memory circuit is electrically connected to the second transistor via an inverter circuit. The other of the source or drain of the first transistor and the second input terminal of the selection circuit are connected to each other through an inverter circuit. By providing an inverter circuit, If the voltage of the signal held in the storage capacitor decreases during It is possible to compensate for this and output the normal voltage. An inverter circuit is provided to compensate for the voltage. If this is possible, the guaranteed operating range of the storage device can be expanded.

[0018] The second memory circuit may be a latch circuit or a flip-flop circuit.

[0019] The selection circuit and the second memory circuit include a third transistor and a fourth transistor. The third transistor and the fourth transistor are transistors using, for example, Si for the channel formation region. A transistor is used. Effect of the Invention

[0020] According to one embodiment of the disclosed invention, a complex manufacturing process is not required and power consumption can be reduced. In addition, it is possible to provide a storage device that can perform the above-mentioned operations even if the power supply voltage is stopped for a short period of time. It is possible to provide a memory device that can reduce power consumption by using Si transistors. The effect of reducing power consumption when gate leakage increases with miniaturization of semiconductor devices is large. [Brief description of the drawings]

[0021] [Figure 1] FIG. 1 is a circuit diagram of a memory device according to an embodiment. [Diagram 2] 4 is a timing chart showing the operation of the storage device according to the embodiment. [Diagram 3] FIG. 1 is a circuit diagram of a memory device according to an embodiment. [Figure 4] FIG. 1 is a circuit diagram of a memory device according to an embodiment. [Diagram 5] FIG. 1 is a circuit diagram of a memory device according to an embodiment. [Figure 6] 1 is a circuit diagram illustrating a configuration of a memory circuit that can be used in a memory device according to an embodiment. [Figure 7] 1 is a circuit diagram illustrating a configuration of a memory circuit that can be used in a memory device according to an embodiment. [Figure 8] 1A and 1B illustrate a configuration of a storage device according to an embodiment. [Figure 9] FIG. 1 is a circuit diagram of a conventional memory device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] Hereinafter, embodiments of the invention disclosed in this specification will be described with reference to the drawings. The invention disclosed herein can be embodied in many different forms, and The embodiments and details of the present invention may be modified in various ways without departing from the spirit and scope of the present invention. It is easily understood by those skilled in the art that the present invention can be modified in various ways. In the drawings shown below, the same parts or similar functions are The parts having the same functions are given the same reference numerals and the repeated explanations are omitted.

[0023] In addition, the position, size, range, etc. of each component shown in the drawings etc. may be changed in order to make the explanation easier to understand. For this reason, the actual location, size, range, etc. may not be shown. The present invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0024] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components. Please note that the numbers are added to avoid confusion and are not limited in number. Voltage can refer to the difference between a certain potential and a reference potential (e.g. ground potential). Therefore, voltage, potential, and potential difference can be rephrased as potential, voltage, and voltage difference, respectively. It is Noh.

[0025] In addition, when it is explicitly stated that A and B are connected, it means that A and B are electrically connected. A and B are connected functionally, A and B are directly connected, This includes cases where

[0026] In this specification, the state in which the source and drain of a transistor are conductive is referred to as the "on state." A state in which the source and drain of a transistor are not conductive is referred to as an "off state."

[0027] (Embodiment 1) <Configuration of the storage device shown in Figure 1> In this embodiment, a configuration of a storage device of one embodiment of the present invention will be described with reference to FIG. .

[0028] The memory device 240 illustrated in FIG. A memory circuit 220 having a third transistor 203 and a storage capacitor 202. A memory circuit 221 and a selection circuit 236 (which acts as a multiplexer) constituted by a fourth transistor. (also called.)

[0029] The first transistor 201 and the second transistor 203 are made of, for example, an oxide semiconductor. The transistor (OS transistor) used in the channel formation region is used. Since the leakage current of the capacitor in the off state is extremely small, the signal stored in the storage capacitor 202 It is possible to configure the memory circuit 220 so that the data can be retained even if the power supply is cut off. In addition, the first transistor 201 and the second transistor 203 are OS transistors. The memory circuit 220 used has the advantage that there is no deterioration in characteristics due to rewriting. The semiconductor material will be described later.

[0030] The third and fourth transistors use, for example, Si in the channel formation regions. The Si may be single crystal Si or polycrystalline Si, but is particularly In particular, transistors in which the channel is formed in single crystal silicon are suitable because they have a high operating frequency. In addition, instead of Si, semiconductors such as Ge and SiC, and compound semiconductors such as GaAs and GaP are used. You may use it.

[0031] In the memory circuit 220, one terminal of the storage capacitor 202 is connected to the source of the first transistor 201. or drain of the second transistor 203 and the source or drain of the second transistor 204. The other terminal of the storage capacitor 202 is connected to a low potential (for example, the ground potential GND). The source or drain of the first transistor 201 and the The connection part of the source or drain of the transistor 203 and the storage capacitor 202 is a node FN. Let us assume that.

[0032] A control signal OSG1 is input to the gate of the first transistor 201. The gate of the starter 203 receives a control signal OSG2.

[0033] A first input terminal of the selection circuit 236 is connected to the source or drain of the first transistor 201. The other one is electrically connected to a second input terminal of the selection circuit 236. The other of the source and drain of the selection circuit 236 is electrically connected to the output terminal of the selection circuit 236. , and is electrically connected to the input terminal of the memory circuit 221.

[0034] The selection circuit 236 selects one of the two input signals in response to a selection signal RC. The selected signal is output.

[0035] An input signal IN is input to a first input terminal of the selection circuit 236. The voltage Vx( (not shown) is a volatile memory circuit that can hold a data signal only while the More specifically, the memory circuit 221 includes a latch formed of a fourth transistor. A switch circuit, flip-flop circuit, etc. can be used.

[0036] <Method of driving the storage device> FIG. 2 shows a timing chart for driving the storage device 240 shown in FIG.

[0037] <Normal operation period (period T1)> The period during which the storage device 240 operates normally is defined as a period T1.

[0038] In the period T1, the input signal IN is input to the memory circuit 221 via the selection circuit 236. The input signal IN is held in the memory circuit 221 .

[0039] In the period T1, the gate of the first transistor 201 is connected to the gate of the first transistor 201. It is better to input the control signal OSG1 that turns the storage capacitor 202 into the OFF state. Therefore, the storage device 240 can operate at high speed and power consumption can be reduced.

[0040] During the period T1, the potential of the node FN may be indefinite. The signal from the node FN is not transmitted to the memory circuit 221 .

[0041] <Write operation period (period T2)> The period during which the input signal IN is written to the memory circuit 220 is set as a period T2. This is the period before the period T3 (power supply voltage supply stop period) described later. Before the supply is stopped, the input signal IN is written to the storage circuit 220.

[0042] At the beginning of the period T2, the control signal OSG1 that controls the first transistor 201 is The voltage becomes high enough to write the input signal IN to the first transistor 202. When a signal is input to the gate of the first transistor 201, the source and drain of the first transistor 201 become conductive. As a result, the input signal IN is supplied to the holding capacitor 203 via the first transistor 201. The input signal IN is input to the storage capacitor 202, and is held by the storage capacitor 202. When the period during which the supply of the power supply voltage Vx is stopped is short, the second transistor 203 is turned on. It is preferable that the node between the second transistor 203 and the selection circuit 236 is in the input state. By keeping the potential of the input signal IN the same as that of the input signal IN, the operation of the storage device 240 can be made faster and frequent power changes can be avoided. This is effective for turning the power supply on and off. Also, when the supply of the power supply voltage Vx is stopped for a long period of time, In other words, the second transistor 203 may be in an on state or an off state. The signal held in the capacitance 202 is transferred to the first transistor 201 and the second transistor 202. Since the leakage current in the off state of 03 is extremely small, the supply of the power supply voltage Vx is stopped. Even if the period is long, the data signal is retained for a sufficiently long time. The voltage that can be written does not have to be the high-level potential (VDD) or the high-level potential (VD D) is also acceptable.

[0043] <Power supply voltage supply interruption period (period T3)> The period during which the supply of the power supply voltage Vx is stopped is designated as period T3. At the beginning of period T3, the storage device 2 The supply of the power supply voltage Vx to the first transistor 201 is stopped. The control signal OSG1 is set to a low level potential (VSS). When the supply of the power supply voltage Vx is stopped, the voltage Vx stored in the memory circuit 221 is turned off. However, after the supply of the power supply voltage Vx to the memory circuit 221 is stopped, Even if the input signal IN held in the holding capacitor 202 is changed, the input signal IN is held. The first transistor 201 and the second transistor 203 connected to each other are in an off state. Since the leakage current is extremely small, the input signal IN held by the holding capacitor 202 can be held for a long time. In this way, the storage device 240 can maintain the power supply voltage Vx even after the supply of the power supply voltage Vx is stopped. During the period T3, the supply of the power supply voltage Vx to the storage device 240 is stopped. This corresponds to the period during which

[0044] As described above, the first transistor 201 and the second transistor 203 are in an off state. Since the leakage current is extremely small, the input signal IN held by the holding capacitor 202 can be held for a long time. Can be kept for a period of time.

[0045] <Power supply resumption period (period T4)> The period during which the supply of the power supply voltage Vx is resumed is designated as period T4. The supply of the power supply voltage Vx to the first transistor 201 and the second transistor 202 is resumed. The control signals OSG1 and OSG2 for controlling the transistor 203 are at a low level potential (VSS). and the first transistor 201 and the second transistor 203 remain in an off state. Therefore, the input signal IN remains held in the holding capacitor 202.

[0046] <Read operation period (period T5)> The period during which the input signal IN written in the memory circuit 220 is read is defined as a period T5. At the beginning of the process, the selection signal RC and the control signal OSG2 that controls the second transistor 203 are The potential goes from low level (VSS) to high level (VDD). A selection signal RC having a high level potential (VDD) is input, and a high level potential is applied to the second transistor 203. The input signal IN held in the holding capacitor 202 is input to the memory circuit 2 The input signal IN input to the memory circuit 221 is output as an output signal OUT. is output.

[0047] When the period T5, which is the read operation period, ends, a new period T1 (normal operation period) begins. and a new input signal IN is input to the storage device 240.

[0048] As described above, in the operation of the memory device 240, the first When a high-level potential (VDD) is input to the gate of the transistor 201, An input signal IN is held in a holding capacitor 202 via a transistor 201 .

[0049] The storage capacitor 202 is connected to the first transistor 201 and the second transistor 203. and is not directly connected to the gate of the third transistor or the fourth transistor. Therefore, when the leakage current of the gate of the third transistor or the fourth transistor is large, Also, the leakage current in the off state of the first transistor 201 and the second transistor 203 is Since the current is extremely small, the input signal IN held by the holding capacitor 202 is maintained for a long period of time. It is possible.

[0050] As a result, the input signal is maintained even if the power supply voltage is stopped for a long period of time, and It is also possible to provide a storage device capable of suppressing power consumption by stopping the supply of power supply voltage. In particular, when gate leakage increases with the miniaturization of Si transistors, the power consumption is reduced. The effect of suppressing it is great.

[0051] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0052] (Embodiment 2) In this embodiment, a storage device according to one embodiment of the present invention will be described with reference to a storage device having a configuration different from that shown in FIG. The configuration will be described with reference to FIG.

[0053] FIG. 3A shows a configuration of a second transistor 203 connected to the other of the source and the drain of the selection circuit 23. 6. The other configurations are the same as those in the above embodiment. By providing the buffer circuit 204, during the power supply voltage supply stop period, When the voltage of the input signal IN held in the holding capacitor 202 decreases, It is possible to compensate for the voltage and output it as a normal voltage. By providing the above voltage, the guaranteed operating range of the storage device 240 can be expanded. can.

[0054] FIG. 3B shows a configuration of a first transistor 201 connected to the other of the source and the drain of the selection circuit 23. An inverter circuit 205 is provided between the first transistor 203 and the second transistor 204. In this case, an inverter circuit 206 is provided between the other input and the selection circuit 236. The other configuration is the same as that of the first embodiment. In the same manner as in the case where the power supply voltage is stopped, the input signal held in the holding capacitor 202 When the IN voltage drops, the voltage is compensated for and the normal voltage is output. The inverter circuit 205 and the inverter circuit 206 are provided, If the pressure can be compensated for, the guaranteed operating range of the storage device 240 can be extended.

[0055] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0056] (Embodiment 3) In this embodiment, a configuration of a storage device according to one embodiment of the present invention will be described with reference to FIGS. The configuration of the storage device will be described with reference to FIGS.

[0057] FIG. 4A shows a case where the other of the source and the drain of the first transistor 201 is connected to a memory circuit 221. The other configurations are the same as those of the first embodiment. However, as a configuration of the memory circuit 221, an input signal input to an input terminal of the memory circuit 221 is This is the case where a potential of the same level as the potential of IN is output to the output terminal as the output signal OUT. .

[0058] The storage capacitor 202 is connected to the first transistor 201 and the second transistor 203. and is not directly connected to the gate of the third transistor or the fourth transistor. Therefore, when the leakage current of the gate of the third transistor or the fourth transistor is large, Also, the leakage current in the off state of the first transistor 201 and the second transistor 203 is Since the current is extremely small, the output signal OUT held by the holding capacitor 202 can be held for a long period of time. It is possible to do so.

[0059] FIG. 4B shows a configuration in which the other of the source and the drain of the second transistor 203 and the selection circuit 23 6. The other configuration is the same as that shown in FIG. By providing the buffer circuit 204, during the power supply voltage supply stop period, When the voltage of the output signal OUT held in the holding capacitor 202 decreases, It is possible to compensate for the voltage and output it as a normal voltage. By providing the above voltage, the guaranteed operating range of the storage device 240 can be expanded. can.

[0060] FIG. 4C illustrates a semiconductor device including the other of the source and the drain of the first transistor 201 and the memory circuit 22. An inverter circuit 205 is provided between the first transistor 203 and the second transistor 204. In this case, an inverter circuit 206 is provided between the other input and the selection circuit 236. The other configuration is the same as that of FIG. 4(A). Similarly, during the power supply voltage supply stop period, the output signal O When the UT voltage drops, the voltage is compensated for and the normal voltage is output. The inverter circuit 205 and the inverter circuit 206 are provided, If the pressure can be compensated for, the guaranteed operating range of the storage device 240 can be extended.

[0061] FIG. 5A shows a case where the other of the source and the drain of the first transistor 201 is an inverter circuit. It is electrically connected to the output terminal of the memory circuit 221 via 205. The other components are as follows: The configuration of the memory circuit 221 is the same as that of the first embodiment. A potential at a level different from the potential of the input signal IN input to the input terminal (when the input signal IN is high level) When the input signal IN is at a low level potential, it becomes a low level potential. When the input signal IN is at a low level potential, it becomes a high level This is the case where a potential difference (Vp) is output to the output terminal as the output signal OUT.

[0062] The storage capacitor 202 is connected to the first transistor 201 and the second transistor 203. and is not directly connected to the gate of the third transistor or the fourth transistor. Therefore, when the leakage current of the gate of the third transistor or the fourth transistor is large, Also, the leakage current in the off state of the first transistor 201 and the second transistor 203 is Since the current is extremely small, the output signal OUT held by the holding capacitor 202 can be held for a long period of time. It is possible to do so.

[0063] FIG. 5B shows a case where the other of the source and the drain of the first transistor 201 is connected to a memory circuit 221. the other of the source and drain of the second transistor 203. and the selection circuit 236. However, the configuration of the memory circuit 221 is the same as that of the memory circuit 22 A potential of a different level from the potential of the input signal IN input to the input terminal 1 (when the input signal IN is When the input signal IN is at a low level, it becomes a low level. The output signal OUT is output to the output terminal. By providing the inverter circuit 206, the storage capacitor 202 can store the current during the power supply voltage supply stop period. When the voltage of the output signal OUT decreases, the voltage is compensated for during output to restore normal operation. By providing the inverter circuit 206, the voltage can be output as If this can be compensated for, the guaranteed operation range of the storage device 240 can be expanded.

[0064] FIG. 5C shows a case where the other of the source and the drain of the first transistor 201 is an inverter circuit. 205 and the output terminal of the memory circuit 221. A buffer circuit 204 is provided between the other of the source or drain of the third transistor and the selection circuit 236. The other configurations are the same as those in the first embodiment. However, the memory circuit 221 In this configuration, the potential of the input signal IN input to the input terminal of the memory circuit 221 is different from that of the input signal IN. When the input signal IN is at a high level potential, it becomes a low level potential. When the potential is low, it becomes high.) is output to the output terminal as the output signal OUT. By providing the buffer circuit 204, In the case where the voltage of the output signal OUT held in the holding capacitor 202 is decreased, The buffer circuit 2 can compensate for the voltage and output it as a normal voltage. 04 and compensating for the above voltage, the guaranteed operating range of the storage device 240 can be expanded. This can be done.

[0065] The memory device 240 is also used by various circuits in the signal processing device in different ways. Therefore, it takes time for the input signal IN input to the storage device 240 to become stable. There may be a variation between the source and drain of the first transistor 201. In the case where the other terminal is electrically connected to the input terminal side of the storage circuit 221, If the charging time is constant, the voltage written to the storage capacitor 202 may vary. In order to suppress the variation in voltage caused by writing, The charging time must be set with a certain margin, taking into consideration the various circuit configurations that may be used. The other of the source and the drain of the transistor 201 is electrically connected to the output terminal of the memory circuit 221. By configuring the memory device 240 to be connected in the same manner, the configuration of the memory device 240 is constant, so that In addition, the potential variation of the memory device 2 to which different circuits are connected can be suppressed. Even if the capacitance is 40, the charging time to the storage capacitor 202 is determined by taking into consideration the circuits connected to each capacitor. It is possible to keep it constant without any fluctuation.

[0066] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0067] (Embodiment 4) In this embodiment, a volatile laser that can be used for the memory circuit 221 of the memory device of one embodiment of the present invention is An example of the configuration of a latch circuit and a flip-flop circuit will be described with reference to FIG. 6 and FIG. 7. do.

[0068] FIG. 6 illustrates an example of the configuration of a volatile latch circuit that can be used in a semiconductor device according to one embodiment of the present invention. 2 is a circuit diagram showing an inverter circuit 207, an inverter circuit 208, and a clocked inverter circuit 209. The inverter circuit 207 is composed of a capacitor circuit 211 and an analog switch circuit 213. The input terminal of the inverter circuit 207 is connected to the input terminal of the memory circuit 221, and the output terminal of the inverter circuit 207 is The input terminal of the inverter circuit 208 is connected to the input terminal of the analog switch circuit 213. is connected to the output terminal of the analog switch circuit 213, and the output terminal of the inverter circuit 208 The input of the clocked inverter circuit 211 is connected to the output terminal of the memory circuit 221. The terminal is connected to the output terminal of the inverter circuit 208, and the clocked inverter circuit 211 The output terminal of the inverter circuit 208 is connected to the input terminal of the inverter circuit 208 .

[0069] FIG. 7 shows the configuration of a volatile flip-flop circuit that can be applied to a semiconductor device according to one embodiment of the present invention. 1 is a circuit diagram illustrating an example of an inverter circuit 207, an inverter circuit 208, and an inverter a clocked inverter circuit 211; a clocked The inverter circuit 212, the analog switch circuit 213, and the analog switch circuit 214 The input terminal of the inverter circuit 207 is connected to the input terminal of the memory circuit 221. The output terminal of the inverter circuit 207 is connected to the input terminal of the analog switch circuit 213. The input terminal of the inverter circuit 208 is connected to the output terminal of the analog switch circuit 213. The output terminal of the inverter circuit 208 is connected to the input terminal of the analog switch circuit 214. The input terminal of the clocked inverter circuit 211 is connected to the output terminal of the inverter circuit 208. The output terminal of the clocked inverter circuit 211 is connected to the input terminal of the inverter circuit 208. The input terminal of the inverter circuit 209 is connected to the input terminal of the analog switch circuit 2 14, and the output terminal of the inverter circuit 209 is connected to the output terminal of the inverter circuit 210. The input terminal of the clocked inverter circuit 212 is connected to the input terminal of the inverter circuit. The output terminal of the clocked inverter circuit 212 is connected to the output terminal of the inverter circuit 209. The output terminal of the inverter circuit 210 is connected to the input terminal of the memory circuit 209. 21 is connected to the output terminal of the

[0070] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0071] (Embodiment 5) In this embodiment, among transistors that can be used in the semiconductor device of one embodiment of the present invention, For transistors with extremely small leakage current in the low-temperature state, The semiconductors that can be used will be described.

[0072] Specifically, when the oxide semiconductor described in this embodiment is provided in a channel formation region, The transistor (OS transistor) having a significantly small leakage current in the sixth embodiment is This can be applied to the transistors described in .

[0073] We process oxide semiconductors with a large energy gap of 3.0 eV or more under appropriate conditions, and A transistor including an oxide semiconductor layer obtained by sufficiently reducing the carrier density is The leakage current (off-state current) between the source and drain in the off state was measured using a conventional silicon transistor. It can be made extremely low compared to transistors.

[0074] <Oxide semiconductor> The oxide semiconductor used is at least indium (In) or zinc (Zn It is particularly preferable that the oxide semiconductor contains In and Zn. As a stabilizer to reduce the variation in the electrical characteristics of transistors using In addition, it is preferable to have gallium (Ga) as a stabilizer. It is preferable that the alloy contains hafnium (Hf) and diphenyl ether (DEN) as stabilizers. Zr, titanium (Ti), scandium (Sc), yttrium (Y), tantanides (e.g., cerium (Ce), neodymium (Nd), gadolinium (Gd)) It is preferable that one or more selected from the above are included.

[0075] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-Zr-Zn oxides In-Ti-Zn oxides, In-Sc-Zn oxides, In-Y-Zn oxides, In-La-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, I n-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In -Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In- Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Y b-Zn oxide, In-Lu-Zn ​​oxide, and oxides of quaternary metals In-Sn- Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide In-Sn-Al-Zn oxides, In-Sn-Hf-Zn oxides, In-Hf- Al-Zn based oxides can be used.

[0076] Here, the In-Ga-Zn oxide is an oxide having In, Ga, and Zn as the main components. The ratio of In, Ga, and Zn does not matter. Metal elements may also be included.

[0077] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0 and m is not an integer) In addition, M may be selected from Ga, Fe, Mn, and Co. Indicates one or more metal elements, or the above-mentioned elements as stabilizers In addition, as an oxide semiconductor, In2SnO5(ZnO) n (n>0 and n is an integer) Materials represented by the formula:

[0078] For example, In:Ga:Zn=1:1:1, In:Ga:Zn=3:1:2, or In In-Ga-Zn oxides with an atomic ratio of Ga:Zn=2:1:3 and oxides with similar compositions It is a good idea to use compounds.

[0079] Oxide semiconductor films are roughly classified into single-crystal oxide semiconductor films and non-single-crystal oxide semiconductor films. The single crystal oxide semiconductor film includes an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, and a polycrystalline oxide semiconductor film. Physical semiconductor film, CAAC-OS (C Axis Aligned Crystalline This refers to films such as oxide semiconductor films.

[0080] The oxide semiconductor film may have, for example, a non-single crystal structure. Axis Aligned Crystal), polycrystalline, microcrystalline, and amorphous parts. The amorphous part has a higher defect level density than the microcrystals and CAAC. The defect level density is higher than that of the conventional GaN.

[0081] The oxide semiconductor film may include, for example, a CAAC-OS. The c-axis is oriented, and the a-axis and / or b-axis are not macroscopically aligned.

[0082] The oxide semiconductor film may have, for example, microcrystals. The microcrystalline oxide semiconductor film has a thickness of, for example, 1 nm to 10 nm. The microcrystalline oxide semiconductor film contains microcrystals (also referred to as nanocrystals) having a size of 100 nm. The atomic order is more regular than that of an amorphous oxide semiconductor film. The amorphous oxide semiconductor film has a feature that the density of defect states is lower than that of an amorphous oxide semiconductor film.

[0083] The oxide semiconductor film may have, for example, an amorphous portion. The amorphous oxide semiconductor film has an irregular atomic arrangement. The oxide semiconductor film is ordered and does not have a crystalline component. A typical example is an oxide semiconductor film whose entire structure is completely amorphous.

[0084] Note that the oxide semiconductor film may be a CAAC-OS film, a microcrystalline oxide semiconductor film, or an amorphous oxide semiconductor film. The mixed film may be a film having, for example, an amorphous oxide semiconductor region and a microcrystalline oxide semiconductor region. The mixed film has a semiconductor region and a CAAC-OS region. A stack of an oxide semiconductor region, a microcrystalline oxide semiconductor region, and a CAAC-OS region. The structure may be

[0085] Note that the oxide semiconductor film may be, for example, single crystal.

[0086] The oxide semiconductor film has a plurality of crystal parts, and the c-axes of the crystal parts are aligned along a normal vector of a surface on which the crystal parts are formed. or preferably aligned in a direction parallel to the normal vector of the surface. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. An example of such an oxide semiconductor film is a CAAC-OS film.

[0087] <CAAC-OS film> The CAAC-OS film is one of the oxide semiconductor films having a plurality of crystal parts, and most of the crystal parts have a size that can be accommodated within a cube with a side length of less than 100 nm. Therefore, the crystal parts included in the CAAC-OS film also include cases where the side length is less than 10 nm, less than 5 nm, or less than 3 nm and can be accommodated within a cube. The CAAC-OS film is characterized by having a lower density of defect energy levels than microcrystalline oxide semiconductor films. Hereinafter, the CAAC-OS film will be described in detail.

[0088] When the CAAC-OS film is observed by a transmission electron microscope (TEM: Transmission Electron Microscope), a clear boundary between crystal parts, that is, a grain boundary (also referred to as a grain boundary), cannot be confirmed. Therefore, it can be said that the CAAC-OS film is less likely to cause a decrease in electron mobility due to grain boundaries.

[0089] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, cases of -5° or more and 5° or less are also included. Also, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, cases of 85° or more and 95° or less are also included.

[0090] Also, in this specification, when a crystal is trigonal or rhombohedral, it is expressed as a hexagonal system. .

[0091] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation ) It can be confirmed that the metal atoms are arranged in layers in the crystal part. Each layer has a surface on which the CAAC-OS film is formed (also called a surface on which the film is formed) or a top surface having irregularities. The shape of the CAAC-OS film reflects this, and the CAAC-OS film is aligned parallel to the surface on which the film is formed or the top surface.

[0092] On the other hand, the CAAC-OS film was observed by TEM from a direction roughly perpendicular to the sample surface (planar TEM). When the metal atoms were observed, they were found to be arranged in triangular or hexagonal shapes in the crystals. However, no regularity was observed in the arrangement of metal atoms between different crystal parts. stomach.

[0093] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It is clear that there are

[0094] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. This indicates that the crystals in the CAAC-OS film have a c-axis orientation, and the c-axis is generally aligned on the surface on which the film is formed or on the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0095] On the other hand, in-plane X-ray irradiation is performed on the CAAC-OS film in a direction perpendicular to the c-axis. In the analysis by the ane method, a peak may appear at 2θ around 56°. This peak is This is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is set as the axis (φ axis). When the sample is rotated and analyzed (φ scan), the crystal plane equivalent to the (110) plane is In contrast, in the case of the CAAC-OS film, the 2θ is set to 5 Even when the φ is fixed at around 6° and scanned, no clear peak appears.

[0096] From the above, it is considered that the a-axis and b-axis orientations are inconsistent between different crystal regions in the CAAC-OS film. The crystal is regular, but has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which the crystal is formed or the upper surface. Therefore, the layered arrangement confirmed by the cross-sectional TEM observation mentioned above is consistent with the above. Each layer of aligned metal atoms is a plane parallel to the ab plane of the crystal.

[0097] The crystalline portion is formed when the CAAC-OS film is formed or when a crystallization process such as a heat treatment is performed. As described above, the c-axis of the crystal is aligned along the surface on which the CAAC-OS film is formed or along the surface on which the CAAC-OS film is formed. The orientation of the CAAC-OS film is parallel to the normal vector of the top surface. When the shape of the CAAC-OS film is changed by etching, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed. Or it may not be parallel to the normal vector of the upper surface.

[0098] In addition, the degree of crystallinity in the CAAC-OS film may not be uniform. When the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the top surface, The adjacent regions may have a higher degree of crystallinity than the regions adjacent the surface to be formed. When impurities are added to the C-OS film, the crystallinity of the region where the impurities are added changes, and regions with different crystallinities may be formed partially.

[0099] In addition, in the out-of-plane method analysis of the CAAC-OS film having InGaZnO4 crystals, in addition to the peak at around 2θ = 31°, a peak may also appear at around 2θ = 36°. The peak at around 2θ = 36° indicates that the CAAC-OS film contains crystals that do not have c-axis orientation in part. The CAAC-OS film preferably shows a peak at around 2θ = 31° and does not show a peak at around 2θ = 36°.

[0100] A transistor using a CAAC-OS film has little variation in electrical characteristics due to irradiation with visible light or ultraviolet light. Therefore, the transistor has high reliability.

[0101] Note that the oxide semiconductor film may be, for example, a laminated film having two or more of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a CA AC-OS film.

[0102] <Method for forming a CAAC-OS film> When applying a CAAC-OS film as the oxide semiconductor film, there are three methods for forming the CAAC-OS film that can be cited.

[0103] The first is to form an oxide semiconductor film with a film formation temperature of 200°C or higher and 450°C or lower, and form crystal parts in which the c-axis of the crystal parts contained in the oxide semiconductor film is aligned in a direction parallel to the normal vector of the surface to be formed or the normal vector of the surface.

[0104] The second is to form an oxide semiconductor film with a thin film thickness and then perform a heat treatment at 200°C or higher and 700°C or lower By performing the above, the c-axis of a crystal part included in the oxide semiconductor film is aligned with a normal vector of a formation surface or is a method for forming crystals aligned parallel to the normal vector of the surface.

[0105] The third method is to deposit a thin oxide semiconductor film on the first layer and then heat treat it at a temperature between 200 and 700°C. The oxide semiconductor film is then subjected to a second oxide semiconductor film formation. The c-axis of the crystal part is aligned in a direction parallel to the normal vector of the surface on which it is formed or the normal vector of the surface. This is a method for forming crystal parts.

[0106] The CAAC-OS film can be formed, for example, by sputtering a polycrystalline oxide semiconductor target. The sputtering target is used to form a film by sputtering. Upon impact, the crystalline regions in the sputtering target cleave from the ab plane, forming a -b: The particles peel off as plate-like or pellet-like sputtered particles with surfaces parallel to the surface. In this case, the plate-like sputtered particles may be crystalline and may be crystalline. By reaching the plate, a CAAC-OS film can be formed.

[0107] In addition, the following conditions are preferably applied to form the CAAC-OS film.

[0108] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber is In addition, the impurity concentration in the deposition gas may be reduced. A deposition gas having a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0109] In addition, by increasing the substrate heating temperature during film formation, the migration of sputtered particles after they reach the substrate is reduced. Specifically, the substrate heating temperature is set to 100° C. or higher and 740° C. or lower, preferably The deposition temperature is set to 200°C or higher and 500°C or lower. When a plate-shaped sputtered particle reaches a substrate, migration occurs on the substrate, The flat surface of the sputtered particle adheres to the substrate.

[0110] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition is reduced. The oxygen ratio in the deposition gas is preferably 30% by volume or more, and more preferably 100% by volume or more. The product is %.

[0111] As an example of a sputtering target, an In-Ga-Zn-O compound target is The details are shown below.

[0112] InO X powder, GaO Y Powder and ZnO Z The powders are mixed in a specified number of moles and then pressurized. By heat treatment at a temperature between 1000 and 1500℃, polycrystalline In-Ga -Zn-O compound target, where X, Y and Z are any positive numbers. , the predetermined molar ratio is, for example, InO X powder, GaO Y Powder and ZnO Z Powder, 2 :2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3 or 3:1:2. The type of powder and the molar ratio of the powder to be mixed depend on the sputtering target to be prepared. The setting can be changed as appropriate depending on the kit.

[0113] This concludes the description of the CAAC-OS membrane.

[0114] <Dehydration treatment (dehydrogenation treatment), oxygenation treatment (peroxygenation treatment)> After the oxide semiconductor film is formed, a dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen from the oxide semiconductor film. Then, hydrogen or moisture is removed to purify the material so that it contains as few impurities as possible, and then the material is dehydrated. (Dehydrogenation treatment) Add oxygen to the oxide semiconductor film to fill the increased oxygen vacancies. In this specification and the like, a treatment for supplying oxygen to an oxide semiconductor film is preferably performed. Such a treatment may be referred to as oxygen addition treatment or hyperoxygen treatment.

[0115] In this manner, hydrogen or moisture is removed from the oxide semiconductor film by the dehydration treatment (dehydrogenation treatment). By adding oxygen to the material, the oxygen vacancies are compensated for, resulting in an i-type (intrinsic) or In such an oxide semiconductor film, an oxide semiconductor film that is almost i-type can be obtained. In the case of , the amount of carriers derived from the donor is extremely small (close to zero), and the carrier concentration is 1 × 10 14 / cm 3 Less than 1 x 10 12 / cm 3 less than 1×10 1 1 / cm 3 less than 1.45×10 10 / cm 3 It will be less than.

[0116] In this way, the hydrogen concentration is sufficiently reduced and highly purified, and oxygen is supplied to the hydrogen gas. The oxide semiconductor layer has a reduced defect level in the energy gap caused by electron vacancies. The transistor can achieve extremely excellent off-state current characteristics. For example, The off-state current (here, the value per unit channel width (1 μm)) is 100 zA (1 zA ( Zeptoampere) is 1 x 10 -21 A) or less, preferably 10zA or less. At 85°C, it is 100zA (1×10 -19 A) or less, preferably 10zA (1×10 -2 0 In this way, the i-type (intrinsic) or substantially i-type oxide semiconductor By using the insulating layer, a transistor with extremely excellent off-current characteristics can be obtained.

[0117] (Embodiment 6) In this embodiment, a configuration that can be applied to a storage device of one embodiment of the present invention will be described with reference to FIG. FIG. 8 is a schematic cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. Specifically, the present invention relates to a storage device including a transistor and a capacitor element that have a significantly low leakage current in an off state. A part of the memory circuit is provided on an upper layer of another circuit formed by the CMOS process. .

[0118] The transistor having a significantly low leakage current in the off state is the transistor according to the fifth embodiment. The semiconductor described below is provided in a region where a channel is formed.

[0119] The memory device illustrated in FIG. 8 is a transistor having a significantly low leakage current in the off state. A part of the memory circuit 220 including the transistor 303 and the capacitor element 302 is formed by a CMOS process. The transistor 301 is provided in an upper layer of the selection circuit 236 or the memory circuit 221. Specifically, semiconductors containing group 14 of the periodic table (such as silicon) A transistor 301 including a semiconductor layer and a transistor including an oxide semiconductor layer in which a channel is formed The semiconductor layer 311 and the insulating layer 314 are also included. , a conductive layer 315, an insulating layer 316, an insulating layer 317, a connection layer 318, and a conductive layer 319a , a conductive layer 319b, and a conductive layer 319c, an insulating layer 320, a connection layer 321, and a semiconductor layer 331, an insulating layer 333, a conductive layer 334, a conductive layer 336a and a conductive layer 336b, and a conductive layer 338, an insulating layer 339, a connection layer 341, and a conductive layer 342.

[0120] With such a configuration, the transistor 303 and the capacitor element 302 can be formed on top of other circuits (for example, the memory circuit 221, the selection circuit 236, etc.), so that an increase in the occupied area of the memory device can be suppressed.

[0121] Hereinafter, each element constituting the semiconductor device according to one aspect of the present invention will be described.

[0122] <Layer including transistors formed by CMOS process>

[0123] The semiconductor layer 311 has regions 313a and 313b. Also, adjacent transistors are electrically separated by an insulating layer 312 provided in a part of the region of the semiconductor layer 311 .

[0124] As the semiconductor layer 311, for example, a semiconductor substrate can be used. Also, a semiconductor provided on another substrate can be used as the semiconductor layer 311.

[0125] The regions 313a and 313b are provided so as to be separated from each other, and are regions doped with a dopant that imparts an n-type or p-type conductivity type. The regions 313a and 313b have a function as a source region or a drain region of a transistor. Also, the regions 313a and 313b are electrically connected to the conductive layer 319a or the conductive layer 319b via the connection layer 318, respectively . ​ are electrically connected.

[0126] When the transistor 301 is an n-channel transistor, the dopant is n On the other hand, in the case of p-channel transistors, p An element that imparts electrical conductivity to the mold is used.

[0127] In addition, a low concentration region may be provided in a part of the regions 313a and 313b. The depth of the region may be, but is not limited to, smaller than the depth of the other regions.

[0128] The insulating layer 314 is disposed over the region of the semiconductor layer 311 sandwiched between the insulating layers 312. The layer 314 functions as a gate insulating layer of the transistor 301 .

[0129] The insulating layer 314 may be, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide. Silicon oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide Aluminum, hafnium oxide, organic insulating materials (such as polyimide or acrylic), etc. In addition, a layer of the material applicable to the insulating layer 314 can be laminated to form an insulating layer. Layer 314 may be configured.

[0130] The conductive layer 315 overlaps with the semiconductor layer 311 with the insulating layer 314 interposed therebetween. The region of the semiconductor layer 311 that contacts the conductive layer 31 serves as a channel forming region of the transistor 301. 5 functions as the gate of the transistor 301 .

[0131] The conductive layer 315 may be made of, for example, molybdenum, magnesium, titanium, chromium, tantalum, Metallic materials such as tungsten, aluminum, copper, neodymium, or scandium, or For the conductive layer 315, a layer of an alloy material containing these as a main component can be used. The conductive layer 315 may also be formed by laminating possible materials.

[0132] The insulating layer 316 is provided on the insulating layer 314 and is disposed between the opposing portions of the conductive layer 315. The plate is provided in contact with a pair of side surfaces.

[0133] The insulating layer 317 is provided on the conductive layer 315 and the insulating layer 316 .

[0134] The insulating layers 316 and 317 are made of the following materials among those applicable to the insulating layer 314: A layer of the same material as that applied to insulating layer 314 or a layer of a different material can be used. In addition, materials applicable to the insulating layer 316 and the insulating layer 317 are laminated to form the insulating layer 316 or the insulating layer 317. An edge layer 317 may also be configured.

[0135] The connection layer 318 is provided so as to fill the opening provided in the insulating layer 317. 13a or region 313b.

[0136] The conductive layer 319a, the conductive layer 319b, and the conductive layer 319c are provided over the insulating layer 317. The conductive layer 319a is electrically connected to the region 313a via the connection layer 318. 9b is electrically connected to region 313b via connection layer 318. Also, conductive layer 319c is It is electrically connected to the conductive layer 315 via a connecting layer 318 (not shown).

[0137] The connection layer 318 and the conductive layers 319a, 319b, and 319c include: Among the above-mentioned materials applicable to the conductive layer 315, the same material as that applied to the conductive layer 315 A layer of the same material or a layer of a different material can be used. 9a, conductive layer 319b, and conductive layer 319c are laminated to form a connection layer 318. , and the conductive layer 319a, the conductive layer 319b, and the conductive layer 319c. .

[0138] The insulating layer 320 is formed by stacking the insulating layer 317 and the conductive layers 319a, 319b, and 319c. The insulating layer 320 is formed on the insulating layer 19c. It is possible.

[0139] The connection layer 321 is provided so as to fill the opening provided in the insulating layer 320, and is a conductive layer. The connection layer 321 is electrically connected to the connection layer 319c. The composition can be used.

[0140] <Layer containing transistors and capacitive elements with extremely low leakage current in the off state>

[0141] The semiconductor layer 331 is provided on the insulating layer 320. The semiconductors described in embodiment 5 can be used.

[0142] Note that the dopant is added to the region of the semiconductor layer 331 overlapping with the conductive layer 336a and the conductive layer 336b. A doped region may be provided. The dopant may be a Group 15 element (typically nitrogen (N ), phosphorus (P), arsenic (As), and antimony (Sb), boron (B), aluminum Al, Ar, He, Ne, In, n), fluorine (F), chlorine (Cl), titanium (Ti), and zinc (Zn). It is possible to use one or more selected regions. Note that the region does not necessarily have to be provided.

[0143] The conductive layer 336a and the conductive layer 336b are provided separately from each other, and the semiconductor layer 331 The conductive layer 336a and the conductive layer 336b are electrically connected to the source of the transistor. The conductive layer 336b functions as an electrode or a drain electrode. The conductive layer 336a also functions as one electrode of the capacitor 302. .

[0144] The conductive layer 336a and the conductive layer 336b may be made of aluminum (Al), chromium (Cr), Copper (Cu), Tantalum (Ta), Titanium (Ti), Molybdenum (Mo), Tungsten ( Metals such as W, neodymium (Nd), scandium (Sc), or the metallic elements mentioned above Alloys containing the above metal elements, alloys combining the above metal elements, nitrides of the above metal elements, etc. It can be formed using manganese (Mn), magnesium (Mg), di Metal elements such as zirconium (Zr) and beryllium (Be) may also be used.

[0145] The insulating layer 333 is provided over the semiconductor layer 331, the conductive layer 336a, and the conductive layer 336b. The insulating layer 333 also functions as a gate insulating layer of the transistor. 333 also functions as a dielectric layer for the capacitance element 302 .

[0146] The insulating layer 333 may be, for example, aluminum nitride, aluminum oxide, or aluminum oxynitride. Aluminum, aluminum oxide nitride, silicon nitride, silicon oxide, silicon nitride oxide, nitric oxide A material selected from silicon oxide, tantalum oxide, or lanthanum oxide is used as a single layer or a laminate. It can be formed as follows.

[0147] The insulating layer 333 is made of hafnium silicate (HfSiO x ), nitrogen added Hafnium Silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminate HfAl x O y N z ), high-k materials such as hafnium oxide and yttrium oxide By using this, the effective thickness of the gate insulating film (e.g., silicon oxide equivalent) is not changed. By making the physical gate insulating film thicker, gate leakage can be reduced. Includes high-k materials, silicon oxide, silicon oxynitride, silicon nitride, and oxide nitride. Silicon, aluminum oxide, aluminum oxynitride, or gallium oxide It may have a laminated structure with the above.

[0148] The conductive layer 334 overlaps with the semiconductor layer 331 with the insulating layer 333 interposed therebetween. The conductive layer 334 functions as a gate of the transistor. It is preferable that the second insulating film 336 is provided so as to overlap with the first insulating film 336b.

[0149] The conductive layer 334 may be made of aluminum (Al), chromium (Cr), copper (Cu), or tantalum. (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd ), scandium (Sc), or an alloy containing the above-mentioned metal elements The above-mentioned metal elements are combined, and the above-mentioned metal elements are used as nitrides. In addition, manganese (Mn), magnesium (Mg), zirconium (Zr Metal elements such as Zn (Zn) and beryllium (Be) may also be used.

[0150] The conductive layer 334 may have a single layer structure or a stacked structure of two or more layers. Single layer structure using aluminum containing kon, and two layer structure with titanium laminated on aluminum , a two-layer structure in which titanium is laminated on titanium nitride, and a two-layer structure in which tungsten is laminated on titanium nitride. Layer structure, two-layer structure with tungsten laminated on tantalum nitride, Cu-Mg-Al alloy A two-layer structure with Cu laminated on top of titanium, and then aluminum laminated on top of that titanium. There are three-layer structures with titanium formed on top.

[0151] The conductive layer 334 may be made of indium tin oxide or indium oxide containing tungsten oxide. , indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium oxide, indium zinc oxide, and indium oxide with silicon oxide added A light-transmitting conductive material such as indium tin oxide can also be used. A laminated structure of a light-transmitting conductive material and the above metal element may also be used.

[0152] In addition, the conductive layer 334 and the semiconductor layer 331 overlap with each other and are in contact with each other. Examples of such materials include gallium oxide, nitrogen-containing indium gallium zinc oxide, and nitrogen-containing indium gallium zinc oxide. Indium tin oxide, nitrogen-containing indium gallium oxide, nitrogen-containing indium zinc oxide Nitrogen-containing tin oxide, nitrogen-containing indium oxide, and metal nitrides (InN, Z nN, etc.) may be formed.

[0153] These materials have a work function of 5 eV or more, preferably 5.5 eV or more, and the insulating layer 333 By overlapping with the semiconductor layer 331 through the insulating layer 332, the threshold voltage of the transistor can be made positive. For example, a nitrogen-containing semiconductor device can be used as a switching element. In the case of using In-Ga-Zn-O, the nitrogen concentration is at least higher than that of the semiconductor layer 331. Specifically, In-Ga-Zn-O with a nitrogen concentration of 7 atomic % or more is used.

[0154] The conductive layer 338 is provided over the conductive layer 336a with the insulating layer 333 interposed therebetween.

[0155] Here, the conductive layer 336a, the insulating layer 333, and the conductive layer 338 form a capacitor 302. will be done.

[0156] An insulating layer 339 is provided on the insulating layer 333 , the conductive layer 334 and the conductive layer 338 .

[0157] The insulating layer 339 can be formed using a material similar to that of the insulating layer 317.

[0158] The connection layer 341 is provided so as to fill the opening provided in the insulating layer 339, and the conductive layer 33 8.

[0159] The connecting layer 341 may be configured similarly to the connecting layer 318 .

[0160] The conductive layer 342 is provided on the insulating layer 339. The conductive layer 342 is connected to the insulating layer 339 via the connection layer 341. The conductive layer 338 is electrically connected to the conductive layer 338 .

[0161] The conductive layer 342 has a structure similar to that of the conductive layer 319a, the conductive layer 319b, and the conductive layer 319c. It is possible.

[0162] The structure of the transistor in FIG. 8, which has a significantly low leakage current in the off state, is a so-called top A so-called bottom gate structure may be used. This is a so-called top contact structure in which a semiconductor layer is provided on a conductive layer. A so-called bottom contact structure may also be used.

[0163] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. . [Explanation of symbols]

[0164] 101 OS transistor 102 Holding capacity 121 Memory circuit 136 Selection circuit 140 Storage device 201 Transistor 202 Holding capacity 203 Transistor 204 Buffer Circuit 205 Inverter circuit 206 Inverter Circuit 207 Inverter Circuit 208 Inverter Circuit 209 Inverter Circuit 210 Inverter circuit 211 Clocked Inverter Circuit 212 Clocked Inverter Circuit 213 Analog Switch Circuit 214 Analog Switch Circuit 220 Memory circuit 221 Memory circuit 236 Selection Circuit 240 Storage device 301 Transistor 302 Capacitive element 303 Transistor 311 Semiconductor layer 312 Insulating layer 313a area 313b area 314 Insulating layer 315 Conductive Layer 316 Insulating Layer 317 Insulating Layer 318 Connection Layer 319a conductive layer 319b Conductive layer 319c conductive layer 320 Insulating layer 321 Connection Layer 331 Semiconductor Layer 333 Insulating Layer 334 Conductive Layer 336a conductive layer 336b Conductive layer 338 Conductive Layer 339 Insulating Layer 341 Connection Layer 342 Conductive Layer

Claims

[Claim 1] A first transistor; A second transistor; and A holding capacity; A selection circuit; A memory circuit, one of a source and a drain of the first transistor is directly connected to one terminal of the storage capacitor and one of a source and a drain of the second transistor; the other of the source and the drain of the first transistor is electrically connected to a first input terminal of the selection circuit; the other of the source and the drain of the second transistor is electrically connected to a second input terminal of the selection circuit; an output terminal of the selection circuit is electrically connected to an input terminal of the storage circuit; the first transistor and the second transistor each include an oxide semiconductor layer; the oxide semiconductor layer has a channel formation region, the other of the source and the drain of the first transistor is electrically connected to a first input terminal of the selection circuit via a first inverter circuit; the other of the source and the drain of the second transistor is electrically connected to a second input terminal of the selection circuit via a second inverter circuit.

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