High voltage device

Abstract

To provide an HV component with improved performance in terms of insulation strength and reliability as compared with a conventional two-node method.SOLUTION: A high voltage device includes: a first electrode; a second electrode, disposed below the first electrode, spaced from the first electrode; and a dielectric layer disposed between the first electrode and the second electrode. The first electrode further extends in at least one lateral direction with respect to the second electrode.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to high voltage (HV) components or devices for microelectronic devices, and in particular, but not exclusively, to galvanic isolation devices. [Background technology]

[0002] In some applications, high insulation capability between metal plates can be a key requirement. In galvanic isolation applications, the requirement for insulation strength can exceed 5 kVRMS (root mean square). Due to limitations in the insulation (dielectric) layer capabilities of available wafer fabrication processes, it can be difficult or even impossible to achieve such levels of insulation. This is because the stacking of intermetal dielectric layers in CMOS processes limits the insulation thickness to only a few microns, which is insufficient to achieve a sufficiently high insulation strength. Therefore, device designs need to be improved to help redistribute the electric field and avoid / reduce high peak values ​​of the electric field on the device.

[0003] US Patent No. 9,583,558 is concerned with supporting lateral isolation between HV components (e.g. HV capacitors) and the low voltage (LV) side (logic, gate drivers, etc.). The HV capability is enhanced using a dielectric stack composed of different dielectric materials. US Patent No. 8,643,138 uses two isolation capacitors in series to increase the breakdown voltage.

[0004] Figure 1 shows a simulation of the equipotential lines of the electric field of a conventional HV component with vertically stacked nodes. In a CMOS process, semiconductor substrates are typically used to create microelectronic circuits. In a device such as that shown in Figure 1, the semiconductor substrate a107 itself has the effect of a wide lateral extension of the main plate a102 of the LV node. As a result, when a voltage is applied, the electrostatic potential is not distributed symmetrically between the HV node a101 and the LV node a102. In particular, at the edges of the nodes, the potential lines bend differently in the HV and LV nodes. The bend around the edge a1011 of the HV node a101 is much tighter than the bend around the edge of the LV node. Furthermore, the bend of the potential lines becomes tighter as the distance between the nodes decreases and thus the strength of the electric field also increases. A localized high electric field can cause an electrical breakdown of the dielectric and subsequently the entire HV component. Thus, in this device, a breakdown is caused at the edge a1011 of the main plate a101 of the HV node. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent No. 9,583,558 [Patent Document 2] U.S. Patent No. 8,643,138 Summary of the Invention

[0006] Aspects and preferred features are set out in the accompanying claims.

[0007] The present disclosure relates to HV components (e.g., capacitors or transformers) that exhibit improved performance in terms of dielectric strength and reliability compared to traditional two-node approaches without adding dielectric thickness between the nodes or increased process complexity.

[0008] Advantages of the disclosed device include the following: The device can be realized within standard back-end-of-line (BEOL) technologies, The device achieves significant improvement in dielectric strength compared to conventional approaches for the same insulating dielectric thickness; Compared to conventional designs, lower process costs are achieved for the same insulation class, The features of the disclosed devices can be applied / combined in any other manner, for example used in an integrated on-chip solution.

[0009] The disclosed HV components overcome the inherent asymmetric shape of the nodes in conventional devices and balance the electric fields at the node edges. This balancing of the electric fields significantly enhances the insulation strength of the HV components while using the same dielectric thickness between the HV and LV nodes.

[0010] The HV components can be micro-transformers or parallel plate capacitors and can withstand very high voltages.

[0011] According to one aspect of the disclosure, a high voltage device is provided that includes a first electrode, a second electrode disposed below and spaced apart from the first electrode, and a dielectric layer disposed between the first electrode and the second electrode, where the first electrode extends further in at least one lateral direction relative to the second electrode, thereby balancing the electric fields at the edges of the electrodes compared to a device in which the first electrode does not extend beyond the second electrode, thereby resulting in improved insulation strength of the HV component and enabling the device to withstand higher voltages.

[0012] The first electrode may comprise a first portion and a second portion, the first portion may be located above the second electrode, and the second portion may not be located above the second electrode. In other words, a portion of the first electrode may be located above the second electrode, and a portion of the first electrode may extend beyond the edge of the second electrode such that the first electrode overhangs the second electrode. The overhang of the first electrode over the second electrode compensates for the asymmetric distribution of the electrostatic potential. The first portion of the first electrode and the second portion of the first electrode may not be physically separated, but may define different regions within the first electrode.

[0013] The first electrode and the second electrode can comprise capacitor plates. In this configuration, the device can be a parallel plate capacitor.

[0014] Alternatively, the first electrode and the second electrode may comprise a transformer coil, in this configuration the device may be a micro-transformer.

[0015] The device may further comprise a semiconductor substrate disposed beneath the second electrode. The substrate may be electrically floating. Alternatively, the substrate may be electrically connected to the second electrode.

[0016] The first electrode can be configured to be biased at a higher absolute voltage than the second electrode.

[0017] The device may further comprise a first field plate electrically connected to the first electrode. Introducing the first field plate allows for further reduction of the electric field at the edge of the first electrode. The first field plate may further extend in at least one lateral direction relative to the first electrode. Extending the first field plate beyond the edge of the first electrode helps to further reduce the electric field at the edge of the first electrode.

[0018] The device may further comprise a second field plate electrically connected to the second electrode. By introducing the second field plate, the electric field at the edge of the second electrode is reduced for high values ​​of the distance between the edge of the first electrode and the edge of the second electrode while keeping the electric field at the edge of the first electrode reduced. The second field plate may further extend in at least one lateral direction relative to the second electrode. By positive overhanging beyond the edge of the second electrode, the second field plate may reduce the electric field at the edge of the second electrode.

[0019] The device may further comprise a passivation layer disposed over the first electrode.

[0020] The device can be fabricated using complementary metal oxide semiconductor (CMOS) compatible processes.

[0021] Advantageously, at least one electrode may include a rounded corner in the vertical direction. The introduction of a rounded corner further reduces the electric field at the corner, since the electric field at the corner is proportional to the (-1)th power of the corner radius. Preferably, the corner of the lower edge of the first electrode may have a rounded shape, and the corner of the upper edge of the second electrode may have a rounded shape. The corners of the lower edge of the first electrode and the upper edge of the second electrode have the highest electric field, so rounding these corners further improves the high voltage capability of the device.

[0022] Preferably, at least one electrode may include laterally rounded corners, the introduction of which further reduces the electric field at the corners.

[0023] More preferably, at least one electrode may have a substantially circular shape in a lateral dimension, which further improves the reduction of the electric field since the electric field at a corner is proportional to the (minus one) power of the corner radius.

[0024] Advantageously, the first electrode and the second electrode can have a geometrically similar shape in the lateral dimension. In addition, the first electrode and the second electrode can be arranged concentrically in the lateral dimension. These features of the present structure reduce non-uniform electric field redistribution and avoid causing electric field "hot spots."

[0025] The device may be a galvanic isolation device.

[0026] According to a further aspect of the present disclosure, there is provided a method of manufacturing a high voltage semiconductor-based device, the method including forming a first electrode, forming a second electrode disposed below and spaced apart from the first electrode, and forming a dielectric layer disposed between the first electrode and the second electrode, the first electrode extending further in at least one lateral direction than the second electrode.

[0027] Some preferred embodiments of the present disclosure will now be described, by way of example only, with reference to the accompanying drawings, in which: [Brief description of the drawings]

[0028] [Figure 1] A simulation of the electric field equipotential lines of a conventional HV component. [Diagram 2] FIG. 2 is a schematic diagram of HV components according to one embodiment of the present disclosure. [Figure 3(a)] Simulation of the distribution of electrostatic potential for different overhang values ​​between a first (top) electrode and a second (bottom) electrode in an HV component, where the simulation of the electrostatic potential distribution in a component with symmetric first and second electrodes. [Figure 3(b)]Simulation of the distribution of electrostatic potential for different overhang values ​​between a first (top) and a second (bottom) electrode in an HV component, where the second (bottom) electrode extends beyond the first (top) electrode. [Figure 3(c)] 1 is a simulation of electrostatic potential distribution within a component in which a first (top) electrode extends beyond a second (bottom) electrode, according to one embodiment of the present disclosure. [Figure 4] FIG. 13 is a schematic diagram of an HV component according to a further embodiment of the present disclosure, the component comprising a field plate on the second electrode. [Diagram 5] FIG. 13 is a schematic diagram of an HV component according to a further embodiment of the present disclosure, the component comprising a field plate on a first electrode. [Figure 6] FIG. 5 is a schematic diagram showing the geometric dimensions of the HV components of FIG. [Figure 7] FIG. 6 is a schematic diagram showing the geometric dimensions of the HV components of FIG. [Figure 8] 3 shows the simulated dependence of the electric field at the electrode edges of FIG. 2 on the overhang between the second electrode and the first electrode. [Figure 9] 3 is a simulation result of optimum values ​​of overhang between the second electrode and the first electrode of FIG. 2 for different dielectric thicknesses and different heights above the substrate. [Figure 10(a)] FIG. 13 is a plan view of an example capacitor layout design according to a further embodiment of the present disclosure, which is an embodiment of a capacitor layout in which the plates have rounded corners. [Figure 10(b)] FIG. 13 is a plan view of an example capacitor layout design according to a further embodiment of the present disclosure, the capacitor layout having plates with circular shapes. [Figure 11] FIG. 1 is a diagram illustrating the definition of a corner radius. [Figure 12] FIG. 11 illustrates vertically the location of electric field "hot spots" within a component according to one embodiment. [Figure 13] 1A-1C illustrate different shapes of main and field plate corners according to embodiments of the present disclosure: (a) a plate with no vertical radius at the corners, (b) a plate with rounded corners on the side of the plate facing the opposing plate, and (c) a plate with rounded corners on the side of the plate facing the opposing plate. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] FIG. 2 shows a schematic diagram of an HV component according to one embodiment of the present disclosure. In this embodiment, the component has a high voltage (HV) node including a first electrode or first main plate a101 and a low voltage (LV) node including a second electrode or second main plate a102 formed on a substrate a107. In one example, the electrodes can be transformer coils or plates of a parallel capacitor. The first electrode is configured with a higher absolute voltage than the second electrode. There is a positive overhang of the HV node main plate a101 of a distance d104 beyond the LV node main plate a102. This compensates for the asymmetric distribution of electrostatic potential. There can be a connection linking the LV node a102 and the substrate a107 to similar electrostatic potentials or the substrate a107 can be left floating.

[0030] FIG. 3 shows a simulation of the distribution of electrostatic potential for different overhangs between the first (top) electrode a101 and the second (bottom) electrode a102.

[0031] Figure 3(a) shows a simulation of a component with symmetric first (top) and second (bottom) electrodes. Within the HV component, the distribution of electrostatic potential is not symmetric in the vertical direction because the doped substrate acts as a large extension of the bottom electrode. At the edges of the nodes, the potential lines bend differently for HV and LV nodes. The bend around the edge of the HV node is much tighter than the bend around the edge of the LV node. Furthermore, the bend of the potential lines becomes tighter as the distance between the nodes decreases and thus the strength of the electric field also increases. In this example, the electric field is maximum at the edge of the top electrode. This point is therefore weak and susceptible to electrical breakdown. A local electric field that is too high can cause an electrical breakdown of the dielectric and subsequently the entire HV component.

[0032] Figure 3(b) shows a simulation of the electrostatic potential distribution for an HV component where the second (bottom) electrode extends beyond the first (top) electrode. This HV component is more susceptible to breakdown due to the higher electric field at the edge of the top electrode.

[0033] FIG. 3(c) shows a simulation of the electrostatic potential distribution of an HV component in which the first (top) electrode extends beyond the second (bottom) electrode, according to an embodiment of the present disclosure. The electrostatic potential distribution is affected by shifting the electrode edges relative to each other, which is due to the field plate effect. In FIG. 3(c), the electric field at the edge of the top electrode is lowered, thereby improving the electrical stability of the component. The difference between passivation and bulk dielectric is that the passivation is the last layer in the stack. Passivation is weaker than bulk because the potential distribution on the top surface is less controlled. Since passivation is generally weaker than bulk materials, balancing the electric field distribution vertically within the component also helps to reduce undesirable effects such as surface discharge, since it relieves the electrical stress on the passivation.

[0034] 4 shows a schematic diagram of an HV component a100 according to a further embodiment of the present disclosure. In this embodiment, the component includes an HV node a101 and LV nodes a102, a103, a104, a106 separated by a dielectric medium a105. The dielectric a105 can be SiN, SiO 2 , or other dielectric materials, or it can be a combination of layers of different dielectrics. The dielectric a105 acts as the main insulating layer between the HV node a101 and the LV node a102 and can be implemented in different ways, for example in the form of a successively deposited dielectric layer, or as a stack of several intermetal dielectric layers. The HV node a101 and the LV nodes a102, a103, a104, a106 are generally made of metal, polysilicon, or another conductive material. The HV component a100 can be surrounded by other parts of the chip a200, or can even remain alone as a discrete device. The chip can be placed entirely on a substrate a107, or the substrate can be eliminated. In this embodiment, the LV node includes the LV main plate a102, the LV field plate a103, the connection to the contact pad a104, and the connection between the plates a106. The connection to the contact pad a104 is implemented in a separate layer, but can also be in the same layer as the field plate a103. The main plate a101 can be directly contacted by wire bonding through openings in the passivation a109. The additional field plate provides a redistribution of the electric field from the "hot spot" to other parts of the structure.

[0035] FIG. 5 shows a schematic diagram of a HV component a100 according to a further embodiment of the present disclosure. In this embodiment, the HV node includes a main plate a101 and a field plate a108. The field plate a108 can be directly contacted by wire bonding through an opening in the passivation a109. The LV node includes a main plate a102, a field plate a103, a connection to a contact pad a104, and a connection between plates a106. By introducing the field plate a108 in the HV node, a further reduction in the electric field at the main plate edge a1011 of the HV node is achieved. The function of the field plate a108 is similar to that described for the LV field plate a103, but in this case the electric field is reduced at the main plate a101 of the HV node. In FIG. 5, the field plate a108 of the HV node is used in combination with the field plate a103 of the LV node, but it can also be used separately.

[0036] FIG. 6 shows a schematic diagram illustrating the geometric dimensions of the HV components of FIG. 4. The thickness d100 of the dielectric a105 between the HV and LV nodes is shown in FIG. 6. The thickness d100 can be about 3 μm or more. The distance d101 is between the top edge of the main plate of the LV node a102 and the field plate a103. The distance between the top edge of the LV field plate a103 and the surface of the substrate a107 is represented by d102. The lateral extension of the LV field plate a103 beyond the main plate a102 of the LV node is shown as d103. The distance d104 represents the lateral extension of the main plate of the HV node a101 beyond the edge of the main plate of the LV node a102. The field plate a103 of the LV node allows to reduce the electric field at the edge of the main plate a102 of the LV node for higher values ​​of d104 while keeping the electric field at the edge of the HV node a101 reduced. Due to a certain positive overhang d103 beyond the edge of the main plate a102, the field plate allows to reduce the electric field at the edge of the main plate a102. The electric field at the edge of a101 increases only slightly as long as d103 is configured for a distance that is not too large. In other words, the field plate a103 of the LV node does not extend farther than the HV node.

[0037] 7 shows a schematic diagram illustrating the geometric dimensions of the HV component of FIG. 5 with the field plate a108 mounted to the HV node. The extension of the HV node field plate a108 beyond the edge of the HV node main plate a101 is shown as d105. The specific value of the overhang d105 of the HV field plate a108 beyond the HV main plate a101 depends on the overall design of the HV component including, among other factors, the dielectric thickness d100, the distance d106 between the HV main plate and the field plate, and the type of substrate a107.

[0038] FIG. 8 shows the simulated dependence of the electric field at the edges of a101 and a102 on the overhang d104 between the HV node a101 and the LV node a102. From the graph, it can be seen that the optimal overhang was the intersection of the two lines, and the electric field is lowest for a certain positive overhang d104, in other words, the HV node main plate a101 overhangs the LV node main plate a102. The specific value of the overhang d104 depends on the height d107 of the LV node main plate a102 above the substrate a107, as well as the selected conductivity of the substrate a107 and the thickness d100 of the dielectric a105. For a larger overhang d104 above 5 μm, the electric field at the edges of the LV node main plate a102 becomes high, which causes a dielectric breakdown there. It can also be seen that the electric field at the edges of a101 decreases further with increasing d104. In the example shown in FIG. 8, the dielectric a105 has a thickness d100 of 11 μm, the LV node main plate a102 is formed on the second metal layer with a distance to the substrate a107 of ≈4 μm, and the optimal overhang d104 is about 5 μm.

[0039] Figure 9 shows the optimum values ​​of d104 for different dielectric thicknesses d100 and two different heights d107 above the substrate. It can be seen that for thicker dielectrics and lower heights d107, a larger overhang d104 is required to obtain the highest insulation strength for HV components.

[0040] FIG. 10 shows a plan view of an example of a capacitor design. This figure shows a cross-section of the structure shown in FIG. 4. It can be seen that all corners are rounded. FIG. 10(a) shows a first embodiment where the corners are rounded. FIG. 10(b) shows a further embodiment where a circular shape is used to create the nodes and plates. The reduction in the electric field is greatest when the maximum radius of rounding is achieved for a given structure size. The radius of rounding is shown in FIG. 11. This is because the electric field at the corners of the plate is proportional to the negative first power of the corner radius, in other words E≈1 / R. This applies to the shape of the conductive nodes, plates, and other parts of the device (e.g., the connections between the nodes and the contact pads).

[0041] Using circular shapes for the plates and nodes may not be feasible, but field improvements may occur for radius of roundness defined as R1>20um and R2>5um, as shown in FIG. 11.

[0042] In the embodiment of Figures 10(a) and 10(b), the field plate overhang is the same throughout the structure to avoid non-uniform electric field redistribution and to avoid causing electric field "hot spots".

[0043] 12 shows the locations of electric field "hot spots" in the vertical direction within a component according to one embodiment. These locations show where the maximum electric field can be found and where corner rounding reduces the electric field. Reducing sharp corners in the vertical direction improves the electric field distribution.

[0044] Figure 13 shows various shapes of the corners of the main and field plates. Due to the relationship between the electric field and the corner radius (E≈1 / R), the sharp corners in Figure 13(a) do not improve the electric field distribution. Rounding the corners on the sides of the nodes oriented to face the opposing plate or node, as in the device design shown in Figure 13(b,c), improves the electric field distribution. Increasing the radius R3 improves the reduction of the electric field. If metal is used for the plates or nodes, the rounding can be achieved, for example, by adjusting the metal etching process.

[0045] Those skilled in the art will appreciate that in the foregoing description and in the appended claims, positional terms such as "above," "overhanging," "below," "laterally," and the like are made with reference to schematic views of the device such as those showing standard cross-sectional perspective views and those shown in the accompanying drawings. These terms are used for ease of reference but are not intended to be limiting in nature. Thus, these terms should be understood to refer to the device when oriented as shown in the accompanying drawings.

[0046] Although the present disclosure has been described with respect to the preferred embodiments as described above, it should be understood that these embodiments are merely exemplary and the claims are not limited to these embodiments. Those skilled in the art will be able to make modifications and alternatives in light of the disclosure that are considered to fall within the scope of the appended claims. Each feature disclosed or illustrated in this specification can be incorporated into the present disclosure, whether alone or in any suitable combination with other features disclosed or illustrated in this specification. [Explanation of symbols]

[0047] R3 radius a100 HV Components a101 HV node, 1st main plate, 1st electrode a1011 Edge a102 LV node, 2nd main plate, 2nd electrode, LV main plate a103 LV field plate a104 Contact pad A105 Dielectric a106 Plate a107 Board a108 field plate a109 Passivation a200 Chip d100 Thickness d101 distance d102 distance d103 Overhang d104 Overhang, distance d105 Overhang d106 Extension, distance d107 Height

Claims

1. A first electrode; a second electrode disposed below the first electrode and spaced apart from the first electrode; a dielectric layer disposed between the first electrode and the second electrode; Equipped with the first electrode further extends in at least one lateral direction relative to the second electrode; High voltage devices.

2. 2. The device of claim 1, wherein the first electrode comprises a first portion and a second portion, the first portion being disposed above the second electrode and the second portion not being disposed above the second electrode.

3. The device of claim 1 or 2, wherein the first electrode and the second electrode comprise capacitor plates.

4. The device of claim 1 or 2, wherein the first electrode and the second electrode comprise transformer coils.

5. The device of claim 1 , further comprising a semiconductor substrate disposed beneath the second electrode.

6. The device of claim 5 , wherein the substrate is electrically floating.

7. The device of claim 5 , wherein the substrate is electrically connected to the second electrode.

8. 8. The device of claim 1, wherein the first electrode is configured to be biased at a higher absolute voltage than the second electrode.

9. The device of claim 1 , further comprising a first field plate electrically connected to the first electrode.

10. The device of claim 9 , wherein the first field plate further extends in at least one lateral direction relative to the first electrode.

11. The device of claim 1 , further comprising a second field plate electrically connected to the second electrode.

12. The device of claim 11 , wherein the second field plate further extends in at least one lateral direction relative to the second electrode.

13. The device of claim 1 , further comprising a passivation layer disposed over the first electrode.

14. The device of claim 1 , wherein the device is fabricated using a CMOS compatible process.

15. 15. The device of claim 1, wherein at least one electrode includes rounded corners in the vertical direction.

16. 16. The device of claim 15, wherein a lower edge corner of the first electrode has a rounded shape and an upper edge corner of the second electrode has a rounded shape.

17. 17. The device of claim 1, wherein at least one electrode includes rounded corners in the lateral direction.

18. 18. A device according to any one of claims 1 to 17, wherein at least one electrode has a substantially circular shape in a lateral dimension.

19. 19. The device of claim 1, wherein the first electrode and the second electrode have similar geometric shapes in a lateral dimension.

20. 20. The device of claim 19, wherein the first electrode and the second electrode are arranged concentrically in a lateral dimension.

21. 21. The device of any one of claims 1 to 20, which is a galvanic isolation device.

22. 1. A method for manufacturing a high voltage semiconductor-based device, comprising: forming a first electrode; forming a second electrode disposed below the first electrode and spaced apart from the first electrode; forming a dielectric layer disposed between the first electrode and the second electrode; The method, wherein the first electrode extends further in at least one lateral direction than the second electrode.

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