Multilayer ceramic electronic component

Abstract

To provide a multilayer ceramic electronic component capable of improving bending resistance.SOLUTION: A multilayer ceramic electronic component comprises: a laminated body 10; and a pair of external electrodes 40 disposed at both end parts of the laminated body 10. Each external electrode 40 includes a main-surface-side external electrode 411A. The main-surface-side external electrode 411A includes: a main-surface-side base electrode layer 511A; and a main-surface-side plating layer 611A formed in an upper layer than the main-surface-side base electrode layer 511A. The main-surface-side external electrode 411A includes a concave part 510A concaved toward the laminated body 10 side in a cross-sectional view along a lamination direction and a length direction of the laminated body 10. The main-surface-side base electrode layer 511A has: a concave corresponding region 550 corresponding to the concave part 510A; and peripheral regions 560 and 570 adjacent to the concave corresponding region 550 in the length direction. A metal density of the concave corresponding region 550 is lower than the metal density of the peripheral regions 560 and 570.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic electronic component. [Background technology]

[0002] Multilayer ceramic capacitors have been known as multilayer ceramic electronic components. Generally, a multilayer ceramic capacitor includes a laminate in which dielectric layers and internal electrode layers are alternately stacked, and external electrodes provided on both end surfaces of the laminate. For example, Patent Document 1 discloses a multilayer ceramic capacitor having the above-described structure, in which the external electrodes include base electrode layers formed by baking. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-243249 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in this type of multilayer ceramic capacitor, there is a concern that when the capacitor is mounted on a substrate, bending stress generated in the external electrodes is transmitted to the laminate, causing cracks in the laminate, etc. Therefore, a multilayer ceramic capacitor with improved bending resistance is desired.

[0005] An object of the present invention is to provide a multilayer ceramic electronic component that can improve resistance to bending. [Means for solving the problem]

[0006] A multilayer ceramic electronic component according to the present invention comprises a laminate including a plurality of ceramic layers and a plurality of internal conductor layers alternately stacked in a stacking direction, and including a first main surface and a second main surface opposing each other in the stacking direction, a first end surface and a second end surface opposing each other in a longitudinal direction perpendicular to the stacking direction, and a first side surface and a second side surface opposing each other in a width direction perpendicular to the stacking direction and the longitudinal direction; and a pair of external electrodes disposed spaced apart from each other at both ends of the laminate in the longitudinal direction, the external electrode includes a main surface side external electrode arranged on at least one of the first main surface and the second main surface, the main surface side external electrode having a main surface side base electrode layer and a main surface side plating layer formed above the main surface side base electrode layer, the main surface side external electrode has a recess that is recessed toward the laminate in a cross-sectional view along the stacking direction and the length direction, the main surface side base electrode layer has a recess corresponding to the recess and a peripheral region adjacent to the recess corresponding region in the length direction, and the metal density of the recess corresponding region is lower than the metal density of the peripheral region. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a multilayer ceramic electronic component that can improve resistance to bending. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is an external perspective view of a multilayer ceramic capacitor according to an embodiment of the present invention; [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II of FIG. [Figure 3] FIG. 3 is a cross-sectional view taken along the line III-III in FIG. 2. [Figure 4A] FIG. 3 is a cross-sectional view taken along the line IVA-IVA in FIG. 2. [Figure 4B] 4 is a cross-sectional view taken along line IVB-IVB of FIG. 2. [Figure 5A] 3 is an enlarged view of a portion indicated by VA in FIG. 2, showing a cross section of a first main surface side external electrode. FIG. [Figure 5B] FIG. 5B is a diagram corresponding to FIG. 5A and showing a cross section of a first main surface side external electrode. [Figure 6A] 5A to 5C are diagrams illustrating a method for manufacturing a multilayer ceramic capacitor according to an embodiment, showing a step of forming external electrodes on a laminate. [Figure 6B] 5A to 5C are diagrams illustrating a method for manufacturing a multilayer ceramic capacitor according to an embodiment, showing a step of forming external electrodes on a laminate. [Figure 7A] FIG. 1 is a diagram showing a multilayer ceramic capacitor with a double structure. [Figure 7B] FIG. 1 is a diagram showing a multilayer ceramic capacitor with a triple structure. [Figure 7C] FIG. 1 is a diagram showing a multilayer ceramic capacitor with a four-element structure. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, a multilayer ceramic capacitor 1 as a multilayer ceramic electronic component according to an embodiment of the present disclosure will be described with reference to the drawings. Fig. 1 is an external perspective view of the multilayer ceramic capacitor 1 according to the embodiment. Fig. 2 is a cross-sectional view taken along II-II in Fig. 1. Fig. 3 is a cross-sectional view taken along III-III in Fig. 2. Fig. 4A is a cross-sectional view taken along IVA-IVA in Fig. 2. Fig. 4B is a cross-sectional view taken along IVB-IVB in Fig. 2.

[0010] 1, the multilayer ceramic capacitor 1 according to the embodiment has a substantially rectangular parallelepiped shape. The multilayer ceramic capacitor 1 includes a laminate 10 having a substantially rectangular parallelepiped shape and a pair of external electrodes 40 disposed at both ends of the laminate 10 while being spaced apart from each other.

[0011] In FIG. 1, arrow T indicates the stacking direction of the multilayer ceramic capacitor 1 and the laminate 10. This stacking direction T also corresponds to the thickness direction and height direction of the multilayer ceramic capacitor 1 and the laminate 10. In FIG. 1, arrow L indicates the length direction of the multilayer ceramic capacitor 1 and the laminate 10, which is perpendicular to the stacking direction T. In FIG. 1, arrow W indicates the width direction of the multilayer ceramic capacitor 1 and the laminate 10, which is perpendicular to the stacking direction T and the length direction L. A pair of external electrodes 40 are respectively disposed at one end and the other end of the length direction L of the laminate 10.

[0012] 1 to 4B show an XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The stacking direction T of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction. Here, the cross section shown in FIG. 2 is also referred to as an LT cross section. The cross section shown in FIG. 3 is also referred to as a WT cross section. The cross sections shown in FIGS. 4A and 4B are also referred to as LW cross sections.

[0013] As shown in Figures 1 to 4B, the laminate 10 includes a first main surface TS1 and a second main surface TS2 facing in the stacking direction T, a first end surface LS1 and a second end surface LS2 facing in a length direction L perpendicular to the stacking direction T, and a first side surface WS1 and a second side surface WS2 facing in a width direction W perpendicular to the stacking direction T and the length direction L.

[0014] As shown in FIG. 1, the laminate 10 has a substantially rectangular parallelepiped shape. The dimension of the laminate 10 in the length direction L is not necessarily longer than the dimension in the width direction W. The corners and ridges of the laminate 10 are preferably rounded. A corner is a portion where three surfaces of the laminate intersect, and a ridge is a portion where two surfaces of the laminate intersect. Incidentally, unevenness may be formed on part or all of the surfaces constituting the laminate 10.

[0015] The dimensions of the laminate 10 are not particularly limited, but if the dimension of the laminate 10 in the length direction L is defined as the L dimension, then the L dimension is preferably 0.2 mm or more and 10 mm or less. If the dimension of the laminate 10 in the stacking direction T is defined as the T dimension, then the T dimension is preferably 0.05 mm or more and 10 mm or less. If the dimension of the laminate 10 in the width direction W is defined as the W dimension, then the W dimension is preferably 0.1 mm or more and 10 mm or less.

[0016] As shown in Figures 2 and 3, the laminate 10 has an inner layer portion 11, and a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13 arranged to sandwich the inner layer portion 11 in the stacking direction T.

[0017] The internal layer portion 11 includes a plurality of dielectric layers 20 as a plurality of ceramic layers stacked alternately in the stacking direction T, and a plurality of internal electrode layers 30 as a plurality of internal conductor layers. The internal layer portion 11 includes, in the stacking direction T, the internal electrode layer 30 located closest to the first principal surface TS1 to the internal electrode layer 30 located closest to the second principal surface TS2. In the internal layer portion 11, the multiple internal electrode layers 30 are arranged opposite each other with the dielectric layer 20 interposed therebetween. The internal layer portion 11 is a portion that generates electrostatic capacitance and essentially functions as a capacitor.

[0018] The plurality of dielectric layers 20 are made of a dielectric material. The dielectric material may be, for example, a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. The dielectric material may also be a material containing these main components plus a secondary component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound. It is particularly preferable that the dielectric material contain BaTiO3 as the main component.

[0019] The thickness of the dielectric layer 20 is preferably 0.2 μm or more and 15 μm or less. The number of laminated dielectric layers 20 is preferably 10 or more and 1200 or less. Note that this number of dielectric layers 20 is the total number of the dielectric layers 20 in the inner layer portion 11 and the number of the dielectric layers 20 in each of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0020] The multiple internal electrode layers 30 include multiple first internal electrode layers 31 as multiple first internal conductor layers and multiple second internal electrode layers 32 as multiple second internal conductor layers. The first internal electrode layers 31 and the second internal electrode layers 32 are alternately arranged in the stacking direction T with the dielectric layer 20 sandwiched therebetween. The first internal electrode layers 31 extend to the first end face LS1. The second internal electrode layers 32 extend to the second end face LS2. In the following, when it is not necessary to distinguish between the first internal electrode layers 31 and the second internal electrode layers 32, the first internal electrode layers 31 and the second internal electrode layers 32 may be collectively referred to as the internal electrode layers 30.

[0021] 4A, the first internal electrode layer 31 has a first opposing portion 31A and a first lead portion 31B. The first opposing portion 31A is a region facing the second internal electrode layer 32 with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10. The first lead portion 31B is a portion that extends from the first opposing portion 31A to the first end face LS1 and is exposed at the first end face LS1.

[0022] 4B, the second internal electrode layer 32 has a second opposing portion 32A and a second lead portion 32B. The second opposing portion 32A is a region facing the first internal electrode layer 31 with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10. The second lead portion 32B is a portion that extends from the second opposing portion 32A to the second end face LS2 and is exposed at the second end face LS2.

[0023] In the embodiment, the first facing portion 31A and the second facing portion 32A face each other with the dielectric layer 20 interposed therebetween, thereby forming capacitance and exhibiting the characteristics of a capacitor.

[0024] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle. The shapes of the first drawer portion 31B and the second drawer portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle.

[0025] The width direction W dimension of the first facing portion 31A and the width direction W dimension of the first lead portion 31B may be the same dimension, or one of the dimensions may be smaller. The width direction W dimension of the second facing portion 32A and the width direction W dimension of the second lead portion 32B may be the same dimension, or one of the dimensions may be smaller.

[0026] The first internal electrode layer 31 and the second internal electrode layer 32 are made of an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0027] The thickness of each of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably, for example, 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably 10 or more and 1000 or less.

[0028] As shown in FIGS. 2 and 3 , the first main surface side outer layer portion 12 is located on the first main surface TS1 side of the laminate 10. The first main surface side outer layer portion 12 is an assembly of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. On the other hand, the second main surface side outer layer portion 13 is located on the second main surface TS2 side of the laminate 10. The second main surface side outer layer portion 13 is an assembly of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13 may both be the same as the dielectric layers 20 used in the internal layer portion 11.

[0029] The laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is a portion where the first counter portion 31A of the first internal electrode layer 31 and the second counter portion 32A of the second internal electrode layer 32 face each other. The counter electrode portion 11E is configured as a part of the inner layer portion 11. FIGS. 4A and 4B show the ranges of the counter electrode portion 11E in the width direction W and length direction L. The counter electrode portion 11E is also referred to as the effective portion of the capacitor.

[0030] The laminate 10 has a side surface outer layer portion. The side surface outer layer portion includes a first side surface outer layer portion WG1 and a second side surface outer layer portion WG2. The first side surface outer layer portion WG1 is a portion including the dielectric layer 20 located between the counter electrode portion 11E and the first side surface WS1. The second side surface outer layer portion WG2 is a portion including the dielectric layer 20 located between the counter electrode portion 11E and the second side surface WS2. Figures 3, 4A, and 4B show the ranges in the width direction W of the first side surface outer layer portion WG1 and the second side surface outer layer portion WG2. The side surface outer layer portion is also referred to as a W gap or a side gap.

[0031] The laminate 10 has an end surface side outer layer portion. The end surface side outer layer portion includes a first end surface side outer layer portion LG1 and a second end surface side outer layer portion LG2. The first end surface side outer layer portion LG1 is a portion located between the counter electrode portion 11E and the first end face LS1, and includes the dielectric layer 20 and the first lead portion 31B. That is, the first end surface side outer layer portion LG1 is an assembly of the portions of the plurality of dielectric layers 20 on the first end face LS1 side and the plurality of first lead portions 31B. The second end surface side outer layer portion LG2 is a portion located between the counter electrode portion 11E and the second end face LS2, and includes the dielectric layer 20 and the second lead portion 32B. That is, the second end surface side outer layer portion LG2 is an assembly of the portions of the plurality of dielectric layers 20 on the second end face LS2 side and the plurality of second lead portions 32B. 2, 4A, and 4B show the range of the first end-side outer layer portion LG1 and the second end-side outer layer portion LG2 in the length direction L. The end-side outer layer portions are also called L gaps or end gaps.

[0032] As shown in Figures 1 and 2, the external electrode 40 has a first external electrode 40A arranged on the first end face LS1 side of the laminate 10, and a second external electrode 40B arranged on the second end face LS2 side of the laminate 10.

[0033] The first external electrode 40A and the second external electrode 40B have the same basic configuration. The first external electrode 40A and the second external electrode 40B have shapes that are approximately plane-symmetric with respect to a WT cross section at the center of the longitudinal direction L of the multilayer ceramic capacitor 1. Therefore, in the following, when it is not necessary to distinguish between the first external electrode 40A and the second external electrode 40B, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the external electrodes 40.

[0034] The first external electrode 40A is disposed on the first end face LS1. The first external electrode 40A is in contact with the first lead portions 31B of each of the first internal electrode layers 31 exposed at the first end face LS1. This electrically connects the first external electrode 40A to the first internal electrode layers 31. The first external electrode 40A may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the first external electrode 40A is formed to extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0035] The second external electrode 40B is disposed on the second end face LS2. The second external electrode 40B is in contact with the second lead portions 32B of the second internal electrode layers 32 exposed at the second end face LS2. This electrically connects the second external electrode 40B to the second internal electrode layers 32. The second external electrode 40B may also be disposed on parts of the first main surface TS1 and the second main surface TS2, as well as parts of the first side surface WS1 and the second side surface WS2. In this embodiment, the second external electrode 40B is formed to extend from the second end face LS2 to parts of the first main surface TS1 and the second main surface TS2, as well as parts of the first side surface WS1 and the second side surface WS2.

[0036] As described above, in the laminate 10, the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 face each other via the dielectric layer 20, thereby forming capacitance. Therefore, the characteristics of a capacitor are exhibited between the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32.

[0037] 2, 4A, and 4B, the first external electrode 40A has a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A. The second external electrode 40B has a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B.

[0038] The first base electrode layer 50A is disposed on the first end face LS1. The first base electrode layer 50A is connected to the first lead portions 31B of each of the first internal electrode layers 31 exposed at the first end face LS1. In this embodiment, the first base electrode layer 50A is formed to extend from the first end face LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0039] The second base electrode layer 50B is disposed on the second end face LS2. The second base electrode layer 50B is in contact with the second lead portions 32B of each of the second internal electrode layers 32 exposed at the second end face LS2. In this embodiment, the second base electrode layer 50B is formed to extend from the second end face LS2 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0040] The first and second base electrode layers 50A and 50B of the present embodiment are baked layers. The baked layers preferably contain a metal component and either a glass component or a ceramic component, or both. The metal component includes at least one selected from, for example, Cu, Ni, Ag, Pd, an Ag-Pd alloy, and Au. The glass component includes at least one selected from, for example, B, Si, Ba, Mg, Al, and Li. The ceramic component may be the same ceramic material as that of the dielectric layer 20, or a different ceramic material. The ceramic component may include at least one selected from, for example, BaTiO3, CaTiO3, (Ba, Ca)TiO3, SrTiO3, and CaZrO3.

[0041] The baked layer is formed by, for example, applying a conductive paste containing glass and metal to the laminate 10 and baking it. The baked layer can be formed by simultaneously baking a pre-fired laminate chip, which is the material for the laminate 10 having multiple internal electrodes and dielectric layers, and a conductive paste applied to the laminate chip. Alternatively, the baked layer can be formed by first firing the laminate chip to obtain the laminate 10, and then applying a conductive paste to the laminate 10 and baking it. In the above configuration, the baked layer is preferably formed by baking a material to which a ceramic material is added instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. The baked layer may be multiple layers.

[0042] The thickness of the first base electrode layer 50A located on the first end face LS1 in the longitudinal direction L is preferably, for example, approximately 2 μm or more and 220 μm or less at the center of the first base electrode layer 50A in the stacking direction T and width direction W.

[0043] The thickness of the second base electrode layer 50B located on the second end face LS2 in the longitudinal direction L is preferably, for example, approximately 2 μm or more and 220 μm or less at the center of the second base electrode layer 50B in the stacking direction T and width direction W.

[0044] When the first base electrode layer 50A is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness of the first base electrode layer 50A provided on this portion, corresponding to the stacking direction T, is preferably, for example, approximately 3 μm or more and 40 μm or less, at the center of the first base electrode layer 50A provided on this portion in the length direction L and width direction W.

[0045] When the first base electrode layer 50A is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, the thickness of the first base electrode layer 50A provided on this portion in the width direction W is preferably, for example, approximately 3 μm or more and 40 μm or less at the center of the first base electrode layer 50A provided on this portion in the length direction L and stacking direction T.

[0046] When the second base electrode layer 50B is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness of the second base electrode layer 50B provided on this portion in the stacking direction T is preferably, for example, approximately 3 μm or more and 40 μm or less at the center of the second base electrode layer 50B provided on this portion in the length direction L and width direction W.

[0047] When the second base electrode layer 50B is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, the thickness of the second base electrode layer 50B provided on this portion in the width direction W is preferably, for example, approximately 3 μm or more and 40 μm or less at the center of the second base electrode layer 50B provided on this portion in the length direction L and stacking direction T.

[0048] The first plating layer 60A is disposed so as to cover the first base electrode layer 50A.

[0049] The second plating layer 60B is disposed so as to cover the second base electrode layer 50B.

[0050] The first plating layer 60A and the second plating layer 60B may contain at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag-Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may each be formed of multiple layers. The first plating layer 60A and the second plating layer 60B preferably have a two-layer structure in which a Sn plating layer is formed on a Ni plating layer.

[0051] The first plating layer 60A is disposed so as to cover the first base electrode layer 50A. In this embodiment, the first plating layer 60A includes a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0052] The second plating layer 60B is disposed so as to cover the second base electrode layer 50B. In the embodiment, the second plating layer 60B has a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0053] The Ni plating layer prevents the first base electrode layer 50A and the second base electrode layer 50B from being eroded by solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1, thereby facilitating mounting of the multilayer ceramic capacitor 1. The thickness of each of the first Ni plating layer 61A, the first Sn plating layer 62A, the second Ni plating layer 61B, and the second Sn plating layer 62B is preferably 1 μm or more and 15 μm or less.

[0054] The above is the basic configuration of the multilayer ceramic capacitor 1 according to the embodiment. If the lengthwise dimension of the multilayer ceramic capacitor 1 including the laminate 10 and the external electrodes 40 is defined as L, then the L dimension is preferably 0.2 mm or more and 10 mm or less. If the lengthwise dimension of the multilayer ceramic capacitor 1 is defined as T, then the T dimension is preferably 0.05 mm or more and 10 mm or less. If the widthwise dimension of the multilayer ceramic capacitor 1 is defined as W, then the W dimension is preferably 0.1 mm or more and 10 mm or less.

[0055] The multilayer ceramic capacitor 1 of this embodiment having the above basic configuration has the following features in the external electrodes 40, that is, the first external electrode 40A and the second external electrode 40B.

[0056] The external electrode 40 of the embodiment includes a main surface-side external electrode arranged on at least one of the first main surface TS1 and the second main surface TS2. In detail, as described above, the first external electrode 40A of the embodiment is arranged on the first end face LS1 and extends from the first end face LS1 to part of the first main surface TS1 and part of the second main surface TS2, as well as part of the first side surface WS1 and part of the second side surface WS2. That is, the first external electrode 40A of the embodiment includes, as shown in FIG. 2, a first end face side external electrode 400A as an end face side external electrode arranged on the first end face LS1, a first main face side external electrode 411A as a main face side external electrode arranged on the first main face TS1, and a second main face side external electrode 412A as a main face side external electrode arranged on the second main face TS2, and, as shown in FIGS. 4A and 4B, a first side face side external electrode 421A arranged on the first side face WS1 and a second side face side external electrode 422A arranged on the second side face WS2.

[0057] As described above, the first external electrode 40A has a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A. In the embodiment, the first base electrode layer 50A is formed to extend from the first end face LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2, and the first plating layer 60A is disposed so as to cover the first base electrode layer 50A.

[0058] 2, the first end face side external electrode 400A of the embodiment has a first end face side base electrode layer 500A arranged on the first end face LS1 and a first end face side plating layer 600A formed above the first end face side base electrode layer 500A. The first end face side base electrode layer 500A is part of the first base electrode layer 50A. The first end face side plating layer 600A is part of the first plating layer 60A and has a first Ni plating layer 61A and a first Sn plating layer 62A on the first Ni plating layer 61A.

[0059] 2, the first main surface-side external electrode 411A of the embodiment has a first main surface-side base electrode layer 511A as a main surface-side base electrode layer arranged on the first main surface TS1, and a first main surface-side plating layer 611A as a main surface-side plating layer formed above the first main surface-side base electrode layer 511A. The first main surface-side base electrode layer 511A is part of the first base electrode layer 50A. The first main surface-side plating layer 611A is part of the first plating layer 60A and has a first Ni plating layer 61A and a first Sn plating layer 62A on the first Ni plating layer 61A.

[0060] 2, the second main surface-side external electrode 412A of the embodiment has a second main surface-side base electrode layer 512A as a main surface-side base electrode layer arranged on the second main surface TS2, and a second main surface-side plating layer 612A as a main surface-side plating layer formed above the second main surface-side base electrode layer 512A. The second main surface-side base electrode layer 512A is part of the first base electrode layer 50A. The second main surface-side plating layer 612A is part of the first plating layer 60A and has a first Ni plating layer 61A and a first Sn plating layer 62A on the first Ni plating layer 61A.

[0061] 4A and 4B, the first side surface side external electrode 421A of the embodiment has a first side surface side base electrode layer 521A arranged on the first side surface WS1 and a first side surface side plating layer 621A formed above the first side surface side base electrode layer 521A. The first side surface side base electrode layer 521A is part of the first base electrode layer 50A. The first side surface side plating layer 621A is part of the first plating layer 60A and has a first Ni plating layer 61A and a first Sn plating layer 62A on the first Ni plating layer 61A.

[0062] 4A and 4B, the second side surface side external electrode 422A of the embodiment has a second side surface side base electrode layer 522A arranged on the second side surface WS2 and a second side surface side plating layer 622A formed above the second side surface side base electrode layer 522A. The second side surface side base electrode layer 522A is part of the first base electrode layer 50A. The second side surface side plating layer 622A is part of the first plating layer 60A and has a first Ni plating layer 61A and a first Sn plating layer 62A on the first Ni plating layer 61A.

[0063] The thickness of each of the first Ni plating layer 61A and the first Sn plating layer 62A of the above-mentioned first main surface side plating layer 611A, second main surface side plating layer 612A, first side surface side plating layer 621A and second side surface side plating layer 622A is preferably, for example, 1 μm or more and 4 μm or less.

[0064] As described above, the second external electrode 40B of the embodiment is disposed on the second end face LS2 and is formed to extend from the second end face LS2 to part of the first main face TS1 and part of the second main face TS2, and part of the first side face WS1 and part of the second side face WS2. That is, the second external electrode 40B of the embodiment includes, as shown in Fig. 2, a second end face-side external electrode 400B as an end face-side external electrode disposed on the first end face LS1, a first main face-side external electrode 411B as a main face-side external electrode disposed on the first main face TS1, and a second main face-side external electrode 412B as a main face-side external electrode disposed on the second main face TS2, and, as shown in Figs. 4A and 4B, a first side face-side external electrode 421B arranged on the first side face WS1 and a second side face-side external electrode 422B arranged on the second side face WS2.

[0065] As described above, the second external electrode 40B has a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B. In the embodiment, the second base electrode layer 50B is formed to extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2, and the second plating layer 60B is disposed so as to cover the second base electrode layer 50B.

[0066] 2, the second end face side external electrode 400B of the embodiment has a second end face side base electrode layer 500B arranged on the second end face LS2 and a second end face side plating layer 600B formed above the second end face side base electrode layer 500B. The second end face side base electrode layer 500B is part of the second base electrode layer 50B. The second end face side plating layer 600B is part of the second plating layer 60B and has a second Ni plating layer 61B and a second Sn plating layer 62B on the second Ni plating layer 61B.

[0067] 2, the first main surface-side external electrode 411B of the embodiment has a first main surface-side base electrode layer 511B as a main surface-side base electrode layer arranged on the first main surface TS1, and a first main surface-side plating layer 611B as a main surface-side plating layer formed above the first main surface-side base electrode layer 511B. The first main surface-side base electrode layer 511B is part of the second base electrode layer 50B. The first main surface-side plating layer 611B is part of the second plating layer 60B and has a second Ni plating layer 61B and a second Sn plating layer 62B on the second Ni plating layer 61B.

[0068] 2, the second main surface-side external electrode 412B of the embodiment has a second main surface-side base electrode layer 512B as a main surface-side base electrode layer arranged on the second main surface TS2, and a second main surface-side plating layer 612B as a main surface-side plating layer formed above the second main surface-side base electrode layer 512B. The second main surface-side base electrode layer 512B is part of the second base electrode layer 50B. The second main surface-side plating layer 612B is part of the second plating layer 60B and has a second Ni plating layer 61B and a second Sn plating layer 62B on the second Ni plating layer 61B.

[0069] 4A and 4B, the first side surface side external electrode 421B of the embodiment has a first side surface side base electrode layer 521B arranged on the first side surface WS1 and a first side surface side plating layer 621B formed above the first side surface side base electrode layer 521B. The first side surface side base electrode layer 521B is part of the second base electrode layer 50B. The first side surface side plating layer 621B is part of the second plating layer 60B and has a second Ni plating layer 61B and a second Sn plating layer 62B on the second Ni plating layer 61B.

[0070] 4A and 4B, the second side surface side external electrode 422B of the embodiment has a second side surface side base electrode layer 522B arranged on the second side surface WS2 and a second side surface side plating layer 622B formed above the second side surface side base electrode layer 522B. The second side surface side base electrode layer 522B is part of the second base electrode layer 50B. The second side surface side plating layer 622B is part of the second plating layer 60B and has a second Ni plating layer 61B and a second Sn plating layer 62B on the second Ni plating layer 61B.

[0071] The thickness of the second Ni plating layer 61B and the thickness of the second Sn plating layer 62B of the above-mentioned first main surface side plating layer 611B, second main surface side plating layer 612B, first side surface side plating layer 621B and second side surface side plating layer 622B are preferably, for example, 1 μm or more and 4 μm or less.

[0072] FIG. 2 shows an LT cross section of the multilayer ceramic capacitor 1 and the laminate 10 taken along the lamination direction T and the longitudinal direction L. In this LT cross section, the first main surface side external electrode 411A of the first external electrode 40A has a first main surface side recess 510A as a recess recessed toward the laminate 10. The first main surface side recess 510A is formed on the surface of the first main surface side external electrode 411A. The first main surface side recess 510A has a groove shape extending in the width direction W perpendicular to the LT cross section, i.e., in the direction perpendicular to the paper surface of FIG. 2. The first main surface side recess 510A may be formed over the entire length of the first main surface side external electrode 411A along the width direction W. The first main surface side recess 510A is located approximately in the center of the first main surface side external electrode 411A in the longitudinal direction L.

[0073] 2, the second main surface side external electrode 412A of the first external electrode 40A has a second main surface side recess 520A as a recess recessed toward the laminate 10 in the LT cross section. The second main surface side recess 520A is formed on the surface of the second main surface side external electrode 412A. The second main surface side recess 520A has a groove shape extending in the width direction W perpendicular to the LT cross section, i.e., the front-to-back direction of the paper surface of FIG. 2. The second main surface side recess 520A may be formed over the entire length of the second main surface side external electrode 412A along the width direction W. The second main surface side recess 520A is located approximately near the center of the second main surface side external electrode 412A in the length direction L.

[0074] 2, the first main surface side external electrode 411B of the second external electrode 40B has a first main surface side recess 510B as a recess recessed toward the laminate 10 in the LT cross section. The first main surface side recess 510B is formed on the surface of the first main surface side external electrode 411B. The first main surface side recess 510B has a groove shape extending in the width direction W perpendicular to the LT cross section, i.e., the front-to-back direction of the paper surface of FIG. 2. The first main surface side recess 510B may be formed over the entire length of the first main surface side external electrode 411B along the width direction W. The first main surface side recess 510B is located approximately in the vicinity of the center of the first main surface side external electrode 411B in the length direction L.

[0075] 2, the second main surface side external electrode 412B of the second external electrode 40B has a second main surface side recess 520B as a recess recessed toward the laminate 10 in the LT cross section. The second main surface side recess 520B is formed on the surface of the second main surface side external electrode 412B. The second main surface side recess 520B has a groove shape extending in the width direction W perpendicular to the LT cross section, i.e., the front-to-back direction of the paper surface of FIG. 2. The second main surface side recess 520B may be formed over the entire length of the second main surface side external electrode 412B along the width direction W. The second main surface side recess 520B is located approximately in the vicinity of the center of the second main surface side external electrode 412B in the length direction L.

[0076] 4A and 4B show LW cross sections of the multilayer ceramic capacitor 1 and the laminate 10 taken along the length direction L and width direction W. In this LW cross section, the first side surface side external electrode 421A of the first external electrode 40A has a first side surface side recess 530A as a recess recessed toward the laminate 10. The first side surface side recess 530A is formed on the surface of the first side surface side external electrode 421A. The first side surface side recess 530A has a groove shape extending in the stacking direction T perpendicular to the LW cross section, i.e., in the direction from the front to the back of the paper of FIGS. 4A and 4B. The first side surface side recess 530A may be formed over the entire length of the first side surface side external electrode 421A along the stacking direction T. The first side surface side recess 530A is located approximately in the center of the first side surface side external electrode 421A in the length direction L. The first side surface recess 530A may communicate with either or both of the above-mentioned first main surface recess 510A and second main surface recess 520A, or may not communicate with both.

[0077] As shown in FIGS. 4A and 4B, the second side surface side external electrode 422A of the first external electrode 40A has a second side surface side recess 540A as a recess recessed toward the laminate 10 in an LW cross section. The second side surface side recess 540A is formed on the surface of the second side surface side external electrode 422A. The second side surface side recess 540A has a groove shape extending in the stacking direction T perpendicular to the LW cross section, i.e., the front-to-back direction of the paper in FIGS. 4A and 4B. The second side surface side recess 540A may be formed over the entire length of the second side surface side external electrode 422A along the stacking direction T. The second side surface side recess 540A is disposed approximately near the center of the second side surface side external electrode 422A in the length direction L. The second side surface recess 540A may communicate with either or both of the first main surface recess 510A and the second main surface recess 520A, or may not communicate with both.

[0078] As shown in FIGS. 4A and 4B, the first side surface side external electrode 421B of the second external electrode 40B has a first side surface side recess 530B as a recess recessed toward the laminate 10 in an LW cross section. The first side surface side recess 530B is formed on the surface of the first side surface side external electrode 421B. The first side surface side recess 530B has a groove shape extending in the stacking direction T perpendicular to the LW cross section, i.e., in the direction from the front to the back of the paper in FIGS. 4A and 4B. The first side surface side recess 530B may be formed over the entire length of the first side surface side external electrode 421B along the stacking direction T. The first side surface side recess 530B is disposed approximately in the vicinity of the center of the first side surface side external electrode 421B in the length direction L. The first side surface recess 530B may communicate with either or both of the above-described first main surface recess 510B and second main surface recess 520B, or may not communicate with both.

[0079] As shown in FIGS. 4A and 4B, the second side surface side external electrode 422B of the second external electrode 40B has a second side surface side recess 540B as a recess recessed toward the laminate 10 in an LW cross section. The second side surface side recess 540B is formed on the surface of the second side surface side external electrode 422B. The second side surface side recess 540B has a groove shape extending in the stacking direction T perpendicular to the LW cross section, i.e., in the direction from the front to the back of the paper in FIGS. 4A and 4B. The second side surface side recess 540B may be formed over the entire length of the second side surface side external electrode 422B along the stacking direction T. The second side surface side recess 540B is located approximately near the center of the second side surface side external electrode 422B in the length direction L. The second side surface recess 540B may communicate with either or both of the first main surface recess 510B and the second main surface recess 520B, or may not communicate with both.

[0080] The first main surface side external electrode 411A and the second main surface side external electrode 412A of the first external electrode 40A and the first main surface side external electrode 411B and the second main surface side external electrode 412B of the second external electrode 40B have the same configuration. Furthermore, the first side surface side external electrode 421A and the second side surface side external electrode 422A of the first external electrode 40A and the first side surface side external electrode 421B and the second side surface side external electrode 422B of the second external electrode 40B also have the same configuration as the four main surface side external electrodes 411A, 412A, 411B, 412B.

[0081] The first and second main surface recesses 510A, 520A of the first external electrode 40A and the first and second main surface recesses 510B, 520B of the second external electrode 40B have the same configuration. Furthermore, the first and second side surface recesses 530A, 540A of the first external electrode 40A and the first and second side surface recesses 530B, 540B of the second external electrode 40B also have the same configuration as the four main surface recesses 510A, 520A, 510B, 520B.

[0082] Therefore, the first main surface side external electrode 411A and the first main surface side recess 510A of the first external electrode 40A will be described below as representative of these four main surface side external electrodes and main surface side recesses, and these four side surface side external electrodes and side surface side recesses, thereby explaining the four main surface side external electrodes and main surface side recesses, and the four side surface side external electrodes and side surface side recesses.

[0083] The first main surface side external electrode 411A of the first external electrode 40A corresponds to the second main surface side external electrode 412A, the first side surface side external electrode 421A, and the second side surface side external electrode 422A of the first external electrode 40A, and the first main surface side external electrode 411B, the second main surface side external electrode 412B, the first side surface side external electrode 421B, and the second side surface side external electrode 422B of the second external electrode 40B. The first main surface side recess 510A of the first external electrode 40A corresponds to the second main surface side recess 520A, the first side surface side recess 530A, and the second side surface side recess 540A of the first external electrode 40A, and the first main surface side recess 510B, the second main surface side recess 520B, the first side surface side recess 530B, and the second side surface side recess 540B of the second external electrode 40B.

[0084] The first base electrode layer 50A and the first plating layer 60A of the first external electrode 40A correspond to the second base electrode layer 50B and the second plating layer 60B of the second external electrode 40B. The first Ni plating layer 61A and the first Sn plating layer 62A of the first plating layer 60A of the first external electrode 40A correspond to the second Ni plating layer 61B and the second Sn plating layer 62B of the second plating layer 60B of the second external electrode 40B.

[0085] Fig. 5A is an enlarged view of the portion indicated by VA in Fig. 2, and is an LT cross-sectional view showing the first main surface side external electrode 411A of the first external electrode 40A. Fig. 5B is a view corresponding to Fig. 5A, and shows the outline of the LT cross-section of the first main surface side external electrode 411A of the first external electrode 40A. Note that Figs. 5A and 5B show the same XYZ Cartesian coordinate system as Figs. 1 to 4B.

[0086] 5A, the first main surface side external electrode 411A of the first external electrode 40A has a first main surface side base electrode layer 511A disposed on the first main surface TS1, and a first main surface side plating layer 611A including a first Ni plating layer 61A and a first Sn plating layer 62A. The first main surface side recess 510A is formed by recessing three layers, namely, the first Sn plating layer 62A of the outermost first main surface side plating layer 611A, the first Ni plating layer 61A below the first Sn plating layer 62A, and the first main surface side base electrode layer 511A below the first Ni plating layer 61A, toward the laminate 10 in the stacking direction T (corresponding to the Z direction in FIGS. 5A and 5B ).

[0087] Therefore, the thickness of the first principal surface side base electrode layer 511A in the stacking direction T is smallest at the portion corresponding to the first principal surface side recess 510A. In the embodiment, the maximum thickness of the first principal surface side base electrode layer 511A is preferably, for example, 15 μm or more and 30 μm or less.

[0088] The first main surface side base electrode layer 511A of the first main surface side external electrode 411A in the first external electrode 40A has a recess-corresponding region 550 corresponding to the first main surface side recess 510A, and an inner peripheral region 560 and an outer peripheral region 570 as peripheral regions adjacent to this recess-corresponding region 550 in the length direction L (corresponding to the X direction in Figures 5A and 5B).

[0089] The recess-corresponding region 550 is a region that corresponds in the stacking direction T to the first principal surface side recess 510A in the first principal surface side base electrode layer 511A.

[0090] The inner peripheral region 560 is a region within the first main surface side base electrode layer 511A that is further inward in the longitudinal direction L than the recess corresponding region 550, i.e., toward the center of the longitudinal direction L of the laminate 10 (the side away from the first end face LS1 in the longitudinal direction L), and is a region that extends from the recess corresponding region 550 in a range approximately equal to the length in the longitudinal direction L of the recess corresponding region 550.

[0091] The outer peripheral region 570 is a region within the first main surface side base electrode layer 511A that is further outward in the longitudinal direction L than the recess corresponding region 550, i.e., outside the longitudinal direction L of the laminate 10 (the side closer to the first end face LS1 in the longitudinal direction L), and is a region that extends from the recess corresponding region 550 in a range approximately equal to the length in the longitudinal direction L of the recess corresponding region 550.

[0092] As shown in FIG. 5B, the surface of the first main surface side external electrode 411A has the above-mentioned first main surface side recess 510A, as well as a first raised portion 710 on the inside of the first main surface side recess 510A, and a second raised portion 720 on the outside of the first main surface side recess 510A.

[0093] 5B indicates a region in the length direction L of the first main surface recess 510A (recess-corresponding region 550) in the embodiment. The region 700 in the length direction L of the first main surface recess 510A is based on the distance in the length direction L between a first midpoint 510m1 of a line connecting the deepest portion 510d of the first main surface recess 510A to the apex 710p of the first raised portion 710, and a second midpoint 510m2 of a line connecting the deepest portion 510d of the first main surface recess 510A to the apex 720p of the second raised portion 720. The deepest portion 510d of the first main surface recess 510A refers to a portion of the first main surface recess 510A that is closest to the first main surface TS1 of the laminate 10 in the stacking direction T. The apex 710p of the first raised portion 710 is the point on the surface of the first raised portion 710 that is farthest from the first main surface TS1 of the laminate 10 in the stacking direction T. The apex 720p of the second raised portion 720 is the point on the surface of the second raised portion 720 that is farthest from the first main surface TS1 of the laminate 10 in the stacking direction T.

[0094] The distance in the stacking direction T between the apex 710p of the first raised portion 710 and the first main surface TS1 of the laminate 10 is the height 710H of the first raised portion 710. The distance in the stacking direction T between the apex 720p of the second raised portion 720 and the first main surface TS1 of the laminate 10 is the height 720H ​​of the second raised portion 720. In the embodiment, the height 710H of the first raised portion 710 and the height 720H ​​of the second raised portion 720 may be the same or different. If they are different, the height 710H of the first raised portion 710 may be higher than the height 720H ​​of the second raised portion 720, or conversely, may be lower than the height 720H ​​of the second raised portion 720.

[0095] As shown in FIG. 5B, in the embodiment, the depth D of the first main surface recess 510A refers to the shortest distance between the deepest part 510d and the line connecting the vertex 710p of the first raised portion 710 and the vertex 720p of the second raised portion 720.

[0096] In this embodiment, the depth D of the first main surface recess 510A is preferably 3 μm or more and 10 μm or less.

[0097] In this embodiment, the depth D of the first main surface recess 510A is preferably greater than the thickness of the Ni plating layer 61A in the stacking direction T.

[0098] 5B, in this embodiment, a distance 730L in the length direction L between the apex 710p of the first raised portion 710 and the apex 720p of the second raised portion 720 is preferably 50 μm or more and 400 μm or less. Furthermore, this distance 730L is preferably greater than the maximum thickness of the first principal surface side base electrode layer 511A.

[0099] As shown in FIG. 5B, in the embodiment, it is preferable that the distance 740L in the longitudinal direction L between the inner end 560a of the first principal surface side base electrode layer 511A and the deepest part 510d of the first principal surface side recess 510A is not less than 50 μm and not more than 400 μm.

[0100] As shown in FIG. 5B, in the embodiment, the distance 750L in the length direction L between the inner end 560a of the first principal surface side base electrode layer 511A and the vertex 710p of the first raised portion 710 is preferably 50 μm or more and 200 μm or less.

[0101] The inner peripheral region 560 described above is a region corresponding to the first protruding portion 710 in the first principal surface side base electrode layer 511A. The outer peripheral region 570 described above is a region corresponding to the second protruding portion 720 in the first principal surface side base electrode layer 511A.

[0102] 5A, the first principal surface side base electrode layer 511A has a metal portion 800 and a plurality of non-metal portions 810 present in the metal portion 800. The metal portion 800 contains at least one metal component selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, etc., contained in the baked layer that forms the first principal surface side base electrode layer 511A. A plurality of non-metal portions 810 are dispersed within the metal portion 800.

[0103] The non-metallic portion 810 is primarily a void, but it need not be entirely void and may be composed of a glass component containing Ba or Si. The non-metallic portion 810 has the function of alleviating stress caused by force applied to the external electrode. In the following description, the non-metallic portion 810 containing a glass component will be referred to as the void 810.

[0104] In the first principal surface side base electrode layer 511A of the embodiment, the metal density in the recess corresponding region 550 is lower than the metal density in the inner peripheral region 560 corresponding to the first raised portion 710, and is also lower than the metal density in the outer peripheral region 570 corresponding to the second raised portion 720. The metal density here corresponds to the area ratio occupied by the metal portion 800 in the first principal surface side base electrode layer 511A in the LT cross section.

[0105] Furthermore, in the first main surface side base electrode layer 511A of the embodiment, it is preferable to adopt the following condition: the metal density of the recess corresponding region 550 is at least 10% lower than the metal density of the inner peripheral region 560 corresponding to the first raised portion 710, and is 10% lower than the metal density of the outer peripheral region 570 corresponding to the second raised portion 720.

[0106] With the above conditions satisfied, for example, the metal density of the recess corresponding region 550 is preferably 85% or less, and more preferably 60% or more and 85% or less.

[0107] Furthermore, while satisfying the above conditions, for example, the metal density of the inner peripheral region 560 corresponding to the first raised portion 710 and the metal density of the outer peripheral region 570 corresponding to the second raised portion 720 are preferably greater than 85%, and more preferably 90% or more and 95% or less.

[0108] In the LT cross section of the first principal surface side base electrode layer 511A, the average area of ​​the multiple voids 810 present in the recess corresponding region 550 is preferably larger than the average area of ​​the voids 810 in the inner peripheral region 560 and the voids 810 in the outer peripheral region 570.

[0109] In the multilayer ceramic capacitor 1 of the embodiment, the first main surface side external electrode 411A of the first external electrode 40A has a first main surface side recess 510A. The first main surface side base electrode layer 511A of the first main surface side external electrode 411A, which is in direct contact with the laminate 10, has a recess-corresponding region 550 corresponding to the first main surface side recess 510A, an inner peripheral region 560 which is a region inside the recess-corresponding region 550 in the length direction L, and an outer peripheral region 570 which is a region outside the recess-corresponding region 550 in the length direction L, and the metal density of the recess-corresponding region 550 is lower than the metal density of the inner peripheral region 560 and the metal density of the outer peripheral region 570.

[0110] The metal density of the recess-corresponding region 550, which constitutes the center of the first principal surface side base electrode layer 511A in the length direction L, is lower than the metal density of the inner peripheral region 560 and the outer peripheral region 570 on both sides of the recess-corresponding region 550 in the length direction L. This causes the recess-corresponding region 550 to contain a large amount of non-metallic portions 810. Therefore, the recess-corresponding region 550 relieves stress caused by force applied to the external electrode. Furthermore, the metal density of the recess-corresponding region 550, which constitutes the center of the first principal surface side base electrode layer 511A in the length direction L, is lower than the metal density of the inner peripheral region 560 and the outer peripheral region 570 on both sides of the recess-corresponding region 550 in the length direction L. This means that the recess-corresponding region 550 tends to have lower adhesion to the laminate 10 than the inner peripheral region 560 and the outer peripheral region 570. For example, when mounting the external electrodes of the multilayer ceramic capacitor 1 on a substrate (assuming here that the first main surface side external electrode 411A is attached to the substrate by soldering or other means), flexural stress generated in the first main surface side external electrode 411A may concentrate, particularly at the inner end 411e of the first main surface side external electrode 411A or the inner end 560a of the first main surface side base electrode layer 511A shown in FIG. 5B , and be transmitted as tensile stress to the laminate 10, possibly causing cracks or the like in the laminate 10. However, if the adhesion of the recess-corresponding region 550 of the first main surface side base electrode layer 511A to the laminate 10 is relatively low, as in the embodiment, the tensile stress based on the flexural stress that tends to concentrate on the inner end 411e or the end 560a is also dispersed to the interface between the recess-corresponding region 550, which has relatively low adhesion, and the laminate 10. This enables the multilayer ceramic capacitor 1 of the embodiment to have improved flexural resistance. As a result, the occurrence of cracks and the like in the laminate 10 is suppressed.

[0111] Furthermore, in the multilayer ceramic capacitor 1 of the embodiment, the first main surface side external electrode 411A of the first external electrode 40A has the first main surface side recess 510A, and therefore a depression corresponding to the first main surface side recess 510A is also formed in the first main surface side base electrode layer 511A. As a result, the total volume of the first main surface side base electrode layer 511A can be reduced compared to when the first main surface side recess 510A is not present. This reduction in the total volume leads to a reduction in the tensile stress due to the flexural stress concentrated at the inner end 411e and the end 560a described above, which also improves flexural resistance and, as a result, suppresses the occurrence of cracks and the like in the laminate 10.

[0112] Next, we will explain how to measure various parameters, such as the depth D of the first main surface recess 510A, the average area of ​​the voids 810 in the first main surface side base electrode layer 511A, and the metal density of the first main surface side base electrode layer 511A, in the LT cross section of the multilayer ceramic capacitor 1. In the following description, the non-metallic portion 810 containing a glass component will also be referred to as the void 810.

[0113] First, the multilayer ceramic capacitor 1 is polished from the first side surface WS1 or the second side surface WS2 to a position approximately halfway along the width direction W. This exposes the LT cross section at the center of the multilayer ceramic capacitor 1 in the width direction W. Next, a digital microscope is used to measure the depth D of the first main surface recess 510A in the LT cross section exposed by polishing. This allows the depth D of the first main surface recess 510A to be confirmed.

[0114] Next, the LT cross section exposed by polishing is observed using an SEM. Specifically, a portion of the LT cross section including the first principal surface side base electrode layer 511A is captured as a backscattered electron image. In the backscattered electron image, the difference in resistance value is reflected as contrast, with the metal portion 800 appearing relatively white and the voids 810 (non-metal portion 810) appearing darker than the metal portion 800. The imaging magnification is set to 2000, and the recess-corresponding region 550, the inner peripheral region 560, and the outer peripheral region 570 within the first principal surface side base electrode layer 511A in the backscattered electron image are analyzed.

[0115] The acquired backscattered electron image is binarized using image analysis software "WinROOF (manufactured by Mitani Corporation)" to identify the metal portion 800 and the plurality of voids 810 present within the metal portion 800. Using this binarized image, the average area of ​​the plurality of voids 810 and the metal density are calculated for each of the recess-corresponding region 550, the inner peripheral region 560, and the outer peripheral region 570 within the first principal surface side base electrode layer 511A, which are the ranges to be analyzed.

[0116] The area of ​​the voids 810 is calculated based on a binarized image obtained by binarizing the backscattered electron image. Based on the area of ​​each void 810 identified in each of the recess-corresponding region 550, the inner peripheral region 560, and the outer peripheral region 570, the average area of ​​the multiple voids 810 in each region is calculated.

[0117] Based on the areas of the recess corresponding region 550, the inner peripheral region 560 and the outer peripheral region 570 and the area of ​​the voids 810 in these regions (analysis range), the area ratio of the voids 810 in these regions is calculated using the following formula (1). Void area percentage (%) = (Void area / Area of ​​analysis range) × 100…(1)

[0118] From the area ratio of the voids 810 thus determined, the area ratio of the metal portion 800 in each of the recess corresponding region 550, the inner peripheral region 560, and the outer peripheral region 570, that is, the metal density, is calculated using the following formula (2). 100(%) - void area ratio (%) = metal density (%)...(2)

[0119] The area ratio of the metal portion 800 in each of the recess-corresponding region 550, the inner peripheral region 560, and the outer peripheral region 570, that is, the metal density, can also be calculated from the following formula (3). Metal density (%) = (area of ​​metal part / area of ​​analysis range) × 100...(3)

[0120] Next, a method for manufacturing the multilayer ceramic capacitor 1 of the embodiment will be described. The method for manufacturing the multilayer ceramic capacitor 1 of the embodiment is not limited as long as it satisfies the above-mentioned requirements. However, a suitable manufacturing method includes the following steps. Each step will be described in detail below.

[0121] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. Both the dielectric sheet for the dielectric layer 20 and the conductive paste for the internal electrode layer 30 contain a binder and a solvent. The binder and solvent may be known. The conductive paste is, for example, a metal powder to which an organic binder and an organic solvent are added.

[0122] On the dielectric sheets, a conductive paste for the internal electrode layers 30 is printed in a predetermined pattern by, for example, screen printing, gravure printing, etc. In this way, a dielectric sheet on which the pattern of the first internal electrode layer 31 is formed and a dielectric sheet on which the pattern of the second internal electrode layer 32 is formed are prepared.

[0123] A predetermined number of dielectric sheets on which the pattern of the internal electrode layer 30 is not printed are stacked to form a portion that will become the first main surface side outer layer portion 12 on the first main surface TS1 side. Dielectric sheets on which the pattern of the first internal electrode layer 31 is printed and dielectric sheets on which the pattern of the second internal electrode layer 32 is printed are stacked alternately on top of that. This forms a portion that will become the internal layer portion 11. A predetermined number of dielectric sheets on which the pattern of the internal electrode layer 30 is not printed are stacked on top of this portion that will become the internal layer portion 11 to form a portion that will become the second main surface side outer layer portion 13 on the second main surface TS2 side. In this way, a laminated sheet is produced.

[0124] The laminated sheets are pressed in the lamination direction by means of an isostatic press or the like to produce a laminated block.

[0125] The laminated block is cut into pieces of a predetermined size to obtain a plurality of laminated chips, which may then be polished by barrel polishing or the like to round off corners and ridges.

[0126] The laminated chip is fired to produce the laminate 10. The firing temperature at this time depends on the materials of the dielectric layers 20 and the internal electrode layers 30, but is preferably, for example, 900°C or higher and 1400°C or lower.

[0127] A first external electrode 40A and a second external electrode 40B are formed on each of the two end surfaces of the laminate 10 as follows.

[0128] A conductive paste that will become the first base electrode layer 50A is applied to the first end face LS1 side of the laminate 10. A conductive paste that will become the second base electrode layer 50B is applied to the second end face LS2 side of the laminate 10. In this embodiment, the first base electrode layer 50A and the second base electrode layer 50B are baked layers. The baked layers are formed by applying a conductive paste containing a glass component and a metal to the laminate 10 by a method such as dipping, followed by a baking process. The temperature for the baking process at this time is preferably 700°C or higher and 950°C or lower, for example.

[0129] The first and second base electrode layers 50A and 50B are preferably baked layers, which allows the first and second base electrode layers 50A and 50B to be formed by a relatively simple method compared to thin film formation methods such as sputtering and vapor deposition.

[0130] In the embodiment, dipping is performed so that the conductive paste that will become the first main surface side base electrode layer 511A of the first base electrode layer 50A is arranged extending from the first end face LS1 of the laminate 10 to a portion of the first main surface TS1, and so that the conductive paste that will become the second main surface side base electrode layer 512A of the first base electrode layer 50A is arranged extending from the first end face LS1 of the laminate 10 to a portion of the second main surface TS2.

[0131] Furthermore, in the embodiment, dipping is performed so that the conductive paste that will become the first main surface side base electrode layer 511B of the second base electrode layer 50B is arranged extending from the second end face LS2 of the laminate 10 to a portion of the first main surface TS1, and so that the conductive paste that will become the second main surface side base electrode layer 512B of the second base electrode layer 50B is arranged extending from the second end face LS2 of the laminate 10 to a portion of the second main surface TS2.

[0132] At the same time, it is preferable that dipping is performed so that the conductive paste that will become the first side surface side base electrode layer 521A of the first base electrode layer 50A is arranged extending from the first end face LS1 of the laminate 10 to a portion of the first side surface WS1, and so that the conductive paste that will become the second side surface side base electrode layer 522A of the first base electrode layer 50A is arranged extending from the first end face LS1 of the laminate 10 to a portion of the second side surface WS2.

[0133] At the same time, it is preferable that dipping be performed so that the conductive paste that will become the first side surface side base electrode layer 521B of the second base electrode layer 50B is arranged extending from the second end face LS2 of the laminate 10 to a portion of the first side surface WS1, and so that the conductive paste that will become the second side surface side base electrode layer 522B of the second base electrode layer 50B is arranged extending from the second end face LS2 of the laminate 10 to a portion of the second side surface WS2.

[0134] The laminated chip before firing and the conductive paste applied to the laminated chip may be fired simultaneously. In this case, the fired layer is preferably formed by firing a material to which a ceramic material is added instead of a glass component. In this case, it is particularly preferable that the ceramic material added is the same type of ceramic material as that of the dielectric layer 20. In this case, the conductive paste is applied to the laminated chip before firing, and the laminated chip and the conductive paste applied to the laminated chip are fired simultaneously to form the laminate 10 with the fired layer. By forming the fired layer simultaneously with firing the laminate 10, the manufacturing process can be simplified.

[0135] Thereafter, the surfaces of the first base electrode layer 50A and the second base electrode layer 50B, which are formed as baked layers, are plated. In this embodiment, a first plating layer 60A is formed on the surface of the first base electrode layer 50A. Furthermore, a second plating layer 60B is formed on the surface of the second base electrode layer 50B. In this embodiment, a first Ni plating layer 61A is formed on the surface of the first base electrode layer 50A, and a first Sn plating layer 62A is formed on the surface of the first Ni plating layer 61A. Furthermore, in this embodiment, a second Ni plating layer 61B is formed on the surface of the second base electrode layer 50B, and a second Sn plating layer 62B is formed on the surface of the second Ni plating layer 61B.

[0136] Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which makes the process more complicated. Therefore, electrolytic plating is usually preferred. The Ni plating layer and the Sn plating layer are preferably formed sequentially, for example, by barrel plating.

[0137] Here, in order to obtain the groove-shaped recesses described above in each of the main surface side external electrodes and each of the side surface side external electrodes of the external electrode 40 as in the embodiment, for example, the following method can be mentioned.

[0138] 6A and 6B schematically illustrate the process of forming the base electrode layer in this method. First, as shown in FIG. 6A, a first conductive paste P that will become the base electrode layer is applied by dipping to the end of the laminate 10 in the longitudinal direction L. Then, the laminate is dried to volatilize the organic components. During this process, a difference in drying speed occurs between the thickly and thinly coated portions of the conductive paste P. Specifically, the thinly coated portions dry faster. This difference in drying speed induces capillary flow from the thick to the thin portions of the coating, causing the solid components to migrate toward the thinner portions of the coating. Specifically, by adjusting the composition of the conductive paste P and the drying conditions, the solid components of the conductive paste P dry while migrating toward the periphery of the end of the base electrode layer where the coating was thin (the periphery of the edge 560a in FIG. 5A) and toward the ridge of the laminate 10, as shown in FIG. 6B. As a result, recesses G and raised portions 710, 720 are formed, and the metal density of the recess-corresponding regions is reduced. These recesses G become the above-mentioned first main surface recesses 510A, second main surface recesses 520A, first side surface recesses 530A, second side surface recesses 540A, first main surface recesses 510B, second main surface recesses 520B, first side surface recesses 530B, and second side surface recesses 540B. The formation of recesses G and the metal density of the recess-corresponding regions are adjusted by adjusting the composition of the conductive paste P and the drying conditions.

[0139] Through the above manufacturing steps, the multilayer ceramic capacitor 1 is manufactured.

[0140] The configuration of the multilayer ceramic capacitor 1 is not limited to the configurations shown in Figures 1 to 4B. For example, the multilayer ceramic capacitor 1 may be a multilayer ceramic capacitor having a double structure, a triple structure, or a quadruple structure as shown in Figures 7A, 7B, and 7C.

[0141] The multilayer ceramic capacitor 1 shown in FIG. 7A is a double-structure multilayer ceramic capacitor 1, and includes, as the internal electrode layers 30, a first internal electrode layer 33 and a second internal electrode layer 34, as well as a floating internal electrode layer 35 that serves as a floating internal conductor layer that is not drawn out to either the first end face LS1 or the second end face LS2.

[0142] The multilayer ceramic capacitor 1 shown in FIG. 7B is a triple-structure multilayer ceramic capacitor 1 including a first floating internal electrode layer 35A and a second floating internal electrode layer 35B as the floating internal electrode layers 35.

[0143] The multilayer ceramic capacitor 1 shown in FIG. 7C is a four-layer structure multilayer ceramic capacitor 1 having, as the floating internal electrode layers 35, a first floating internal electrode layer 35A, a second floating internal electrode layer 35B, and a third floating internal electrode layer 35C.

[0144] In this way, by providing the floating internal electrode layers 35 as the internal electrode layers 30, the multilayer ceramic capacitor 1 has a structure in which the opposing electrode portion is divided into multiple parts. As a result, multiple capacitor components are formed between the opposing internal electrode layers 30, and these capacitor components are connected in series. Therefore, the voltage applied to each capacitor component is reduced, and the multilayer ceramic capacitor 1 can have a high withstand voltage. It goes without saying that the multilayer ceramic capacitor 1 of the embodiment may have a multi-connection structure of four or more.

[0145] In the multilayer ceramic capacitor 1 having the structure shown in Figures 7A, 7B, and 7C, as in the above-mentioned embodiment, the first external electrode 40A has a first main surface side recess 510A and a second main surface side recess 520A, and the second external electrode 40B has a first main surface side recess 510B and a second main surface side recess 520B.

[0146] In the multilayer ceramic capacitor 1 having the structure shown in Figures 7A, 7B, and 7C, as in the above-mentioned embodiment, the first external electrode 40A may have a first side surface recess 530A and a second side surface recess 540A, and the second external electrode 40B may have a first side surface recess 530B and a second side surface recess 540B.

[0147] In particular, even in multilayer ceramic capacitors 1 having a two-, three-, or four-structure having floating internal electrode layers 35 as shown in Figures 7A to 7C, by providing recesses (first main surface side recesses, second main surface side recesses) in the main surface side external electrodes as in the embodiment and making the metal density of the recess corresponding regions 550 lower than the metal density of the peripheral regions (inner peripheral region 560 and outer peripheral region 570), it is possible to improve the resistance to flexing as described above, and as a result, the occurrence of cracks, etc. in the laminate 10 is suppressed.

[0148] The multilayer ceramic capacitor 1 according to the embodiment described above provides the following advantages.

[0149] (1) The multilayer ceramic capacitor 1 according to the embodiment includes a laminate 10 including dielectric layers 20 as a plurality of ceramic layers alternately stacked in a stacking direction T and internal electrode layers 30 as a plurality of internal conductor layers, the laminate 10 including a first main surface TS1 and a second main surface TS2 facing the stacking direction T, a first end face LS1 and a second end face LS2 facing a length direction L perpendicular to the stacking direction T, and a first side surface WS1 and a second side surface WS2 facing a width direction W perpendicular to the stacking direction T and the length direction L, and a pair of spaced apart metal layers 11 and 12 at both ends of the length direction L of the laminate 10. The external electrode 40 includes a pair of external electrodes 40 arranged on the first and second main surfaces TS1 and TS2, respectively, and the internal electrode layer 30 includes a first internal electrode layer 31 as a first internal conductor layer drawn to the first end face LS1 and a second internal electrode layer 32 as a second internal conductor layer drawn to the second end face LS2, and the external electrodes 40 include a first main surface side external electrode 411A and a second main surface side external electrode 412A as main surface side external electrodes, and a first main surface side external electrode 411B and a second main surface side external electrode 412B as main surface side external electrodes arranged on the first and second main surfaces TS1 and TS2, respectively, and the first main surface side external electrode 411A and the second main surface side external electrode 412A, and the first main surface side external electrode 411B and the second main surface side external electrode 412B are formed on the first main surface side base electrode layer 511A and the second main surface side base electrode layer 512A, and the first main surface side base electrode layer 511B and the second main surface side base electrode layer 512B as main surface side base electrode layers, and the first main surface side plating layer formed on the first main surface side base electrode layer 511A and the second main surface side base electrode layer 512A, and the first main surface side base electrode layer 511B and the second main surface side base electrode layer 512B as main surface side plating layers, respectively. a first main surface side plating layer (611A) and a second main surface side plating layer (612A), and a first main surface side plating layer (611B) and a second main surface side plating layer (612B), and the first main surface side external electrode (411A) and the second main surface side external electrode (412A), and the first main surface side external electrode (411B) and the second main surface side external electrode (412B) each have a first main surface side recess (510A) and a second main surface side recess (520A), and a first main surface side recess (510B) and a second main surface side recess (520B) as recesses recessed toward the laminate (10) side in a cross-sectional view along the stacking direction (T) and the length direction (L);Each of the first and second main surface side base electrode layers 511A, 512A, 511B, 512B has a recess-corresponding region 550 corresponding to the first and second main surface side recesses 510A, 520A, 510B, 520B, respectively, and an inner peripheral region 560 and an outer peripheral region 570 as peripheral regions adjacent to the recess-corresponding region 550 in the length direction L, and the metal density of the recess-corresponding region 550 is lower than the metal density of the inner peripheral region 560 and the outer peripheral region 570.

[0150] This allows the multilayer ceramic capacitor 1 according to the embodiment to have improved resistance to bending when mounted on a substrate, and as a result, the occurrence of cracks and the like in the laminate 10 is suppressed.

[0151] (2) In the multilayer ceramic capacitor 1 according to the embodiment (1), the metal density of the recess corresponding region 550 is preferably 85% or less.

[0152] This makes it possible to improve resistance to bending when mounting on a substrate, and as a result, the occurrence of cracks and the like in the laminate 10 is suppressed.

[0153] (3) In the multilayer ceramic capacitor 1 according to the embodiment (1), the metal density of the recess corresponding region 550 is preferably 60% or more and 85% or less.

[0154] This makes it possible to improve resistance to bending when mounting on a substrate, and as a result, the occurrence of cracks and the like in the laminate 10 is suppressed.

[0155] (4) In the multilayer ceramic capacitor 1 according to the above embodiment (1) or (2), the internal electrode layer 30 includes a configuration having a floating internal electrode layer 35 as a floating internal conductor layer that is not extended to either the first end face LS1 or the second end face LS2 and faces at least one of the first internal electrode layer 31 and the second internal electrode layer 32 across the dielectric layer 20.

[0156] This allows the multilayer ceramic capacitor 1 to have a high withstand voltage.

[0157] The multilayer ceramic capacitor 1 of the embodiment may include a configuration in which each of the first external electrode 40A and the second external electrode 40B includes a side surface side external electrode, which also has a recess similar to that of the main surface side external electrode, and the metal density of the recess corresponding region in the base electrode layer of the side surface side external electrode is lower than the metal density of the surrounding region of the recess corresponding region.

[0158] That is, the multilayer ceramic capacitor 1 of the embodiment includes a laminate 10 including dielectric layers 20 as a plurality of ceramic layers alternately stacked in a stacking direction T and internal electrode layers 30 as a plurality of internal conductor layers, and including a first main surface TS1 and a second main surface TS2 facing the stacking direction T, a first end face LS1 and a second end face LS2 facing a length direction L perpendicular to the stacking direction T, and a first side surface WS1 and a second side surface WS2 facing a width direction W perpendicular to the stacking direction T and the length direction L; a pair of external electrodes 40 arranged at a distance from each other at both ends of the laminate 10 in the longitudinal direction L, The internal conductor layer is a first internal electrode layer 31 as a first internal conductor layer drawn to the first end face LS1; a second internal electrode layer 32 as a second internal conductor layer drawn to the second end face LS2, The external electrode 40 is a side-side external electrode disposed on at least one of the first side surface WS1 and the second side surface WS2; The side surface side external electrode includes a side surface side base electrode layer, a side surface-side plating layer formed above the side surface-side base electrode layer, The side surface side external electrode is In a cross-sectional view along the width direction W and the length direction L, the laminate 10 has a recessed portion recessed toward the laminate 10, The side surface side base electrode layer is a recess-corresponding region corresponding to the recess; a peripheral region adjacent to the recessed portion corresponding region in the length direction L, The metal density in the recess-corresponding region is lower than the metal density in the surrounding region.

[0159] The present invention is not limited to the configurations of the above-described embodiments, and can be appropriately modified and applied within the scope of the present invention. Note that the present invention also includes a combination of two or more of the individual desirable configurations described in the above-described embodiments.

[0160] For example, the multilayer ceramic capacitor 1 may be a two-terminal type having two external electrodes, or a multi-terminal type having many external electrodes.

[0161] In the above-described embodiment, a multilayer ceramic capacitor using a dielectric ceramic is exemplified as a multilayer ceramic electronic component, but the multilayer ceramic electronic component of the present disclosure is not limited to this and can be applied to various other multilayer ceramic electronic components such as piezoelectric components using piezoelectric ceramic, thermistors using semiconductor ceramic, inductors using magnetic ceramic, etc. Examples of piezoelectric ceramics include PZT (lead zirconate titanate) ceramics, examples of semiconductor ceramics include spinel ceramics, and examples of magnetic ceramics include ferrite. [Example]

[0162] Examples are described below. According to the manufacturing method described in the above embodiment, multilayer ceramic capacitors in which the first external electrode and the second external electrode each have a first main surface recess and a second main surface recess, and the metal density in the recess-corresponding region is different from the metal density in the inner peripheral region and the outer peripheral region, were fabricated in lots as samples of Examples 1 and 2 shown in Table 1. The samples within each lot were manufactured under the same manufacturing conditions. For each example, 20 samples for metal density measurement and 30 samples for substrate bending resistance test were taken from the same lot and prepared. The metal density measurement was evaluated using the average value of the measurement results. The metal density was measured according to the measurement method of the above embodiment.

[0163] In manufacturing, each multilayer ceramic capacitor was fabricated according to the following specifications.

[0164] - Dimensions of multilayer ceramic capacitor: L×W×T=1.6mm×0.8mm×0.8mm Dielectric layer: BaTiO3 ·Capacity: 10μF Rated voltage: 25V Base electrode layer: Electrode containing conductive metal (Cu) and glass components (thickness of the base electrode layer placed on each of the first and second end faces: 36 μm) Plated layer: Two layers formed: Ni plated layer (2 μm) and Sn plated layer (4 μm) ·Internal electrode layer: Ni

[0165] On the other hand, multilayer ceramic capacitors in which neither the external electrode nor the second external electrode had a first main surface side recess nor a second main surface side recess were fabricated as samples of Comparative Examples 1, 2, and 3 shown in Table 1, and the same number of samples as in the Examples were prepared for each.

[0166] Furthermore, a multilayer ceramic capacitor in which the first external electrode and the second external electrode each had a first main surface side recess and a second main surface side recess, but the metal density in the recess-corresponding region was not lower than the metal density in the surrounding region, was fabricated as Comparative Example 4 shown in Table 1, and the same number of samples as in the Examples were prepared.

[0167] A substrate bending resistance test, which reflects the bending resistance, was carried out on each of the multilayer ceramic capacitors of Examples 1 and 2 and Comparative Examples 1 to 4, and the results were evaluated. Table 1 shows the evaluation results.

[0168] The outline of the board bending resistance test is as follows: A multilayer ceramic capacitor is mounted on a glass cloth-based epoxy resin printed wiring board. A push rod is pressed against the backside of the mounted surface to perform three-point bending, and the multilayer ceramic capacitor is checked for cracks. A load is applied to the center of the test piece at a rate of 1.0 mm / sec, and the load is held for 5 ± 1 seconds after the specified deflection is reached. In accordance with JIS C 60069-2-21, the load is held for 20 ± 1 seconds. Defect detection is based on the assumption that no cracks have occurred. A capacitor with a capacitance change rate that does not meet the individual specifications is also considered defective. If a crack occurs before the specified bending amount is reached, the capacitor is deemed defective at that point. Next, a visual inspection and cross-section polishing are performed to confirm the absence of cracks or other defects. Evaluation criteria were as follows: A: all chips were good; B: one to three defective chips; and C: four or more defective chips.

[0169] [Table 1]

[0170] According to Table 1, in Comparative Examples 1 and 2, the metal density in the central region in the length direction of the main surface side external electrode was lower than the metal density in the surrounding region, but the main surface side external electrode did not have any recesses, so the flexure resistance was not good. In Comparative Example 3, the metal density in the approximately central region in the length direction of the main surface side external electrode was not lower than the metal density in the surrounding region, and furthermore the main surface side external electrode did not have any recesses, so the flexure resistance was not good. In Comparative Example 4, the main surface side external electrode had a recess, but the metal density in the recessed region (approximately the central region in the length direction of the main surface side external electrode) was higher than the metal density in the surrounding region, so the flexure resistance was not good.

[0171] In contrast, Examples 1 and 2 had good resistance to bending because the main surface side external electrode had a recess and the metal density in the recessed area (approximately the central area in the longitudinal direction of the main surface side external electrode) was lower than the metal density in the surrounding area. Therefore, it is clear that not only having a recess but also having the condition that the metal density in the area corresponding to the recessed area is lower than the metal density in the surrounding area is effective in improving resistance to bending. [Explanation of symbols]

[0172] 1. Multilayer ceramic capacitors (multilayer ceramic electronic components) 10 Laminate 20 Dielectric layer (ceramic layer) 30 Internal electrode layer (internal conductor layer) 31 First internal electrode layer (first internal conductor layer) 32 Second internal electrode layer (second internal conductor layer) 35 Floating internal electrode layer (floating internal conductor layer) 40 External electrode 400A First end face side external electrode (end face side external electrode) 400B Second end face side external electrode (end face side external electrode) 411A First main surface side external electrode (main surface side external electrode) 411B First main surface side external electrode (main surface side external electrode) 412A Second main surface side external electrode (main surface side external electrode) 412B Second main surface side external electrode (main surface side external electrode) 510A First main surface side recess (recess) 510B First main surface side recess (recess) 511A First main surface side base electrode layer (main surface side base electrode layer) 511B First main surface side base electrode layer (main surface side base electrode layer) 512A Second main surface side base electrode layer (main surface side base electrode layer) 512B Second principal surface side base electrode layer (principal surface side base electrode layer) 520A Second main surface recess (recess) 520B Second main surface side recess (recess) 550 recessed area 560 Inner peripheral area (peripheral area) 570 Outer peripheral area (peripheral area) 611A First main surface side plating layer (main surface side plating layer) 611B First main surface side plating layer (main surface side plating layer) 612A Second main surface side plating layer (main surface side plating layer) 612B Second main surface side plating layer (main surface side plating layer) L lengthwise T Stacking direction W width direction LS1 First end face LS2 Second end face TS1 First principal surface TS2 Second principal surface WS1 First Aspect WS2 Second Aspect

Claims

1. a laminate including a plurality of ceramic layers and a plurality of internal conductor layers alternately stacked in a stacking direction, and including a first main surface and a second main surface opposing each other in the stacking direction, a first end face and a second end face opposing each other in a length direction perpendicular to the stacking direction, and a first side face and a second side face opposing each other in a width direction perpendicular to the stacking direction and the length direction; a pair of external electrodes disposed at opposite ends of the laminate in the longitudinal direction and spaced apart from each other; The internal conductor layer is a first internal conductor layer extending to the first end face; a second internal conductor layer extending to the second end surface, The external electrode is a main surface side external electrode disposed on at least one of the first main surface and the second main surface, The main surface side external electrode is a main surface-side base electrode layer; a main surface-side plating layer formed above the main surface-side base electrode layer, The main surface side external electrode is a recessed portion recessed toward the stacked body in a cross-sectional view along the stacking direction and the length direction, The main surface side base electrode layer is a recess-corresponding region corresponding to the recess; a peripheral region adjacent to the recess-corresponding region in the length direction, The metal density in the recess-corresponding region is lower than the metal density in the peripheral region.

2. 2. The multilayer ceramic electronic component according to claim 1, wherein the metal density of the recess-corresponding region is 85% or less.

3. 2. The multilayer ceramic electronic component according to claim 1, wherein the metal density of the recess-corresponding region is 60% or more and 85% or less.

4. 3. The multilayer ceramic electronic component according to claim 1, wherein the internal conductor layers include floating internal conductor layers that are not extended to either the first end face or the second end face and that face at least one of the first internal conductor layers and the second internal conductor layers with the ceramic layers interposed therebetween.

Images